forked from xuos/xiuos
add imxrt1176-sbc board for xizi from Wang_weigen
it is OK
This commit is contained in:
xuedongliang
commit
944225b7ad
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@ -5,8 +5,10 @@ MAKEFLAGS += --no-print-directory
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.PHONY:COMPILE_APP COMPILE_KERNEL
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.PHONY:COMPILE_APP COMPILE_KERNEL
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support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103-rvstar cortex-m0-emulator rv32m1-vega nuvoton-m2354
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riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64
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support += xidatong-arm32 xidatong-riscv64
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arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32
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emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator
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support := $(riscv_support) $(arm_support) $(emulator_support)
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SRC_DIR :=
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SRC_DIR :=
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export BOARD ?=kd233
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export BOARD ?=kd233
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@ -16,7 +18,10 @@ export KCONFIG_CONFIG ?= .config
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ifeq ($(filter $(BOARD),$(support)),)
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ifeq ($(filter $(BOARD),$(support)),)
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$(warning "You should choose board like this:make BOARD=kd233")
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$(warning "You should choose board like this:make BOARD=kd233")
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$(warning "This is what we support:")
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$(warning "This is what we support:")
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$(warning "$(support)")
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$(warning "RISCV EVB: $(riscv_support)")
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$(warning "ARM EVB: $(arm_support)")
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$(warning "EMULATORS: $(emulator_support)")
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# $(warning "$(support)")
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$(error "break" )
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$(error "break" )
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endif
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endif
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@ -30,6 +30,11 @@ SRC_DIR := shared
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SRC_DIR += cortex-m7
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SRC_DIR += cortex-m7
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endif
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endif
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ifeq ($(CONFIG_BOARD_IMXRT1176_SBC_EVB),y)
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SRC_DIR := shared
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SRC_DIR += cortex-m7
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endif
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# cortex-m0 is ARMv6-m
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# cortex-m0 is ARMv6-m
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ifeq ($(CONFIG_BOARD_CORTEX_M0_EVB),y)
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ifeq ($(CONFIG_BOARD_CORTEX_M0_EVB),y)
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@ -0,0 +1,58 @@
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mainmenu "XiZi Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config KERNEL_DIR
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string
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option env="KERNEL_ROOT"
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default "../.."
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config BOARD_IMXRT1176_SBC_EVB
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bool
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select ARCH_ARM
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default y
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source "$KERNEL_DIR/arch/Kconfig"
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menu "imxrt1176-sbc feature"
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source "$BSP_DIR/third_party_driver/Kconfig"
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menu "config default board resources"
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menu "config board app name"
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config BOARD_APP_NAME
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string "config board app name"
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default "/XiUOS_imxrt1176_sbc_app.bin"
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endmenu
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menu "config board service table"
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config SERVICE_TABLE_ADDRESS
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hex "board service table address"
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default 0x2007F0000
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endmenu
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endmenu
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config __STACKSIZE__
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int "stack size for interrupt"
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default 4096
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menu "config board peripheral"
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config MOUNT_SDCARD
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bool "mount cd card"
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default n
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endmenu
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endmenu
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menu "Hardware feature"
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source "$KERNEL_DIR/resources/Kconfig"
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endmenu
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source "$KERNEL_DIR/Kconfig"
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@ -0,0 +1,5 @@
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SRC_DIR := third_party_driver xip
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SRC_FILES := board.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,172 @@
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# 从零开始构建矽璓工业物联操作系统：使用ARM架构的imxrt1176-sbc
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# imxrt1176-sbc
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[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
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## 1. 简介
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| 硬件 | 描述 |
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| -- | -- |
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|芯片型号| MIMXRT1176 |
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|架构| cortex-m7 + cortex-m4 |
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|主频| M7@1GHz m4@400MHz |
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|片内SRAM| M7:512KB / M4:256KB shared with TCM |
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|外设支持| UART GPIO I2C RTC SDIO SEMC SPI USB ADC|
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XiUOS板级当前支持使用UART。
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## 2. 开发环境搭建
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### 推荐使用：
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**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
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更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
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第一步:打开sources.list文件
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```c
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sudo vim /etc/apt/sources.list
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```
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第二步:将以下内容复制到sources.list文件
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```c
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deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
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||||||
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deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
|
||||||
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deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
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||||||
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
|
||||||
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
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||||||
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
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```
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第三步:更新源和系统软件
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```c
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sudo apt-get update
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sudo apt-get upgrade
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```
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||||||
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**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
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### 依赖包安装：
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```
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$ sudo apt install build-essential pkg-config git
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$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
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```
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**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
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新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
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```c
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mkdir test && cd test
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git clone https://gitlink.org.cn/xuos/xiuos.git
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```
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1、打开XiUOS源码文件包可以看到以下目录：
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| 名称 | 说明 |
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| -- | -- |
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| APP_Framework | 应用代码 |
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| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
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2、打开XiZi内核源码文件包可以看到以下目录：
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| 名称 | 说明 |
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| -- | -- |
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| arch | 架构代码 |
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| board | 板级支持包 |
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| fs | 文件系统 |
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| kernel | 内核源码 |
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| lib | 第三方库源码 |
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| resources | 驱动文件 |
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| tool | 系统工具 |
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使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
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<div align= "center">
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<img src = ./img/vscode.jpg width =1000>
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</div>
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### 裁减配置工具的下载
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裁减配置工具：
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**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
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```c
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mkdir kfrontends && cd kfrontends
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git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
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```
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下载源码后按以下步骤执行软件安装：
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```c
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cd kconfig-frontends
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./xs_build.sh
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```
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### 编译工具链：
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ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
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```shell
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$ sudo apt install gcc-arm-none-eabi
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```
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## 编译说明
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### 编辑环境：`Ubuntu18.04`
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### 编译工具链：`arm-none-eabi-gcc`
|
||||||
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使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
|
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编译步骤：
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1.在VScode命令终端中执行以下命令，生成配置文件
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||||||
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```c
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cd ./Ubiquitous/XiZi
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make BOARD=imxrt1176-sbc distclean
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make BOARD=imxrt1176-sbc menuconfig
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```
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2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
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退出时选择`yes`保存上面所配置的内容，如下图所示：
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3.继续执行以下命令，进行编译
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```
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make BOARD=imxrt1176-sbc
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||||||
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```
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4.如果编译正确无误，会产生XiZi-imxrt1176-sbc.elf、XiZi-imxrt1176-sbc.bin文件。
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||||||
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## 3. 烧写及运行
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### 3.1 烧写
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1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility)
|
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||||||
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2、imxrt1176-sbc开发板支持串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT117x，开发板上电，使用usb线将开发板和PC连接，使用串口调试小板连接开发板调试串口的发送和接收管脚，启动管脚连接“serial download”，并按下复位管脚使得MCU进入下载模式。如下图所示：
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||||||
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3、同时需要匹配imxrt1176-sbc开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择ISSI_IS26KSxxxS_IS26KLxxxS，然后点击ok。点击connect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。选择编译生成的XiZi-imxrt1176-sbc.elf,点击ALL-In-One-Action按钮烧写，等待烧写完成
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||||||
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如下图所示：
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||||||
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||||||
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||||||
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||||||
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### 3.2 运行结果
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||||||
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1、烧写完成后，启动管脚连接“Interal Boot”，按下复位键后，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示：
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@ -0,0 +1,420 @@
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||||||
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/*
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||||||
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* Copyright 2017 NXP
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||||||
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* All rights reserved.
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||||||
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*
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||||||
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* SPDX-License-Identifier: BSD-3-Clause
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||||||
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*/
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||||||
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||||||
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/**
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||||||
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* @file board.c
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||||||
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* @brief relative configure for xidatong-arm32
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||||||
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* @version 2.0
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||||||
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* @author AIIT XUOS Lab
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||||||
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* @date 2022.03.15
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||||||
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*/
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||||||
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|
||||||
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/*************************************************
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||||||
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File name: board.c
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||||||
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Description: support imxrt1176-board init function
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||||||
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Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
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||||||
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History:
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||||||
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1. Date: 2022-08-19
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Author: AIIT XUOS Lab
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||||||
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Modification:
|
||||||
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1. support imxrt1176-board MPU、clock、memory init
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||||||
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2. support imxrt1176-board uart、sdio driver init
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||||||
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*************************************************/
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||||||
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||||||
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#include <board.h>
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||||||
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||||||
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#ifdef BSP_USING_GPIO
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||||||
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#include <connect_gpio.h>
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||||||
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#endif
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||||||
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|
||||||
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#ifdef BSP_USING_LPUART
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||||||
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#include <connect_uart.h>
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||||||
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#endif
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||||||
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|
||||||
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#if __CORTEX_M == 7
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||||||
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void BOARD_ConfigMPU(void)
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||||||
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{
|
||||||
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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||||||
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extern uint32_t Image$$RW_m_ncache$$Base[];
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||||||
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/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
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||||||
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extern uint32_t Image$$RW_m_ncache_unused$$Base[];
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||||||
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extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||||
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uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||||
|
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||||
|
0 :
|
||||||
|
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||||
|
#elif defined(__MCUXPRESSO)
|
||||||
|
#if defined(__USE_SHMEM)
|
||||||
|
extern uint32_t __base_rpmsg_sh_mem;
|
||||||
|
extern uint32_t __top_rpmsg_sh_mem;
|
||||||
|
uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem);
|
||||||
|
uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart;
|
||||||
|
#else
|
||||||
|
extern uint32_t __base_NCACHE_REGION;
|
||||||
|
extern uint32_t __top_NCACHE_REGION;
|
||||||
|
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||||
|
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||||
|
#endif
|
||||||
|
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||||
|
extern uint32_t __NCACHE_REGION_START;
|
||||||
|
extern uint32_t __NCACHE_REGION_END;
|
||||||
|
uint32_t nonCacheStart = (uint32_t)(&__NCACHE_REGION_START);
|
||||||
|
uint32_t size = (uint32_t)(&__NCACHE_REGION_END) - nonCacheStart;
|
||||||
|
#endif
|
||||||
|
volatile uint32_t i = 0;
|
||||||
|
|
||||||
|
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
|
||||||
|
/* Disable I cache and D cache */
|
||||||
|
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||||
|
{
|
||||||
|
SCB_DisableICache();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
|
||||||
|
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||||
|
{
|
||||||
|
SCB_DisableDCache();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Disable MPU */
|
||||||
|
ARM_MPU_Disable();
|
||||||
|
|
||||||
|
/* MPU configure:
|
||||||
|
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||||
|
* SubRegionDisable, Size)
|
||||||
|
* API in mpu_armv7.h.
|
||||||
|
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||||
|
* disabled.
|
||||||
|
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||||
|
* Privileged mode.
|
||||||
|
* Use MACROS defined in mpu_armv7.h:
|
||||||
|
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||||
|
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||||
|
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||||
|
* 0 x 0 0 Strongly Ordered shareable
|
||||||
|
* 0 x 0 1 Device shareable
|
||||||
|
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||||
|
* through no write allocate
|
||||||
|
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||||
|
* back no write allocate
|
||||||
|
* 0 1 1 0 Normal shareable Outer and inner write
|
||||||
|
* through no write allocate
|
||||||
|
* 0 1 1 1 Normal shareable Outer and inner write
|
||||||
|
* back no write allocate
|
||||||
|
* 1 0 0 0 Normal not shareable outer and inner
|
||||||
|
* noncache
|
||||||
|
* 1 1 0 0 Normal shareable outer and inner
|
||||||
|
* noncache
|
||||||
|
* 1 0 1 1 Normal not shareable outer and inner write
|
||||||
|
* back write/read acllocate
|
||||||
|
* 1 1 1 1 Normal shareable outer and inner write
|
||||||
|
* back write/read acllocate
|
||||||
|
* 2 x 0 0 Device not shareable
|
||||||
|
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||||
|
* policy.
|
||||||
|
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||||
|
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||||
|
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||||
|
* mpu_armv7.h.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||||||
|
* Refer to Arm errata 1013783-B for more details.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||||||
|
|
||||||
|
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||||
|
|
||||||
|
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||||
|
|
||||||
|
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||||
|
|
||||||
|
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||||
|
|
||||||
|
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||||
|
|
||||||
|
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
|
||||||
|
|
||||||
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
|
||||||
|
|
||||||
|
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||||
|
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef USE_SDRAM
|
||||||
|
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
while ((size >> i) > 0x1U)
|
||||||
|
{
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i != 0)
|
||||||
|
{
|
||||||
|
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||||
|
assert(!(nonCacheStart % size));
|
||||||
|
assert(size == (uint32_t)(1 << i));
|
||||||
|
assert(i >= 5);
|
||||||
|
|
||||||
|
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
|
||||||
|
|
||||||
|
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||||
|
|
||||||
|
/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
|
||||||
|
|
||||||
|
/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||||
|
|
||||||
|
/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
|
||||||
|
|
||||||
|
/* Enable MPU */
|
||||||
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||||
|
|
||||||
|
/* Enable I cache and D cache */
|
||||||
|
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
|
||||||
|
SCB_EnableDCache();
|
||||||
|
#endif
|
||||||
|
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
|
||||||
|
SCB_EnableICache();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#elif __CORTEX_M == 4
|
||||||
|
void BOARD_ConfigMPU(void)
|
||||||
|
{
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||||
|
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
|
||||||
|
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
|
||||||
|
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||||
|
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||||
|
uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||||
|
0 :
|
||||||
|
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||||
|
#elif defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t __base_NCACHE_REGION;
|
||||||
|
extern uint32_t __top_NCACHE_REGION;
|
||||||
|
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||||
|
uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||||
|
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||||
|
extern uint32_t __NCACHE_REGION_START[];
|
||||||
|
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||||
|
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||||
|
uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
|
||||||
|
#endif
|
||||||
|
#if defined(__USE_SHMEM)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
|
||||||
|
/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
|
||||||
|
extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
|
||||||
|
extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
|
||||||
|
uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
|
||||||
|
uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
|
||||||
|
#elif defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t __base_rpmsg_sh_mem;
|
||||||
|
extern uint32_t __top_rpmsg_sh_mem;
|
||||||
|
uint32_t rpmsgShmemStart = (uint32_t)(&__base_rpmsg_sh_mem);
|
||||||
|
uint32_t rpmsgShmemSize = (uint32_t)(&__top_rpmsg_sh_mem) - rpmsgShmemStart;
|
||||||
|
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||||
|
extern uint32_t __RPMSG_SH_MEM_START[];
|
||||||
|
extern uint32_t __RPMSG_SH_MEM_SIZE[];
|
||||||
|
uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
|
||||||
|
uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
uint32_t i = 0;
|
||||||
|
|
||||||
|
/* Only config non-cacheable region on system bus */
|
||||||
|
assert(nonCacheStart >= 0x20000000);
|
||||||
|
|
||||||
|
/* Disable code bus cache */
|
||||||
|
if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))
|
||||||
|
{
|
||||||
|
/* Enable the processor code bus to push all modified lines. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
|
||||||
|
/* Now disable the cache. */
|
||||||
|
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable system bus cache */
|
||||||
|
if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))
|
||||||
|
{
|
||||||
|
/* Enable the processor system bus to push all modified lines. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
|
||||||
|
/* Now disable the cache. */
|
||||||
|
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable MPU */
|
||||||
|
ARM_MPU_Disable();
|
||||||
|
|
||||||
|
while ((nonCacheSize >> i) > 0x1U)
|
||||||
|
{
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i != 0)
|
||||||
|
{
|
||||||
|
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||||
|
assert(!(nonCacheStart % nonCacheSize));
|
||||||
|
assert(nonCacheSize == (uint32_t)(1 << i));
|
||||||
|
assert(i >= 5);
|
||||||
|
|
||||||
|
/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(__USE_SHMEM)
|
||||||
|
i = 0;
|
||||||
|
|
||||||
|
while ((rpmsgShmemSize >> i) > 0x1U)
|
||||||
|
{
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i != 0)
|
||||||
|
{
|
||||||
|
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||||
|
assert(!(rpmsgShmemStart % rpmsgShmemSize));
|
||||||
|
assert(rpmsgShmemSize == (uint32_t)(1 << i));
|
||||||
|
assert(i >= 5);
|
||||||
|
|
||||||
|
/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
|
||||||
|
MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
|
||||||
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable MPU */
|
||||||
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||||
|
|
||||||
|
/* Enables the processor system bus to invalidate all lines in both ways.
|
||||||
|
and Initiate the processor system bus cache command. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
|
||||||
|
/* Wait until the cache command completes */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
|
||||||
|
/* Now enable the system bus cache. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
|
||||||
|
|
||||||
|
/* Enables the processor code bus to invalidate all lines in both ways.
|
||||||
|
and Initiate the processor code bus code cache command. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
|
||||||
|
/* Now enable the code bus cache. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This is the timer interrupt service routine. */
|
||||||
|
void SysTick_Handler(int irqn, void *arg)
|
||||||
|
{
|
||||||
|
TickAndTaskTimesliceUpdate();
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
|
||||||
|
|
||||||
|
struct InitSequenceDesc _board_init[] =
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_GPIO
|
||||||
|
// { "hw_pin", Imxrt1052HwGpioInit },
|
||||||
|
#endif
|
||||||
|
|
||||||
|
{ " NONE ",NONE },
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initial imxrt1050 board.
|
||||||
|
*/
|
||||||
|
void InitBoardHardware()
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
BOARD_ConfigMPU();
|
||||||
|
BOARD_InitPins();
|
||||||
|
BOARD_BootClockRUN();
|
||||||
|
|
||||||
|
// NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||||
|
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
||||||
|
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
|
||||||
|
|
||||||
|
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART
|
||||||
|
Imxrt1176HwUartInit();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||||
|
KPrintf("\nconsole init completed.\n");
|
||||||
|
KPrintf("board initialization......\n");
|
||||||
|
|
||||||
|
for(i = 0; _board_init[i].fn != NONE; i++) {
|
||||||
|
ret = _board_init[i].fn();
|
||||||
|
KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed");
|
||||||
|
}
|
||||||
|
KPrintf("board init done.\n");
|
||||||
|
KPrintf("start kernel...\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||||
|
|
||||||
|
export CFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
|
||||||
|
export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||||
|
export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-imxrt1176-sbc.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||||
|
export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
|
||||||
|
|
||||||
|
# export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||||
|
|
||||||
|
export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS
|
||||||
|
|
||||||
|
export ARCH = arm
|
||||||
|
export MCU = cortex-m7
|
||||||
Binary file not shown.
|
After Width: | Height: | Size: 94 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 920 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 37 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 24 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 18 KiB |
|
|
@ -0,0 +1,76 @@
|
||||||
|
/**
|
||||||
|
* @file board.h
|
||||||
|
* @brief define imxrt1176-sbc-board init configure and start-up function
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2021-05-28
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: board.h
|
||||||
|
Description: define imxrt1176-sbc board init function and struct
|
||||||
|
Others:
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
1. define imxrt-board InitBoardHardware
|
||||||
|
2. define imxrt-board heap struct
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef __BOARD_H__
|
||||||
|
#define __BOARD_H__
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
// #include "fsl_enet.h"
|
||||||
|
#include "clock_config.h"
|
||||||
|
#include <xizi.h>
|
||||||
|
#include <arch_interrupt.h>
|
||||||
|
|
||||||
|
extern int heap_start;
|
||||||
|
extern int heap_end;
|
||||||
|
#define HEAP_BEGIN (&heap_start)
|
||||||
|
#define HEAP_END (&heap_end)
|
||||||
|
|
||||||
|
#define BOARD_FLASH_SIZE (0x1000000U)
|
||||||
|
|
||||||
|
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||||
|
|
||||||
|
|
||||||
|
void InitBoardHardware(void);
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/*! @brief The board name */
|
||||||
|
#define BOARD_NAME "IMXRT1050"
|
||||||
|
|
||||||
|
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||||
|
4 bits for subpriority */
|
||||||
|
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||||
|
3 bits for subpriority */
|
||||||
|
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||||
|
2 bits for subpriority */
|
||||||
|
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||||
|
1 bits for subpriority */
|
||||||
|
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/
|
||||||
|
|
||||||
|
/*! @brief The ENET PHY address. */
|
||||||
|
#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
void BOARD_ConfigMPU(void);
|
||||||
|
void BOARD_InitPins(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* _BOARD_H_ */
|
||||||
|
|
@ -0,0 +1,226 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file clock_config.c
|
||||||
|
* @brief support imxrt1176-sbc clock configure
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: clock_config.c
|
||||||
|
Description: support imxrt1176-sbc clock configure
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
#ifndef _CLOCK_CONFIG_H_
|
||||||
|
#define _CLOCK_CONFIG_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||||
|
|
||||||
|
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
************************ BOARD_InitBootClocks function ************************
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes default configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitBootClocks(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************** Configuration BOARD_BootClockRUN ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
|
||||||
|
#else
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Clock outputs (values are in Hz): */
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
|
||||||
|
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_BootClockRUN(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
#endif /* _CLOCK_CONFIG_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file dcd.h
|
||||||
|
* @brief support imxrt1176-sbc dcd
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: dcd.h
|
||||||
|
Description: support imxrt1176-sbc dcd
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef __DCD__
|
||||||
|
#define __DCD__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||||
|
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*************************************
|
||||||
|
* DCD Data
|
||||||
|
*************************************/
|
||||||
|
#define DCD_TAG_HEADER (0xD2)
|
||||||
|
#define DCD_VERSION (0x41)
|
||||||
|
#define DCD_TAG_HEADER_SHIFT (24)
|
||||||
|
#define DCD_ARRAY_SIZE 1
|
||||||
|
|
||||||
|
#endif /* __DCD__ */
|
||||||
|
|
@ -0,0 +1,287 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Processors: MIMXRT1052CVJ5B
|
||||||
|
** MIMXRT1052CVL5B
|
||||||
|
** MIMXRT1052DVJ6B
|
||||||
|
** MIMXRT1052DVL6B
|
||||||
|
**
|
||||||
|
** Compiler: GNU C Compiler
|
||||||
|
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||||
|
** Version: rev. 1.0, 2018-09-21
|
||||||
|
** Build: b180921
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Linker file for the GNU C Compiler
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2018 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file link.lds
|
||||||
|
* @brief ok1052-c board Linker script
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2021-05-28
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: link.lds
|
||||||
|
Description: ok1052-c board Linker script
|
||||||
|
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
|
||||||
|
History:
|
||||||
|
1. Date: 2021-05-28
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
1. add shell cmd table and g_service_table
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||||
|
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
/* define flash 32MB */
|
||||||
|
m_boot_data (RX) : ORIGIN = 0x30000000, LENGTH = 0x00001000
|
||||||
|
m_image_vertor_table (RX) : ORIGIN = 0x30001000, LENGTH = 0x00001000
|
||||||
|
m_interrupts (RX) : ORIGIN = 0x30002000, LENGTH = 0x00000400
|
||||||
|
m_text (RX) : ORIGIN = 0x30002400, LENGTH = 0x01FFDC00
|
||||||
|
|
||||||
|
/* define itcm 256KB */
|
||||||
|
sram_itcm_cm7 (rwx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias RAM2) */
|
||||||
|
|
||||||
|
/* define dtcm 256KB */
|
||||||
|
sram_dtcm_cm7 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 /* 256K bytes (alias RAM) */
|
||||||
|
|
||||||
|
/* define ocram1 512KB */
|
||||||
|
sram_oc1 (rwx) : ORIGIN = 0x20240000, LENGTH = 0x80000 /* 512K bytes (alias RAM3) */
|
||||||
|
|
||||||
|
/* define ocram2 256KB */
|
||||||
|
sram_oc2 (rwx) : ORIGIN = 0x202c0000, LENGTH = 0x40000 /* 256K bytes (alias RAM4) */
|
||||||
|
|
||||||
|
/* define nocache regin 256KB */
|
||||||
|
NCACHE_REGION (rwx) : ORIGIN = 0x20300000, LENGTH = 0x40000 /* 256K bytes (alias RAM5) */
|
||||||
|
|
||||||
|
/* define ocram ecc1 and ecc2 64KB */
|
||||||
|
sram_oc_ecc1 (rwx) : ORIGIN = 0x20340000, LENGTH = 0x10000 /* 64K bytes (alias RAM6) */
|
||||||
|
sram_oc_ecc2 (rwx) : ORIGIN = 0x20350000, LENGTH = 0x10000 /* 64K bytes (alias RAM7) */
|
||||||
|
|
||||||
|
/* define extern sdram 32MB*/
|
||||||
|
board_sdram (rwx) : ORIGIN = 0x80000000, LENGTH = 0x2000000 /* 64M bytes (alias RAM8) */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.boot_data :
|
||||||
|
{
|
||||||
|
KEEP(*(.boot_hdr.conf))
|
||||||
|
} > m_boot_data
|
||||||
|
|
||||||
|
.image_vertor_table :
|
||||||
|
{
|
||||||
|
KEEP(*(.boot_hdr.ivt))
|
||||||
|
KEEP(*(.boot_hdr.boot_data))
|
||||||
|
KEEP(*(.boot_hdr.dcd_data))
|
||||||
|
} > m_image_vertor_table
|
||||||
|
|
||||||
|
/* The startup code goes first into internal RAM */
|
||||||
|
.interrupts :
|
||||||
|
{
|
||||||
|
__VECTOR_TABLE = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > m_interrupts
|
||||||
|
|
||||||
|
__VECTOR_RAM = __VECTOR_TABLE;
|
||||||
|
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||||
|
|
||||||
|
/* The program code and other data goes into internal RAM */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
|
||||||
|
/* section information for shell */
|
||||||
|
. = ALIGN(4);
|
||||||
|
_shell_command_start = .;
|
||||||
|
KEEP (*(shellCommand))
|
||||||
|
_shell_command_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
__isrtbl_idx_start = .;
|
||||||
|
KEEP(*(.isrtbl.idx))
|
||||||
|
__isrtbl_start = .;
|
||||||
|
KEEP(*(.isrtbl))
|
||||||
|
__isrtbl_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||||
|
KEEP(*(.g_service_table))
|
||||||
|
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.ctors :
|
||||||
|
{
|
||||||
|
__CTOR_LIST__ = .;
|
||||||
|
/* gcc uses crtbegin.o to find the start of
|
||||||
|
the constructors, so we make sure it is
|
||||||
|
first. Because this is a wildcard, it
|
||||||
|
doesn't matter if the user does not
|
||||||
|
actually link against crtbegin.o; the
|
||||||
|
linker won't look for a file to match a
|
||||||
|
wildcard. The wildcard also means that it
|
||||||
|
doesn't matter which directory crtbegin.o
|
||||||
|
is in. */
|
||||||
|
KEEP (*crtbegin.o(.ctors))
|
||||||
|
KEEP (*crtbegin?.o(.ctors))
|
||||||
|
/* We don't want to include the .ctor section from
|
||||||
|
from the crtend.o file until after the sorted ctors.
|
||||||
|
The .ctor section from the crtend file contains the
|
||||||
|
end of ctors marker and it must be last */
|
||||||
|
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||||
|
KEEP (*(SORT(.ctors.*)))
|
||||||
|
KEEP (*(.ctors))
|
||||||
|
__CTOR_END__ = .;
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.dtors :
|
||||||
|
{
|
||||||
|
__DTOR_LIST__ = .;
|
||||||
|
KEEP (*crtbegin.o(.dtors))
|
||||||
|
KEEP (*crtbegin?.o(.dtors))
|
||||||
|
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||||
|
KEEP (*(SORT(.dtors.*)))
|
||||||
|
KEEP (*(.dtors))
|
||||||
|
__DTOR_END__ = .;
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} > m_text
|
||||||
|
|
||||||
|
__etext = .; /* define a global symbol at end of code */
|
||||||
|
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||||
|
|
||||||
|
.data : AT(__DATA_ROM)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__DATA_RAM = .;
|
||||||
|
__data_start__ = .; /* create a global symbol at data start */
|
||||||
|
*(m_usb_dma_init_data)
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
KEEP(*(.jcr*))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__data_end__ = .; /* define a global symbol at data end */
|
||||||
|
} > sram_dtcm_cm7
|
||||||
|
|
||||||
|
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||||
|
.ncache.init : AT(__NDATA_ROM)
|
||||||
|
{
|
||||||
|
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||||
|
__NCACHE_REGION_START = .;
|
||||||
|
*(NonCacheable.init)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||||
|
} > sram_dtcm_cm7
|
||||||
|
. = __noncachedata_init_end__;
|
||||||
|
.ncache :
|
||||||
|
{
|
||||||
|
*(NonCacheable)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||||
|
__NCACHE_REGION_END = .;
|
||||||
|
} > sram_dtcm_cm7
|
||||||
|
|
||||||
|
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||||
|
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||||
|
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__START_BSS = .;
|
||||||
|
__bss_start__ = .;
|
||||||
|
*(m_usb_dma_noninit_data)
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_end__ = .;
|
||||||
|
__END_BSS = .;
|
||||||
|
} > sram_dtcm_cm7
|
||||||
|
|
||||||
|
.stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
stack_start = .;
|
||||||
|
. += STACK_SIZE;
|
||||||
|
stack_end = .;
|
||||||
|
__StackTop = .;
|
||||||
|
heap_start = .;
|
||||||
|
} > sram_oc1
|
||||||
|
|
||||||
|
PROVIDE(heap_end = ORIGIN(sram_oc1) + LENGTH(sram_oc2) + LENGTH(NCACHE_REGION));
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,894 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_armcc.h
|
||||||
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. May 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ARMCC_H
|
||||||
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
/* CMSIS compiler control DSP macros */
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __ARM_FEATURE_DSP 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#define __COMPILER_BARRIER() __memory_changed()
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ######################### Startup and Lowlevel Init ######################## */
|
||||||
|
|
||||||
|
#ifndef __PROGRAM_START
|
||||||
|
#define __PROGRAM_START __main
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INITIAL_SP
|
||||||
|
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STACK_LIMIT
|
||||||
|
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE
|
||||||
|
#define __VECTOR_TABLE __Vectors
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||||
|
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Control Register
|
||||||
|
\details Returns the content of the Control Register.
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Control Register
|
||||||
|
\details Writes the given value to the Control Register.
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get IPSR Register
|
||||||
|
\details Returns the content of the IPSR Register.
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get APSR Register
|
||||||
|
\details Returns the content of the APSR Register.
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get xPSR Register
|
||||||
|
\details Returns the content of the xPSR Register.
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Process Stack Pointer
|
||||||
|
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Process Stack Pointer
|
||||||
|
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Main Stack Pointer
|
||||||
|
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Main Stack Pointer
|
||||||
|
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Priority Mask
|
||||||
|
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Priority Mask
|
||||||
|
\details Assigns the given value to the Priority Mask Register.
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable FIQ
|
||||||
|
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable FIQ
|
||||||
|
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Base Priority
|
||||||
|
\details Returns the current value of the Base Priority register.
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority
|
||||||
|
\details Assigns the given value to the Base Priority register.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority with condition
|
||||||
|
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||||
|
or the new value increases the BASEPRI priority level.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||||
|
__regBasePriMax = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Fault Mask
|
||||||
|
\details Returns the current value of the Fault Mask register.
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Fault Mask
|
||||||
|
\details Assigns the given value to the Fault Mask register.
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get FPSCR
|
||||||
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0U);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set FPSCR
|
||||||
|
\details Assigns the given value to the Floating Point Status/Control register.
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief No Operation
|
||||||
|
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Interrupt
|
||||||
|
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Event
|
||||||
|
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Send Event
|
||||||
|
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Instruction Synchronization Barrier
|
||||||
|
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or memory,
|
||||||
|
after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__isb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Synchronization Barrier
|
||||||
|
\details Acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dsb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Memory Barrier
|
||||||
|
\details Ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dmb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (32 bit)
|
||||||
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
\param [in] op1 Value to rotate
|
||||||
|
\param [in] op2 Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Breakpoint
|
||||||
|
\details Causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __breakpoint(value)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse bit order of value
|
||||||
|
\details Reverses the bit order of the given value.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __RBIT __rbit
|
||||||
|
#else
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
|
{
|
||||||
|
result <<= 1U;
|
||||||
|
result |= value & 1U;
|
||||||
|
s--;
|
||||||
|
}
|
||||||
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Count leading zeros
|
||||||
|
\details Counts the number of leading zeros of a data value.
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Remove the exclusive lock
|
||||||
|
\details Removes the exclusive lock which is created by LDREX.
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right with Extend (32 bit)
|
||||||
|
\details Moves each bit of a bitstring right by one bit.
|
||||||
|
The carry input is shifted in at the left end of the bitstring.
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
rrx r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ARMCC_H */
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 09. October 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6.6 LTM (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||||
|
#include "cmsis_armclang_ltm.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler above 6.10.1 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,964 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_iccarm.h
|
||||||
|
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. May 2019
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2017-2019 IAR Systems
|
||||||
|
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||||
|
//
|
||||||
|
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||||
|
// you may not use this file except in compliance with the License.
|
||||||
|
// You may obtain a copy of the License at
|
||||||
|
// http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, software
|
||||||
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
// See the License for the specific language governing permissions and
|
||||||
|
// limitations under the License.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ICCARM_H__
|
||||||
|
#define __CMSIS_ICCARM_H__
|
||||||
|
|
||||||
|
#ifndef __ICCARM__
|
||||||
|
#error This file should only be compiled by ICCARM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma system_include
|
||||||
|
|
||||||
|
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||||
|
|
||||||
|
#if (__VER__ >= 8000000)
|
||||||
|
#define __ICCARM_V8 1
|
||||||
|
#else
|
||||||
|
#define __ICCARM_V8 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#elif (__VER__ >= 7080000)
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#else
|
||||||
|
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||||
|
*/
|
||||||
|
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||||
|
/* Macros already defined */
|
||||||
|
#else
|
||||||
|
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||||
|
#if __ARM_ARCH == 6
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif __ARM_ARCH == 7
|
||||||
|
#if __ARM_FEATURE_DSP
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#else
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
#endif /* __ARM_ARCH */
|
||||||
|
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Alternativ core deduction for older ICCARM's */
|
||||||
|
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||||
|
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||||
|
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#else
|
||||||
|
#error "Unknown target."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#else
|
||||||
|
#define __IAR_M0_FAMILY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __NO_RETURN __attribute__((__noreturn__))
|
||||||
|
#else
|
||||||
|
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED __packed
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __RESTRICT restrict
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __FORCEINLINE
|
||||||
|
#define __FORCEINLINE _Pragma("inline=forced")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint16_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint16_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint32_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint32_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__packed struct __iar_u32 { uint32_t v; };
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __USED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#else
|
||||||
|
#define __USED _Pragma("__root")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __WEAK
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#else
|
||||||
|
#define __WEAK _Pragma("__weak")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PROGRAM_START
|
||||||
|
#define __PROGRAM_START __iar_program_start
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INITIAL_SP
|
||||||
|
#define __INITIAL_SP CSTACK$$Limit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STACK_LIMIT
|
||||||
|
#define __STACK_LIMIT CSTACK$$Base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE
|
||||||
|
#define __VECTOR_TABLE __vector_table
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||||
|
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||||
|
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||||
|
|
||||||
|
#if defined(__CLZ)
|
||||||
|
#undef __CLZ
|
||||||
|
#endif
|
||||||
|
#if defined(__REVSH)
|
||||||
|
#undef __REVSH
|
||||||
|
#endif
|
||||||
|
#if defined(__RBIT)
|
||||||
|
#undef __RBIT
|
||||||
|
#endif
|
||||||
|
#if defined(__SSAT)
|
||||||
|
#undef __SSAT
|
||||||
|
#endif
|
||||||
|
#if defined(__USAT)
|
||||||
|
#undef __USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "iccarm_builtin.h"
|
||||||
|
|
||||||
|
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||||
|
#define __disable_irq __iar_builtin_disable_interrupt
|
||||||
|
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||||
|
#define __enable_irq __iar_builtin_enable_interrupt
|
||||||
|
#define __arm_rsr __iar_builtin_rsr
|
||||||
|
#define __arm_wsr __iar_builtin_wsr
|
||||||
|
|
||||||
|
|
||||||
|
#define __get_APSR() (__arm_rsr("APSR"))
|
||||||
|
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||||
|
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||||
|
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||||
|
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||||
|
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||||
|
#else
|
||||||
|
#define __get_FPSCR() ( 0 )
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||||
|
#define __get_MSP() (__arm_rsr("MSP"))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __get_MSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||||
|
#endif
|
||||||
|
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||||
|
#define __get_PSP() (__arm_rsr("PSP"))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __get_PSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||||
|
|
||||||
|
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||||
|
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||||
|
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||||
|
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||||
|
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||||
|
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||||
|
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||||
|
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||||
|
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||||
|
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||||
|
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||||
|
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||||
|
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||||
|
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||||
|
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __TZ_get_PSPLIM_NS() (0U)
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||||
|
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||||
|
|
||||||
|
#define __NOP __iar_builtin_no_operation
|
||||||
|
|
||||||
|
#define __CLZ __iar_builtin_CLZ
|
||||||
|
#define __CLREX __iar_builtin_CLREX
|
||||||
|
|
||||||
|
#define __DMB __iar_builtin_DMB
|
||||||
|
#define __DSB __iar_builtin_DSB
|
||||||
|
#define __ISB __iar_builtin_ISB
|
||||||
|
|
||||||
|
#define __LDREXB __iar_builtin_LDREXB
|
||||||
|
#define __LDREXH __iar_builtin_LDREXH
|
||||||
|
#define __LDREXW __iar_builtin_LDREX
|
||||||
|
|
||||||
|
#define __RBIT __iar_builtin_RBIT
|
||||||
|
#define __REV __iar_builtin_REV
|
||||||
|
#define __REV16 __iar_builtin_REV16
|
||||||
|
|
||||||
|
__IAR_FT int16_t __REVSH(int16_t val)
|
||||||
|
{
|
||||||
|
return (int16_t) __iar_builtin_REVSH(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __ROR __iar_builtin_ROR
|
||||||
|
#define __RRX __iar_builtin_RRX
|
||||||
|
|
||||||
|
#define __SEV __iar_builtin_SEV
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __SSAT __iar_builtin_SSAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __STREXB __iar_builtin_STREXB
|
||||||
|
#define __STREXH __iar_builtin_STREXH
|
||||||
|
#define __STREXW __iar_builtin_STREX
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __USAT __iar_builtin_USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __WFE __iar_builtin_WFE
|
||||||
|
#define __WFI __iar_builtin_WFI
|
||||||
|
|
||||||
|
#if __ARM_MEDIA__
|
||||||
|
#define __SADD8 __iar_builtin_SADD8
|
||||||
|
#define __QADD8 __iar_builtin_QADD8
|
||||||
|
#define __SHADD8 __iar_builtin_SHADD8
|
||||||
|
#define __UADD8 __iar_builtin_UADD8
|
||||||
|
#define __UQADD8 __iar_builtin_UQADD8
|
||||||
|
#define __UHADD8 __iar_builtin_UHADD8
|
||||||
|
#define __SSUB8 __iar_builtin_SSUB8
|
||||||
|
#define __QSUB8 __iar_builtin_QSUB8
|
||||||
|
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||||
|
#define __USUB8 __iar_builtin_USUB8
|
||||||
|
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||||
|
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||||
|
#define __SADD16 __iar_builtin_SADD16
|
||||||
|
#define __QADD16 __iar_builtin_QADD16
|
||||||
|
#define __SHADD16 __iar_builtin_SHADD16
|
||||||
|
#define __UADD16 __iar_builtin_UADD16
|
||||||
|
#define __UQADD16 __iar_builtin_UQADD16
|
||||||
|
#define __UHADD16 __iar_builtin_UHADD16
|
||||||
|
#define __SSUB16 __iar_builtin_SSUB16
|
||||||
|
#define __QSUB16 __iar_builtin_QSUB16
|
||||||
|
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||||
|
#define __USUB16 __iar_builtin_USUB16
|
||||||
|
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||||
|
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||||
|
#define __SASX __iar_builtin_SASX
|
||||||
|
#define __QASX __iar_builtin_QASX
|
||||||
|
#define __SHASX __iar_builtin_SHASX
|
||||||
|
#define __UASX __iar_builtin_UASX
|
||||||
|
#define __UQASX __iar_builtin_UQASX
|
||||||
|
#define __UHASX __iar_builtin_UHASX
|
||||||
|
#define __SSAX __iar_builtin_SSAX
|
||||||
|
#define __QSAX __iar_builtin_QSAX
|
||||||
|
#define __SHSAX __iar_builtin_SHSAX
|
||||||
|
#define __USAX __iar_builtin_USAX
|
||||||
|
#define __UQSAX __iar_builtin_UQSAX
|
||||||
|
#define __UHSAX __iar_builtin_UHSAX
|
||||||
|
#define __USAD8 __iar_builtin_USAD8
|
||||||
|
#define __USADA8 __iar_builtin_USADA8
|
||||||
|
#define __SSAT16 __iar_builtin_SSAT16
|
||||||
|
#define __USAT16 __iar_builtin_USAT16
|
||||||
|
#define __UXTB16 __iar_builtin_UXTB16
|
||||||
|
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||||
|
#define __SXTB16 __iar_builtin_SXTB16
|
||||||
|
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||||
|
#define __SMUAD __iar_builtin_SMUAD
|
||||||
|
#define __SMUADX __iar_builtin_SMUADX
|
||||||
|
#define __SMMLA __iar_builtin_SMMLA
|
||||||
|
#define __SMLAD __iar_builtin_SMLAD
|
||||||
|
#define __SMLADX __iar_builtin_SMLADX
|
||||||
|
#define __SMLALD __iar_builtin_SMLALD
|
||||||
|
#define __SMLALDX __iar_builtin_SMLALDX
|
||||||
|
#define __SMUSD __iar_builtin_SMUSD
|
||||||
|
#define __SMUSDX __iar_builtin_SMUSDX
|
||||||
|
#define __SMLSD __iar_builtin_SMLSD
|
||||||
|
#define __SMLSDX __iar_builtin_SMLSDX
|
||||||
|
#define __SMLSLD __iar_builtin_SMLSLD
|
||||||
|
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||||
|
#define __SEL __iar_builtin_SEL
|
||||||
|
#define __QADD __iar_builtin_QADD
|
||||||
|
#define __QSUB __iar_builtin_QSUB
|
||||||
|
#define __PKHBT __iar_builtin_PKHBT
|
||||||
|
#define __PKHTB __iar_builtin_PKHTB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#define __CLZ __cmsis_iar_clz_not_active
|
||||||
|
#define __SSAT __cmsis_iar_ssat_not_active
|
||||||
|
#define __USAT __cmsis_iar_usat_not_active
|
||||||
|
#define __RBIT __cmsis_iar_rbit_not_active
|
||||||
|
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||||
|
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __INTRINSICS_INCLUDED
|
||||||
|
#error intrinsics.h is already included previously!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <intrinsics.h>
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#undef __CLZ
|
||||||
|
#undef __SSAT
|
||||||
|
#undef __USAT
|
||||||
|
#undef __RBIT
|
||||||
|
#undef __get_APSR
|
||||||
|
|
||||||
|
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||||
|
{
|
||||||
|
if (data == 0U) { return 32U; }
|
||||||
|
|
||||||
|
uint32_t count = 0U;
|
||||||
|
uint32_t mask = 0x80000000U;
|
||||||
|
|
||||||
|
while ((data & mask) == 0U)
|
||||||
|
{
|
||||||
|
count += 1U;
|
||||||
|
mask = mask >> 1U;
|
||||||
|
}
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||||
|
{
|
||||||
|
uint8_t sc = 31U;
|
||||||
|
uint32_t r = v;
|
||||||
|
for (v >>= 1U; v; v >>= 1U)
|
||||||
|
{
|
||||||
|
r <<= 1U;
|
||||||
|
r |= v & 1U;
|
||||||
|
sc--;
|
||||||
|
}
|
||||||
|
return (r << sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm("MRS %0,APSR" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#undef __get_FPSCR
|
||||||
|
#undef __set_FPSCR
|
||||||
|
#define __get_FPSCR() (0)
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
#pragma diag_suppress=Pe177
|
||||||
|
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
#define __get_xPSR __get_PSR
|
||||||
|
|
||||||
|
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __LDREX((unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __STREX(value, (unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#undef __IAR_FT
|
||||||
|
#undef __IAR_M0_FAMILY
|
||||||
|
#undef __ICCARM_V8
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
#pragma diag_default=Pe177
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ICCARM_H__ */
|
||||||
|
|
@ -0,0 +1,39 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.3
|
||||||
|
* @date 24. June 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,272 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. March 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||||
|
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||||
|
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||||
|
(((MPU_RASR_ENABLE_Msk))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,201 @@
|
||||||
|
Apache License
|
||||||
|
Version 2.0, January 2004
|
||||||
|
http://www.apache.org/licenses/
|
||||||
|
|
||||||
|
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||||
|
|
||||||
|
1. Definitions.
|
||||||
|
|
||||||
|
"License" shall mean the terms and conditions for use, reproduction,
|
||||||
|
and distribution as defined by Sections 1 through 9 of this document.
|
||||||
|
|
||||||
|
"Licensor" shall mean the copyright owner or entity authorized by
|
||||||
|
the copyright owner that is granting the License.
|
||||||
|
|
||||||
|
"Legal Entity" shall mean the union of the acting entity and all
|
||||||
|
other entities that control, are controlled by, or are under common
|
||||||
|
control with that entity. For the purposes of this definition,
|
||||||
|
"control" means (i) the power, direct or indirect, to cause the
|
||||||
|
direction or management of such entity, whether by contract or
|
||||||
|
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||||
|
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||||
|
|
||||||
|
"You" (or "Your") shall mean an individual or Legal Entity
|
||||||
|
exercising permissions granted by this License.
|
||||||
|
|
||||||
|
"Source" form shall mean the preferred form for making modifications,
|
||||||
|
including but not limited to software source code, documentation
|
||||||
|
source, and configuration files.
|
||||||
|
|
||||||
|
"Object" form shall mean any form resulting from mechanical
|
||||||
|
transformation or translation of a Source form, including but
|
||||||
|
not limited to compiled object code, generated documentation,
|
||||||
|
and conversions to other media types.
|
||||||
|
|
||||||
|
"Work" shall mean the work of authorship, whether in Source or
|
||||||
|
Object form, made available under the License, as indicated by a
|
||||||
|
copyright notice that is included in or attached to the work
|
||||||
|
(an example is provided in the Appendix below).
|
||||||
|
|
||||||
|
"Derivative Works" shall mean any work, whether in Source or Object
|
||||||
|
form, that is based on (or derived from) the Work and for which the
|
||||||
|
editorial revisions, annotations, elaborations, or other modifications
|
||||||
|
represent, as a whole, an original work of authorship. For the purposes
|
||||||
|
of this License, Derivative Works shall not include works that remain
|
||||||
|
separable from, or merely link (or bind by name) to the interfaces of,
|
||||||
|
the Work and Derivative Works thereof.
|
||||||
|
|
||||||
|
"Contribution" shall mean any work of authorship, including
|
||||||
|
the original version of the Work and any modifications or additions
|
||||||
|
to that Work or Derivative Works thereof, that is intentionally
|
||||||
|
submitted to Licensor for inclusion in the Work by the copyright owner
|
||||||
|
or by an individual or Legal Entity authorized to submit on behalf of
|
||||||
|
the copyright owner. For the purposes of this definition, "submitted"
|
||||||
|
means any form of electronic, verbal, or written communication sent
|
||||||
|
to the Licensor or its representatives, including but not limited to
|
||||||
|
communication on electronic mailing lists, source code control systems,
|
||||||
|
and issue tracking systems that are managed by, or on behalf of, the
|
||||||
|
Licensor for the purpose of discussing and improving the Work, but
|
||||||
|
excluding communication that is conspicuously marked or otherwise
|
||||||
|
designated in writing by the copyright owner as "Not a Contribution."
|
||||||
|
|
||||||
|
"Contributor" shall mean Licensor and any individual or Legal Entity
|
||||||
|
on behalf of whom a Contribution has been received by Licensor and
|
||||||
|
subsequently incorporated within the Work.
|
||||||
|
|
||||||
|
2. Grant of Copyright License. Subject to the terms and conditions of
|
||||||
|
this License, each Contributor hereby grants to You a perpetual,
|
||||||
|
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||||
|
copyright license to reproduce, prepare Derivative Works of,
|
||||||
|
publicly display, publicly perform, sublicense, and distribute the
|
||||||
|
Work and such Derivative Works in Source or Object form.
|
||||||
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|
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5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||||
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Notwithstanding the above, nothing herein shall supersede or modify
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|
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7. Disclaimer of Warranty. Unless required by applicable law or
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END OF TERMS AND CONDITIONS
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APPENDIX: How to apply the Apache License to your work.
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To apply the Apache License to your work, attach the following
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||||||
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Licensed under the Apache License, Version 2.0 (the "License");
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|
||||||
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Unless required by applicable law or agreed to in writing, software
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|
||||||
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See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
menuconfig BSP_USING_LPUART
|
||||||
|
bool "Using UART device"
|
||||||
|
default y
|
||||||
|
select RESOURCES_SERIAL
|
||||||
|
if BSP_USING_LPUART
|
||||||
|
source "$BSP_DIR/third_party_driver/uart/Kconfig"
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_GPIO
|
||||||
|
bool "Using GPIO device "
|
||||||
|
default y
|
||||||
|
select RESOURCES_PIN
|
||||||
|
|
||||||
|
if BSP_USING_GPIO
|
||||||
|
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||||
|
endif
|
||||||
|
|
@ -0,0 +1,7 @@
|
||||||
|
SRC_DIR := common
|
||||||
|
|
||||||
|
ifeq ($(CONFIG_BSP_USING_LPUART),y)
|
||||||
|
SRC_DIR += uart
|
||||||
|
endif
|
||||||
|
|
||||||
|
include $(KERNEL_ROOT)/compiler.mk
|
||||||
|
|
@ -0,0 +1,526 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_cache.c
|
||||||
|
* @brief support imxrt1176-sbc M4 core cache
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_cache.c
|
||||||
|
Description: support imxrt1176-sbc M4 core cache
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_cache.h"
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.cache_lmem"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define L1CACHE_ONEWAYSIZE_BYTE (4096U) /*!< Cache size is 4K-bytes one way. */
|
||||||
|
#define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
|
||||||
|
/*!
|
||||||
|
* brief Enables the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_EnableCodeCache(void)
|
||||||
|
{
|
||||||
|
if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK))
|
||||||
|
{
|
||||||
|
/* First, invalidate the entire cache. */
|
||||||
|
L1CACHE_InvalidateCodeCache();
|
||||||
|
|
||||||
|
/* Now enable the cache. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disables the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_DisableCodeCache(void)
|
||||||
|
{
|
||||||
|
/* First, push any modified contents. */
|
||||||
|
L1CACHE_CleanCodeCache();
|
||||||
|
|
||||||
|
/* Now disable the cache. */
|
||||||
|
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateCodeCache(void)
|
||||||
|
{
|
||||||
|
/* Enables the processor code bus to invalidate all lines in both ways.
|
||||||
|
and Initiate the processor code bus code cache command. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be invalidated.
|
||||||
|
* note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pccReg = 0;
|
||||||
|
/* Align address to cache line size. */
|
||||||
|
uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
|
||||||
|
|
||||||
|
/* Set the invalidate by line command and use the physical address. */
|
||||||
|
pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PCCLCR = pccReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanCodeCache(void)
|
||||||
|
{
|
||||||
|
/* Enable the processor code bus to push all modified lines. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be cleaned.
|
||||||
|
* note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pccReg = 0;
|
||||||
|
/* Align address to cache line size. */
|
||||||
|
uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
|
||||||
|
|
||||||
|
/* Set the push by line command. */
|
||||||
|
pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(2) | LMEM_PCCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PCCLCR = pccReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and invalidates the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateCodeCache(void)
|
||||||
|
{
|
||||||
|
/* Push and invalidate all. */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK |
|
||||||
|
LMEM_PCCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and invalidate processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be Cleaned and Invalidated.
|
||||||
|
* note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pccReg = 0;
|
||||||
|
/* Align address to cache line size. */
|
||||||
|
uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
|
||||||
|
|
||||||
|
/* Set the push by line command. */
|
||||||
|
pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(3) | LMEM_PCCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PCCLCR = pccReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
/*!
|
||||||
|
* brief Enables the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_EnableSystemCache(void)
|
||||||
|
{
|
||||||
|
/* Only enable when not enabled. */
|
||||||
|
if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK))
|
||||||
|
{
|
||||||
|
/* First, invalidate the entire cache. */
|
||||||
|
L1CACHE_InvalidateSystemCache();
|
||||||
|
|
||||||
|
/* Now enable the cache. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disables the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_DisableSystemCache(void)
|
||||||
|
{
|
||||||
|
/* First, push any modified contents. */
|
||||||
|
L1CACHE_CleanSystemCache();
|
||||||
|
|
||||||
|
/* Now disable the cache. */
|
||||||
|
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateSystemCache(void)
|
||||||
|
{
|
||||||
|
/* Enables the processor system bus to invalidate all lines in both ways.
|
||||||
|
and Initiate the processor system bus cache command. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be invalidated.
|
||||||
|
* note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pscReg = 0;
|
||||||
|
uint32_t startAddr =
|
||||||
|
address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */
|
||||||
|
|
||||||
|
/* Set the invalidate by line command and use the physical address. */
|
||||||
|
pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(1) | LMEM_PSCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PSCLCR = pscReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanSystemCache(void)
|
||||||
|
{
|
||||||
|
/* Enable the processor system bus to push all modified lines. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be cleaned.
|
||||||
|
* note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pscReg = 0;
|
||||||
|
uint32_t startAddr =
|
||||||
|
address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */
|
||||||
|
|
||||||
|
/* Set the push by line command. */
|
||||||
|
pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(2) | LMEM_PSCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PSCLCR = pscReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and invalidates the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateSystemCache(void)
|
||||||
|
{
|
||||||
|
/* Push and invalidate all. */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK |
|
||||||
|
LMEM_PSCCR_GO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
|
||||||
|
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and Invalidates processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* param address The physical address of cache.
|
||||||
|
* param size_byte size of the memory to be Clean and Invalidated.
|
||||||
|
* note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t pscReg = 0;
|
||||||
|
uint32_t startAddr =
|
||||||
|
address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */
|
||||||
|
|
||||||
|
/* Set the push by line command. */
|
||||||
|
pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(3) | LMEM_PSCLCR_LADSEL_MASK;
|
||||||
|
LMEM->PSCLCR = pscReg;
|
||||||
|
|
||||||
|
while (startAddr < endAddr)
|
||||||
|
{
|
||||||
|
/* Set the address and initiate the command. */
|
||||||
|
LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
|
||||||
|
|
||||||
|
/* Wait until the cache command completes. */
|
||||||
|
while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates cortex-m4 L1 instrument cache by range.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be invalidated.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t size = size_byte;
|
||||||
|
|
||||||
|
if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
L1CACHE_InvalidateCodeCacheByRange(address, size);
|
||||||
|
}
|
||||||
|
else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
|
||||||
|
L1CACHE_InvalidateCodeCacheByRange(address, size);
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
size = size_byte - size;
|
||||||
|
L1CACHE_InvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
L1CACHE_InvalidateSystemCacheByRange(address, size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans cortex-m4 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be cleaned.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t size = size_byte;
|
||||||
|
|
||||||
|
if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanCodeCacheByRange(address, size);
|
||||||
|
}
|
||||||
|
else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
|
||||||
|
L1CACHE_CleanCodeCacheByRange(address, size);
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
size = size_byte - size;
|
||||||
|
L1CACHE_CleanSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
L1CACHE_CleanSystemCacheByRange(address, size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and Invalidates cortex-m4 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be clean and invalidated.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
uint32_t size = size_byte;
|
||||||
|
|
||||||
|
if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanInvalidateCodeCacheByRange(address, size);
|
||||||
|
}
|
||||||
|
else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
|
||||||
|
{
|
||||||
|
size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
|
||||||
|
L1CACHE_CleanInvalidateCodeCacheByRange(address, size);
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
size = size_byte - size;
|
||||||
|
L1CACHE_CleanInvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
L1CACHE_CleanInvalidateSystemCacheByRange(address, size);
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,359 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_cache.h
|
||||||
|
* @brief support imxrt1176-sbc M4 core cache
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_cache.h
|
||||||
|
Description: support imxrt1176-sbc M4 core cache
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_CACHE_H_
|
||||||
|
#define _FSL_CACHE_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup cache_lmem
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief cache driver version. */
|
||||||
|
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*! @brief code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. */
|
||||||
|
#define L1CODEBUSCACHE_LINESIZE_BYTE \
|
||||||
|
FSL_FEATURE_L1ICACHE_LINESIZE_BYTE /*!< The code bus CACHE line size is 16B = 128b. */
|
||||||
|
#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \
|
||||||
|
L1CODEBUSCACHE_LINESIZE_BYTE /*!< The system bus CACHE line size is 16B = 128b. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
|
||||||
|
/*!
|
||||||
|
* @name cache control for L1 cache (local memory controller for code/system bus cache)
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_EnableCodeCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_DisableCodeCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateCodeCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanCodeCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be cleaned.
|
||||||
|
* @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidates the processor code bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateCodeCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidate processor code bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be Cleaned and Invalidated.
|
||||||
|
* @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables/disables the processor code bus write buffer.
|
||||||
|
*
|
||||||
|
* @param enable The enable or disable flag.
|
||||||
|
* true - enable the code bus write buffer.
|
||||||
|
* false - disable the code bus write buffer.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)
|
||||||
|
{
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
|
||||||
|
/*!
|
||||||
|
* @brief Enables the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_EnableSystemCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_DisableSystemCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateSystemCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanSystemCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be cleaned.
|
||||||
|
* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidates the processor system bus cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateSystemCache(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates processor system bus cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address of cache.
|
||||||
|
* @param size_byte size of the memory to be Clean and Invalidated.
|
||||||
|
* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
|
||||||
|
* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables/disables the processor system bus write buffer.
|
||||||
|
*
|
||||||
|
* @param enable The enable or disable flag.
|
||||||
|
* true - enable the code bus write buffer.
|
||||||
|
* false - disable the code bus write buffer.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)
|
||||||
|
{
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*@}*/
|
||||||
|
#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name cache control for unified L1 cache driver
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates cortex-m4 L1 instrument cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates cortex-m4 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans cortex-m4 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be cleaned.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates cortex-m4 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be clean and invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
/*@}*/
|
||||||
|
#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Unified Cache Control for all caches
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates instruction cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note Address and size should be aligned to 16-Byte due to the cache operation unit
|
||||||
|
* FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
|
||||||
|
* size if startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note Address and size should be aligned to 16-Byte due to the cache operation unit
|
||||||
|
* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
|
||||||
|
* size if startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_InvalidateDCacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Clean data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be cleaned.
|
||||||
|
* @note Address and size should be aligned to 16-Byte due to the cache operation unit
|
||||||
|
* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
|
||||||
|
* size if startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanDCacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be Cleaned and Invalidated.
|
||||||
|
* @note Address and size should be aligned to 16-Byte due to the cache operation unit
|
||||||
|
* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
|
||||||
|
* size if startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! @}*/
|
||||||
|
|
||||||
|
#endif /* _FSL_CACHE_H_*/
|
||||||
|
|
@ -0,0 +1,621 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_cache.c
|
||||||
|
* @brief support imxrt1176-sbc M7 core cache
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_cache.c
|
||||||
|
Description: support imxrt1176-sbc M7 core cache
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_cache.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
|
||||||
|
#define L2CACHE_8WAYS_MASK 0xFFU
|
||||||
|
#define L2CACHE_16WAYS_MASK 0xFFFFU
|
||||||
|
#define L2CACHE_SMALLWAYS_NUM 8U
|
||||||
|
#define L2CACHE_1KBCOVERTOB 1024U
|
||||||
|
#define L2CACHE_SAMLLWAYS_SIZE 16U
|
||||||
|
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
/*!
|
||||||
|
* @brief Set for all ways and waiting for the operation finished.
|
||||||
|
* This is provided for all the background operations.
|
||||||
|
*
|
||||||
|
* @param auxCtlReg The auxiliary control register.
|
||||||
|
* @param regAddr The register address to be operated.
|
||||||
|
*/
|
||||||
|
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates the Level 2 cache line by physical address.
|
||||||
|
* This function invalidates a cache line by physcial address.
|
||||||
|
*
|
||||||
|
* @param address The physical addderss of the cache.
|
||||||
|
* The format of the address shall be :
|
||||||
|
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||||
|
* Tag | index | 0
|
||||||
|
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||||
|
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||||
|
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||||
|
* The n is varies according to the index width.
|
||||||
|
* @return The actual 32-byte aligned physical address be operated.
|
||||||
|
*/
|
||||||
|
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans the Level 2 cache line based on the physical address.
|
||||||
|
* This function cleans a cache line based on a physcial address.
|
||||||
|
*
|
||||||
|
* @param address The physical addderss of the cache.
|
||||||
|
* The format of the address shall be :
|
||||||
|
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||||
|
* Tag | index | 0
|
||||||
|
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||||
|
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||||
|
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||||
|
* The n is varies according to the index width.
|
||||||
|
* @return The actual 32-byte aligned physical address be operated.
|
||||||
|
*/
|
||||||
|
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidates the Level 2 cache line based on the physical address.
|
||||||
|
* This function cleans and invalidates a cache line based on a physcial address.
|
||||||
|
*
|
||||||
|
* @param address The physical addderss of the cache.
|
||||||
|
* The format of the address shall be :
|
||||||
|
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||||
|
* Tag | index | 0
|
||||||
|
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||||
|
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||||
|
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||||
|
* The n is varies according to the index width.
|
||||||
|
* @return The actual 32-byte aligned physical address be operated.
|
||||||
|
*/
|
||||||
|
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the number of the Level 2 cache and the way size.
|
||||||
|
* This function cleans and invalidates a cache line based on a physcial address.
|
||||||
|
*
|
||||||
|
* @param num_ways The number of the cache way.
|
||||||
|
* @param size_way The way size.
|
||||||
|
*/
|
||||||
|
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
|
||||||
|
{
|
||||||
|
uint16_t mask = L2CACHE_8WAYS_MASK;
|
||||||
|
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
|
||||||
|
|
||||||
|
/* Check the ways used at first. */
|
||||||
|
if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||||
|
{
|
||||||
|
mask = L2CACHE_16WAYS_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the opeartion for all ways/entries of the cache. */
|
||||||
|
*(uint32_t *)regAddr = mask;
|
||||||
|
/* Waiting for until the operation is complete. */
|
||||||
|
while ((*(volatile uint32_t *)regAddr & mask) && timeout)
|
||||||
|
{
|
||||||
|
__ASM("nop");
|
||||||
|
timeout--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
|
||||||
|
{
|
||||||
|
/* Align the address first. */
|
||||||
|
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||||
|
/* Invalidate the cache line by physical address. */
|
||||||
|
L2CACHEC->REG7_INV_PA = address;
|
||||||
|
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
|
||||||
|
{
|
||||||
|
/* Align the address first. */
|
||||||
|
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||||
|
/* Invalidate the cache line by physical address. */
|
||||||
|
L2CACHEC->REG7_CLEAN_PA = address;
|
||||||
|
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
|
||||||
|
{
|
||||||
|
/* Align the address first. */
|
||||||
|
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||||
|
/* Clean and invalidate the cache line by physical address. */
|
||||||
|
L2CACHEC->REG7_CLEAN_INV_PA = address;
|
||||||
|
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
|
||||||
|
{
|
||||||
|
assert(num_ways);
|
||||||
|
assert(size_way);
|
||||||
|
|
||||||
|
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||||
|
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||||
|
|
||||||
|
*num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||||
|
if (!size)
|
||||||
|
{
|
||||||
|
/* 0 internally mapped to the same size as 1 - 16KB.*/
|
||||||
|
size += 1;
|
||||||
|
}
|
||||||
|
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initializes the level 2 cache controller module.
|
||||||
|
*
|
||||||
|
* param config Pointer to configuration structure. See "l2cache_config_t".
|
||||||
|
*/
|
||||||
|
void L2CACHE_Init(l2cache_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config);
|
||||||
|
|
||||||
|
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
|
||||||
|
uint8_t count;
|
||||||
|
uint32_t auxReg = 0;
|
||||||
|
|
||||||
|
/*The aux register must be configured when the cachec is disabled
|
||||||
|
* So disable first if the cache controller is enabled.
|
||||||
|
*/
|
||||||
|
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
|
||||||
|
{
|
||||||
|
L2CACHE_Disable();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Unlock all entries. */
|
||||||
|
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||||
|
{
|
||||||
|
waysNum = 0xFFFFU;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
|
||||||
|
{
|
||||||
|
L2CACHE_LockdownByWayEnable(count, waysNum, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the ways and way-size etc. */
|
||||||
|
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
|
||||||
|
L2CACHEC->REG1_AUX_CONTROL = auxReg;
|
||||||
|
|
||||||
|
/* Set the tag/data ram latency. */
|
||||||
|
if (config->lateConfig)
|
||||||
|
{
|
||||||
|
uint32_t data = 0;
|
||||||
|
/* Tag latency. */
|
||||||
|
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
|
||||||
|
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
|
||||||
|
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
|
||||||
|
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||||
|
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
|
||||||
|
/* Data latency. */
|
||||||
|
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
|
||||||
|
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
|
||||||
|
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
|
||||||
|
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||||
|
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets an available default settings for the cache controller.
|
||||||
|
*
|
||||||
|
* This function initializes the cache controller configuration structure with default settings.
|
||||||
|
* The default values are:
|
||||||
|
* code
|
||||||
|
* config->waysNum = kL2CACHE_8ways;
|
||||||
|
* config->waySize = kL2CACHE_32KbSize;
|
||||||
|
* config->repacePolicy = kL2CACHE_Roundrobin;
|
||||||
|
* config->lateConfig = NULL;
|
||||||
|
* config->istrPrefetchEnable = false;
|
||||||
|
* config->dataPrefetchEnable = false;
|
||||||
|
* config->nsLockdownEnable = false;
|
||||||
|
* config->writeAlloc = kL2CACHE_UseAwcache;
|
||||||
|
* endcode
|
||||||
|
* param config Pointer to the configuration structure.
|
||||||
|
*/
|
||||||
|
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config);
|
||||||
|
|
||||||
|
/* Initializes the configure structure to zero. */
|
||||||
|
memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||||
|
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||||
|
|
||||||
|
/* Get the default value */
|
||||||
|
config->wayNum = (l2cache_way_num_t)number;
|
||||||
|
config->waySize = (l2cache_way_size)size;
|
||||||
|
config->repacePolicy = kL2CACHE_Roundrobin;
|
||||||
|
config->lateConfig = NULL;
|
||||||
|
config->istrPrefetchEnable = false;
|
||||||
|
config->dataPrefetchEnable = false;
|
||||||
|
config->nsLockdownEnable = false;
|
||||||
|
config->writeAlloc = kL2CACHE_UseAwcache;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables the level 2 cache controller.
|
||||||
|
* This function enables the cache controller. Must be written using a secure access.
|
||||||
|
* If write with a Non-secure access will cause a DECERR response.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Enable(void)
|
||||||
|
{
|
||||||
|
/* Invalidate first. */
|
||||||
|
L2CACHE_Invalidate();
|
||||||
|
/* Enable the level 2 cache controller. */
|
||||||
|
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disables the level 2 cache controller.
|
||||||
|
* This function disables the cache controller. Must be written using a secure access.
|
||||||
|
* If write with a Non-secure access will cause a DECERR response.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Disable(void)
|
||||||
|
{
|
||||||
|
/* First CleanInvalidate all enties in the cache. */
|
||||||
|
L2CACHE_CleanInvalidate();
|
||||||
|
/* Disable the level 2 cache controller. */
|
||||||
|
L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||||
|
/* DSB - data sync barrier.*/
|
||||||
|
__DSB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates the Level 2 cache.
|
||||||
|
* This function invalidates all entries in cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Invalidate(void)
|
||||||
|
{
|
||||||
|
/* Invalidate all entries in cache. */
|
||||||
|
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
|
||||||
|
/* Cache sync. */
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans the level 2 cache controller.
|
||||||
|
* This function cleans all entries in the level 2 cache controller.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Clean(void)
|
||||||
|
{
|
||||||
|
/* Clean all entries of the cache. */
|
||||||
|
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
|
||||||
|
/* Cache sync. */
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and invalidates the level 2 cache controller.
|
||||||
|
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanInvalidate(void)
|
||||||
|
{
|
||||||
|
/* Clean all entries of the cache. */
|
||||||
|
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
|
||||||
|
/* Cache sync. */
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function invalidates all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be invalidated.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
|
||||||
|
/* Invalidate addresses in the range. */
|
||||||
|
while (address < endAddr)
|
||||||
|
{
|
||||||
|
address = L2CACHE_InvalidateLineByAddr(address);
|
||||||
|
/* Update the size. */
|
||||||
|
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Cache sync. */
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function cleans all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be cleaned.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t num_ways = 0;
|
||||||
|
uint32_t size_way = 0;
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
|
||||||
|
/* Get the number and size of the cache way. */
|
||||||
|
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||||
|
|
||||||
|
/* Check if the clean size is over the cache size. */
|
||||||
|
if ((endAddr - address) > num_ways * size_way)
|
||||||
|
{
|
||||||
|
L2CACHE_Clean();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clean addresses in the range. */
|
||||||
|
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||||
|
{
|
||||||
|
/* Clean the address in the range. */
|
||||||
|
address = L2CACHE_CleanLineByAddr(address);
|
||||||
|
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function cleans and invalidates all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be cleaned and invalidated.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
uint32_t num_ways = 0;
|
||||||
|
uint32_t size_way = 0;
|
||||||
|
uint32_t endAddr = address + size_byte;
|
||||||
|
|
||||||
|
/* Get the number and size of the cache way. */
|
||||||
|
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||||
|
|
||||||
|
/* Check if the clean size is over the cache size. */
|
||||||
|
if ((endAddr - address) > num_ways * size_way)
|
||||||
|
{
|
||||||
|
L2CACHE_CleanInvalidate();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clean addresses in the range. */
|
||||||
|
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||||
|
{
|
||||||
|
/* Clean the address in the range. */
|
||||||
|
address = L2CACHE_CleanInvalidateLineByAddr(address);
|
||||||
|
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables or disables to lock down the data and instruction by way.
|
||||||
|
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||||||
|
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||||||
|
* But the normal cache maintenance operations that invalidate, clean or clean
|
||||||
|
* and validate cache contents affect the locked-down cache lines as normal.
|
||||||
|
*
|
||||||
|
* param masterId The master id, range from 0 ~ 7.
|
||||||
|
* param mask The ways to be enabled or disabled to lockdown.
|
||||||
|
* each bit in value is related to each way of the cache. for example:
|
||||||
|
* value: bit 0 ------ way 0.
|
||||||
|
* value: bit 1 ------ way 1.
|
||||||
|
* --------------------------
|
||||||
|
* value: bit 15 ------ way 15.
|
||||||
|
* Note: please make sure the value setting is align with your supported ways.
|
||||||
|
* param enable True enable the lockdown, false to disable the lockdown.
|
||||||
|
*/
|
||||||
|
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
|
||||||
|
{
|
||||||
|
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||||
|
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||||
|
num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||||
|
|
||||||
|
assert(mask < (1U << num_ways));
|
||||||
|
assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
|
||||||
|
|
||||||
|
uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
|
||||||
|
uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
|
||||||
|
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
/* Data lockdown. */
|
||||||
|
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
|
||||||
|
/* Instruction lockdown. */
|
||||||
|
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Data lockdown. */
|
||||||
|
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
|
||||||
|
/* Instruction lockdown. */
|
||||||
|
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidate cortex-m7 L1 instruction cache by range.
|
||||||
|
*
|
||||||
|
* param address The start address of the memory to be invalidated.
|
||||||
|
* param size_byte The memory size.
|
||||||
|
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L1 I-cache line size if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t addr = address & ~((uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1U);
|
||||||
|
uint32_t align_len = address - addr;
|
||||||
|
int32_t size = (int32_t)size_byte + (int32_t)align_len;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
while (size > 0)
|
||||||
|
{
|
||||||
|
SCB->ICIMVAU = addr;
|
||||||
|
addr += (uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
|
||||||
|
size -= (int32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
|
||||||
|
}
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates all instruction caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* param address The physical address.
|
||||||
|
* param size_byte size of the memory to be invalidated.
|
||||||
|
* note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||||
|
L2CACHE_InvalidateByRange(address, size_byte);
|
||||||
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
|
||||||
|
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Invalidates all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* param address The physical address.
|
||||||
|
* param size_byte size of the memory to be invalidated.
|
||||||
|
* note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||||
|
L2CACHE_InvalidateByRange(address, size_byte);
|
||||||
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
L1CACHE_InvalidateDCacheByRange(address, size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* param address The physical address.
|
||||||
|
* param size_byte size of the memory to be cleaned.
|
||||||
|
* note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanDCacheByRange(address, size_byte);
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||||
|
L2CACHE_CleanByRange(address, size_byte);
|
||||||
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Cleans and Invalidates all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* param address The physical address.
|
||||||
|
* param size_byte size of the memory to be cleaned and invalidated.
|
||||||
|
* note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||||
|
L2CACHE_CleanInvalidateByRange(address, size_byte);
|
||||||
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,477 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_cache.c
|
||||||
|
* @brief support imxrt1176-sbc M7 core cache
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_cache.c
|
||||||
|
Description: support imxrt1176-sbc M7 core cache
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_CACHE_H_
|
||||||
|
#define _FSL_CACHE_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup cache_armv7_m7
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief cache driver version 2.0.4. */
|
||||||
|
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||||
|
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
|
||||||
|
#endif
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
|
||||||
|
/*! @brief Number of level 2 cache controller ways. */
|
||||||
|
typedef enum _l2cache_way_num
|
||||||
|
{
|
||||||
|
kL2CACHE_8ways = 0, /*!< 8 ways. */
|
||||||
|
#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
|
||||||
|
kL2CACHE_16ways /*!< 16 ways. */
|
||||||
|
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
|
||||||
|
} l2cache_way_num_t;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller way size. */
|
||||||
|
typedef enum _l2cache_way_size
|
||||||
|
{
|
||||||
|
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
|
||||||
|
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
|
||||||
|
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
|
||||||
|
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
|
||||||
|
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
|
||||||
|
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
|
||||||
|
} l2cache_way_size;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller replacement policy. */
|
||||||
|
typedef enum _l2cache_replacement
|
||||||
|
{
|
||||||
|
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
|
||||||
|
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
|
||||||
|
} l2cache_replacement_t;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller force write allocate options. */
|
||||||
|
typedef enum _l2cache_writealloc
|
||||||
|
{
|
||||||
|
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
|
||||||
|
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
|
||||||
|
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
|
||||||
|
} l2cache_writealloc_t;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller tag/data ram latency. */
|
||||||
|
typedef enum _l2cache_latency
|
||||||
|
{
|
||||||
|
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
|
||||||
|
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
|
||||||
|
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
|
||||||
|
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
|
||||||
|
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
|
||||||
|
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
|
||||||
|
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
|
||||||
|
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
|
||||||
|
} l2cache_latency_t;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
|
||||||
|
typedef struct _l2cache_latency_config
|
||||||
|
{
|
||||||
|
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
|
||||||
|
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
|
||||||
|
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
|
||||||
|
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
|
||||||
|
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
|
||||||
|
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
|
||||||
|
} L2cache_latency_config_t;
|
||||||
|
|
||||||
|
/*! @brief Level 2 cache controller configure structure. */
|
||||||
|
typedef struct _l2cache_config
|
||||||
|
{
|
||||||
|
/* ------------------------ l2 cachec basic settings ---------------------------- */
|
||||||
|
l2cache_way_num_t wayNum; /*!< The number of ways. */
|
||||||
|
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
|
||||||
|
l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
|
||||||
|
/* ------------------------ tag/data ram latency settings ----------------------- */
|
||||||
|
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
|
||||||
|
/* ------------------------ Prefetch enable settings ---------------------------- */
|
||||||
|
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
|
||||||
|
bool dataPrefetchEnable; /*!< Data prefetch enable. */
|
||||||
|
/* ------------------------ Non-secure access settings -------------------------- */
|
||||||
|
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
|
||||||
|
/* ------------------------ other settings -------------------------------------- */
|
||||||
|
l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
|
||||||
|
} l2cache_config_t;
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Control for cortex-m7 L1 cache
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables cortex-m7 L1 instruction cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_EnableICache(void)
|
||||||
|
{
|
||||||
|
SCB_EnableICache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables cortex-m7 L1 instruction cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_DisableICache(void)
|
||||||
|
{
|
||||||
|
SCB_DisableICache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidate cortex-m7 L1 instruction cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_InvalidateICache(void)
|
||||||
|
{
|
||||||
|
SCB_InvalidateICache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidate cortex-m7 L1 instruction cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L1 I-cache line size if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables cortex-m7 L1 data cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_EnableDCache(void)
|
||||||
|
{
|
||||||
|
SCB_EnableDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables cortex-m7 L1 data cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_DisableDCache(void)
|
||||||
|
{
|
||||||
|
SCB_DisableDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates cortex-m7 L1 data cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_InvalidateDCache(void)
|
||||||
|
{
|
||||||
|
SCB_InvalidateDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans cortex-m7 L1 data cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_CleanDCache(void)
|
||||||
|
{
|
||||||
|
SCB_CleanDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates cortex-m7 L1 data cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_CleanInvalidateDCache(void)
|
||||||
|
{
|
||||||
|
SCB_CleanInvalidateDCache();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates cortex-m7 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans cortex-m7 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be cleaned.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be clean and invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||||
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||||
|
{
|
||||||
|
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
|
||||||
|
}
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||||
|
/*!
|
||||||
|
* @name Control for L2 pl310 cache
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initializes the level 2 cache controller module.
|
||||||
|
*
|
||||||
|
* @param config Pointer to configuration structure. See "l2cache_config_t".
|
||||||
|
*/
|
||||||
|
void L2CACHE_Init(l2cache_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets an available default settings for the cache controller.
|
||||||
|
*
|
||||||
|
* This function initializes the cache controller configuration structure with default settings.
|
||||||
|
* The default values are:
|
||||||
|
* @code
|
||||||
|
* config->waysNum = kL2CACHE_8ways;
|
||||||
|
* config->waySize = kL2CACHE_32KbSize;
|
||||||
|
* config->repacePolicy = kL2CACHE_Roundrobin;
|
||||||
|
* config->lateConfig = NULL;
|
||||||
|
* config->istrPrefetchEnable = false;
|
||||||
|
* config->dataPrefetchEnable = false;
|
||||||
|
* config->nsLockdownEnable = false;
|
||||||
|
* config->writeAlloc = kL2CACHE_UseAwcache;
|
||||||
|
* @endcode
|
||||||
|
* @param config Pointer to the configuration structure.
|
||||||
|
*/
|
||||||
|
void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables the level 2 cache controller.
|
||||||
|
* This function enables the cache controller. Must be written using a secure access.
|
||||||
|
* If write with a Non-secure access will cause a DECERR response.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Enable(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables the level 2 cache controller.
|
||||||
|
* This function disables the cache controller. Must be written using a secure access.
|
||||||
|
* If write with a Non-secure access will cause a DECERR response.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Disable(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates the Level 2 cache.
|
||||||
|
* This function invalidates all entries in cache.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Invalidate(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function invalidates all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans the level 2 cache controller.
|
||||||
|
* This function cleans all entries in the level 2 cache controller.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_Clean(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function cleans all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be cleaned.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidates the level 2 cache controller.
|
||||||
|
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanInvalidate(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||||
|
* This function cleans and invalidates all cache lines between two physical addresses.
|
||||||
|
*
|
||||||
|
* @param address The start address of the memory to be cleaned and invalidated.
|
||||||
|
* @param size_byte The memory size.
|
||||||
|
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||||
|
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||||
|
* is not aligned. For the size_byte, application should make sure the
|
||||||
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables or disables to lock down the data and instruction by way.
|
||||||
|
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||||||
|
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||||||
|
* But the normal cache maintenance operations that invalidate, clean or clean
|
||||||
|
* and validate cache contents affect the locked-down cache lines as normal.
|
||||||
|
*
|
||||||
|
* @param masterId The master id, range from 0 ~ 7.
|
||||||
|
* @param mask The ways to be enabled or disabled to lockdown.
|
||||||
|
* each bit in value is related to each way of the cache. for example:
|
||||||
|
* value: bit 0 ------ way 0.
|
||||||
|
* value: bit 1 ------ way 1.
|
||||||
|
* --------------------------
|
||||||
|
* value: bit 15 ------ way 15.
|
||||||
|
* Note: please make sure the value setting is align with your supported ways.
|
||||||
|
* @param enable True enable the lockdown, false to disable the lockdown.
|
||||||
|
*/
|
||||||
|
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
|
||||||
|
* Mainly used for many drivers for easy cache operation.
|
||||||
|
*@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates all instruction caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Invalidates all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be invalidated.
|
||||||
|
* @note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be cleaned.
|
||||||
|
* @note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Cleans and Invalidates all data caches by range.
|
||||||
|
*
|
||||||
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||||
|
*
|
||||||
|
* @param address The physical address.
|
||||||
|
* @param size_byte size of the memory to be cleaned and invalidated.
|
||||||
|
* @note address and size should be aligned to cache line size
|
||||||
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||||
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||||
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||||
|
*/
|
||||||
|
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! @}*/
|
||||||
|
|
||||||
|
#endif /* _FSL_CACHE_H_*/
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
SRC_FILES := system_MIMXRT1176_cm7.c fsl_clock.c fsl_common.c fsl_pmu.c fsl_common_arm.c pin_mux.c \
|
||||||
|
clock_config.c dcd.c fsl_dcdc.c fsl_anatop_ai.c
|
||||||
|
|
||||||
|
include $(KERNEL_ROOT)/compiler.mk
|
||||||
|
|
@ -0,0 +1,903 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* How to setup clock using clock driver functions:
|
||||||
|
*
|
||||||
|
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||||
|
*
|
||||||
|
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||||
|
*
|
||||||
|
* 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: Clocks v8.0
|
||||||
|
processor: MIMXRT1176xxxxx
|
||||||
|
package_id: MIMXRT1176DVMAA
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 0.0.0
|
||||||
|
board: MIMXRT1170-EVK
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file clock_config.c
|
||||||
|
* @brief support imxrt1176-sbc clock config
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: clock_config.c
|
||||||
|
Description: support imxrt1176-sbc clock config
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "clock_config.h"
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
#include "fsl_dcdc.h"
|
||||||
|
#include "fsl_pmu.h"
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
************************ BOARD_InitBootClocks function ************************
|
||||||
|
******************************************************************************/
|
||||||
|
void BOARD_InitBootClocks(void)
|
||||||
|
{
|
||||||
|
BOARD_BootClockRUN();
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||||
|
/* This function should not run from SDRAM since it will change SEMC configuration. */
|
||||||
|
AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
|
||||||
|
void UpdateSemcClock(void)
|
||||||
|
{
|
||||||
|
/* Enable self-refresh mode and update semc clock root to 200MHz. */
|
||||||
|
SEMC->IPCMD = 0xA55A000D;
|
||||||
|
while ((SEMC->INTR & 0x3) == 0)
|
||||||
|
;
|
||||||
|
SEMC->INTR = 0x3;
|
||||||
|
SEMC->DCCR = 0x0B;
|
||||||
|
/*
|
||||||
|
* Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
|
||||||
|
* need to change the SEMC clock root here. If customer is using their own DCD and
|
||||||
|
* want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
|
||||||
|
* adjusted here to fine tune the SDRAM performance
|
||||||
|
*/
|
||||||
|
CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************** Configuration BOARD_BootClockRUN ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!Configuration
|
||||||
|
name: BOARD_BootClockRUN
|
||||||
|
called_from_default_init: true
|
||||||
|
outputs:
|
||||||
|
- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
|
||||||
|
- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
|
||||||
|
- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
|
||||||
|
- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
|
||||||
|
- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||||
|
- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||||
|
- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
|
||||||
|
- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
|
||||||
|
- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
|
||||||
|
- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
|
||||||
|
- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
|
||||||
|
- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: MQS_MCLK.outFreq, value: 24 MHz}
|
||||||
|
- {id: OSC_24M.outFreq, value: 24 MHz}
|
||||||
|
- {id: OSC_32K.outFreq, value: 32.768 kHz}
|
||||||
|
- {id: OSC_RC_16M.outFreq, value: 16 MHz}
|
||||||
|
- {id: OSC_RC_400M.outFreq, value: 400 MHz}
|
||||||
|
- {id: OSC_RC_48M.outFreq, value: 48 MHz}
|
||||||
|
- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
|
||||||
|
- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
|
||||||
|
- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
|
||||||
|
- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
|
||||||
|
- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
|
||||||
|
- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
|
||||||
|
- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
|
||||||
|
- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
|
||||||
|
- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
|
||||||
|
- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
|
||||||
|
- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
|
||||||
|
- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
|
||||||
|
- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
|
||||||
|
- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
|
||||||
|
- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
|
||||||
|
- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||||
|
settings:
|
||||||
|
- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
|
||||||
|
- {id: SOCDomainVoltage, value: OD}
|
||||||
|
- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
|
||||||
|
- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
|
||||||
|
- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
|
||||||
|
- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
|
||||||
|
- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
|
||||||
|
- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
|
||||||
|
- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
|
||||||
|
- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
|
||||||
|
- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
|
||||||
|
- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
|
||||||
|
- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
|
||||||
|
- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
|
||||||
|
- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
|
||||||
|
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
|
||||||
|
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
|
||||||
|
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
|
||||||
|
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
|
||||||
|
- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
|
||||||
|
- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
|
||||||
|
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
|
||||||
|
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
|
||||||
|
- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
|
||||||
|
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
|
||||||
|
- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef SKIP_POWER_ADJUSTMENT
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
#define BYPASS_LDO_LPSR 1
|
||||||
|
#define SKIP_LDO_ADJUSTMENT 1
|
||||||
|
#elif __CORTEX_M == 4
|
||||||
|
#define SKIP_DCDC_ADJUSTMENT 1
|
||||||
|
#define SKIP_FBB_ENABLE 1
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
|
||||||
|
.loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
|
||||||
|
};
|
||||||
|
|
||||||
|
const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.mfd = 268435455, /* Denominator of spread spectrum */
|
||||||
|
.ss = NULL, /* Spread spectrum parameter */
|
||||||
|
.ssEnable = false, /* Enable spread spectrum or not */
|
||||||
|
};
|
||||||
|
|
||||||
|
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
|
||||||
|
{
|
||||||
|
.loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
|
||||||
|
.postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
|
||||||
|
.numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||||
|
.denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||||
|
.ss = NULL, /* Spread spectrum parameter */
|
||||||
|
.ssEnable = false, /* Enable spread spectrum or not */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
void BOARD_BootClockRUN(void)
|
||||||
|
{
|
||||||
|
clock_root_config_t rootCfg = {0};
|
||||||
|
|
||||||
|
/* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
|
||||||
|
DCDC_BootIntoDCM(DCDC);
|
||||||
|
|
||||||
|
#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
|
||||||
|
if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
|
||||||
|
{
|
||||||
|
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set 1.125V for production samples to align with data sheet requirement */
|
||||||
|
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
|
||||||
|
/* Check if FBB need to be enabled in OverDrive(OD) mode */
|
||||||
|
if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
|
||||||
|
{
|
||||||
|
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
|
||||||
|
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||||
|
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
|
||||||
|
pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
|
||||||
|
pmu_static_lpsr_dig_config_t lpsrDigConfig;
|
||||||
|
|
||||||
|
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
|
||||||
|
{
|
||||||
|
PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
|
||||||
|
PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
|
||||||
|
}
|
||||||
|
|
||||||
|
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
|
||||||
|
{
|
||||||
|
PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
|
||||||
|
lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
|
||||||
|
PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Config CLK_1M */
|
||||||
|
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
|
||||||
|
|
||||||
|
/* Init OSC RC 16M */
|
||||||
|
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
|
||||||
|
|
||||||
|
/* Init OSC RC 400M */
|
||||||
|
CLOCK_OSC_EnableOscRc400M();
|
||||||
|
CLOCK_OSC_GateOscRc400M(true);
|
||||||
|
|
||||||
|
/* Init OSC RC 48M */
|
||||||
|
CLOCK_OSC_EnableOsc48M(true);
|
||||||
|
CLOCK_OSC_EnableOsc48MDiv2(true);
|
||||||
|
|
||||||
|
/* Config OSC 24M */
|
||||||
|
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
|
||||||
|
/* Wait for 24M OSC to be stable. */
|
||||||
|
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
|
||||||
|
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||||
|
|
||||||
|
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __CORTEX_M == 4
|
||||||
|
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||||
|
|
||||||
|
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
|
||||||
|
*/
|
||||||
|
/* Init Arm Pll. */
|
||||||
|
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||||
|
|
||||||
|
/* Bypass Sys Pll1. */
|
||||||
|
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
|
||||||
|
|
||||||
|
/* DeInit Sys Pll1. */
|
||||||
|
CLOCK_DeinitSysPll1();
|
||||||
|
|
||||||
|
/* Init Sys Pll2. */
|
||||||
|
CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
|
||||||
|
|
||||||
|
/* Init System Pll2 pfd0. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
|
||||||
|
|
||||||
|
/* Init System Pll2 pfd1. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
|
||||||
|
|
||||||
|
/* Init System Pll2 pfd2. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
|
||||||
|
|
||||||
|
/* Init System Pll2 pfd3. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
|
||||||
|
|
||||||
|
/* Init Sys Pll3. */
|
||||||
|
CLOCK_InitSysPll3();
|
||||||
|
|
||||||
|
/* Init System Pll3 pfd0. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
|
||||||
|
|
||||||
|
/* Init System Pll3 pfd1. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
|
||||||
|
|
||||||
|
/* Init System Pll3 pfd2. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
|
||||||
|
|
||||||
|
/* Init System Pll3 pfd3. */
|
||||||
|
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
|
||||||
|
|
||||||
|
/* Bypass Audio Pll. */
|
||||||
|
CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
|
||||||
|
|
||||||
|
/* DeInit Audio Pll. */
|
||||||
|
CLOCK_DeinitAudioPll();
|
||||||
|
|
||||||
|
/* Init Video Pll. */
|
||||||
|
CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
|
||||||
|
|
||||||
|
/* Module clock root configurations. */
|
||||||
|
/* Configure M7 using ARM_PLL_CLK */
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure M4 using SYS_PLL3_PFD3_CLK */
|
||||||
|
#if __CORTEX_M == 4
|
||||||
|
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure BUS using SYS_PLL3_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
|
||||||
|
rootCfg.div = 2;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure BUS_LPSR using SYS_PLL3_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
|
||||||
|
rootCfg.div = 3;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SEMC using SYS_PLL2_PFD1_CLK */
|
||||||
|
#ifndef SKIP_SEMC_INIT
|
||||||
|
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
|
||||||
|
rootCfg.div = 3;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||||
|
UpdateSemcClock();
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure CSSYS using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CSTRACE using SYS_PLL2_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
|
||||||
|
rootCfg.div = 4;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
|
||||||
|
#if __CORTEX_M == 4
|
||||||
|
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 240;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure ADC1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ADC2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ACMP using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT4 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT5 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GPT6 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
|
||||||
|
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
|
||||||
|
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CAN1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CAN2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CAN3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART1 using SYS_PLL2_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
|
||||||
|
rootCfg.div = 22;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART2 using SYS_PLL2_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
|
||||||
|
rootCfg.div = 22;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART4 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART5 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART6 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART7 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART8 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART9 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART10 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART11 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPUART12 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C4 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C5 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPI2C6 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI4 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI5 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LPSPI6 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure EMV1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure EMV2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET_QOS using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET_25M using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure USDHC1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure USDHC2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure ASRC using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure MQS using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure MIC using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SPDIF using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SAI1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SAI2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SAI3 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure SAI4 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure GC355 using PLL_VIDEO_CLK */
|
||||||
|
rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
|
||||||
|
rootCfg.div = 2;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LCDIF using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure MIPI_REF using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CSI2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CSI2_UI using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CSI using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CKO1 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
|
||||||
|
|
||||||
|
/* Configure CKO2 using OSC_RC_48M_DIV2 */
|
||||||
|
rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
|
||||||
|
rootCfg.div = 1;
|
||||||
|
CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
|
||||||
|
|
||||||
|
/* Set SAI1 MCLK1 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||||
|
/* Set SAI1 MCLK2 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
|
||||||
|
/* Set SAI1 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||||
|
/* Set SAI2 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||||
|
/* Set SAI3 MCLK3 clock source. */
|
||||||
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||||
|
|
||||||
|
/* Set MQS configuration. */
|
||||||
|
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||||
|
/* Set ENET Ref clock source. */
|
||||||
|
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
|
||||||
|
/* Set ENET_1G Tx clock source. */
|
||||||
|
IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
|
||||||
|
/* Set ENET_1G Ref clock source. */
|
||||||
|
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
|
||||||
|
/* Set ENET_QOS Tx clock source. */
|
||||||
|
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
|
||||||
|
/* Set ENET_QOS Ref clock source. */
|
||||||
|
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
|
||||||
|
/* Set GPT1 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
|
||||||
|
/* Set GPT2 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
|
||||||
|
/* Set GPT3 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
|
||||||
|
/* Set GPT4 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
|
||||||
|
/* Set GPT5 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
|
||||||
|
/* Set GPT6 High frequency reference clock source. */
|
||||||
|
IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
|
||||||
|
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
|
||||||
|
#else
|
||||||
|
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,339 @@
|
||||||
|
/**
|
||||||
|
* @file dcd.c
|
||||||
|
* @brief support imxrt1176-sbc dcd
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: dcd.c
|
||||||
|
Description: support imxrt1176-sbc dcd
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#include "dcd.h"
|
||||||
|
#include "fsl_common.h"
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.dcd_data"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.dcd_data"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: DCDx V2.0
|
||||||
|
processor: MIMXRT1176xxxxx
|
||||||
|
package_id: MIMXRT1176DVMAA
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 9.0.1
|
||||||
|
board: MIMXRT1170-EVK
|
||||||
|
output_format: c_array
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||||
|
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||||
|
const uint8_t dcd_data[] = {
|
||||||
|
/* HEADER */
|
||||||
|
/* Tag */
|
||||||
|
0xD2,
|
||||||
|
/* Image Length */
|
||||||
|
0x03, 0x98,
|
||||||
|
/* Version */
|
||||||
|
0x41,
|
||||||
|
|
||||||
|
/* COMMANDS */
|
||||||
|
|
||||||
|
/* group: 'Imported Commands' */
|
||||||
|
/* #1.1-93, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x02, 0xEC, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */
|
||||||
|
0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02,
|
||||||
|
/* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x0, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4 */
|
||||||
|
0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10,
|
||||||
|
/* #1.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x8, size: 4 */
|
||||||
|
0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08,
|
||||||
|
/* #1.82, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||||
|
/* #1.83, command: write_value, address: SEMC_BMCR0, value: 0x00030524, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x08, 0x00, 0x03, 0x05, 0x24,
|
||||||
|
/* #1.84, command: write_value, address: SEMC_BMCR1, value: 0x06030524, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x0C, 0x06, 0x03, 0x05, 0x24,
|
||||||
|
/* #1.85, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||||
|
/* #1.86, command: write_value, address: SEMC_SDRAMCR0, value: 0x00000F31, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x31,
|
||||||
|
/* #1.87, command: write_value, address: SEMC_SDRAMCR1, value: 0x00772A22, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22,
|
||||||
|
/* #1.88, command: write_value, address: SEMC_SDRAMCR2, value: 0x00010A0D, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D,
|
||||||
|
/* #1.89, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08,
|
||||||
|
/* #1.90, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.91, command: write_value, address: SEMC_IPCR1, value: 0x00000002, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||||
|
/* #1.92, command: write_value, address: SEMC_IPCR2, value: 0x00000000, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||||
|
/* #1.93, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||||
|
|
||||||
|
/* group: 'nop' */
|
||||||
|
/* #1, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #2, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #3, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #4, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #5, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
|
||||||
|
/* group: 'set intr/ipcmd' */
|
||||||
|
/* #1.1-2, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x14, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
|
||||||
|
/* #1.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||||
|
|
||||||
|
/* group: 'nop2' */
|
||||||
|
/* #1, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #2, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #3, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #4, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #5, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
|
||||||
|
/* group: 'set intr/ipcmd 2' */
|
||||||
|
/* #1.1-2, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x14, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
|
||||||
|
/* #1.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||||
|
|
||||||
|
/* group: 'nop3' */
|
||||||
|
/* #1, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #2, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #3, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #4, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #5, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
|
||||||
|
/* group: 'set intr/iptxdat/ipcmd' */
|
||||||
|
/* #1.1-3, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x1C, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
|
||||||
|
/* #1.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33,
|
||||||
|
/* #1.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||||
|
|
||||||
|
/* group: 'nop4' */
|
||||||
|
/* #1, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #2, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #3, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #4, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
/* #5, command: nop */
|
||||||
|
0xC0, 0x00, 0x04, 0x00,
|
||||||
|
|
||||||
|
/* group: 'set intr/s' */
|
||||||
|
/* #1.1-2, command header bytes for merged 'Write - value' command */
|
||||||
|
0xCC, 0x00, 0x14, 0x04,
|
||||||
|
/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
|
||||||
|
/* #1.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */
|
||||||
|
0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09
|
||||||
|
};
|
||||||
|
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||||
|
|
||||||
|
#else
|
||||||
|
const uint8_t dcd_data[] = {0x00};
|
||||||
|
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||||
|
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||||
|
|
@ -0,0 +1,376 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2019 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_anatop_ai.c
|
||||||
|
* @brief support imxrt1176-sbc ai
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_anatop_ai.c
|
||||||
|
Description: support imxrt1176-sbc ai
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_anatop_ai.h"
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.anatop_ai"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata)
|
||||||
|
{
|
||||||
|
uint32_t temp;
|
||||||
|
uint32_t rdata;
|
||||||
|
uint32_t pre_toggle_done;
|
||||||
|
uint32_t toggle_done;
|
||||||
|
|
||||||
|
switch (itf)
|
||||||
|
{
|
||||||
|
case kAI_Itf_Ldo:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
|
||||||
|
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
|
||||||
|
ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */
|
||||||
|
ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
}
|
||||||
|
else /* read */
|
||||||
|
{
|
||||||
|
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
|
||||||
|
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
|
||||||
|
ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_1g:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_Audio:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
|
||||||
|
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
|
||||||
|
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done
|
||||||
|
*/
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_Video:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
|
||||||
|
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
|
||||||
|
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
|
||||||
|
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
|
||||||
|
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
|
||||||
|
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
|
||||||
|
toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_400m:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pre_toggle_done =
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
toggle_done =
|
||||||
|
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
|
||||||
|
} while (toggle_done == pre_toggle_done);
|
||||||
|
rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_Temp:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
|
||||||
|
ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case kAI_Itf_Bandgap:
|
||||||
|
if (isWrite)
|
||||||
|
{
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
|
||||||
|
ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
|
||||||
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
||||||
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
|
||||||
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
||||||
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
||||||
|
ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
|
||||||
|
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* This branch should never be hit. */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata)
|
||||||
|
{
|
||||||
|
(void)ANATOP_AI_Access(itf, true, addr, wdata);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr)
|
||||||
|
{
|
||||||
|
uint32_t rdata;
|
||||||
|
rdata = ANATOP_AI_Access(itf, false, addr, 0);
|
||||||
|
return rdata;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ANATOP_AI_WriteWithMaskShift(
|
||||||
|
anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
|
||||||
|
{
|
||||||
|
uint32_t rdata;
|
||||||
|
rdata = ANATOP_AI_Read(itf, addr);
|
||||||
|
rdata = (rdata & (~mask)) | ((wdata << shift) & mask);
|
||||||
|
ANATOP_AI_Write(itf, addr, rdata);
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,110 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_common.c
|
||||||
|
* @brief
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_common.c
|
||||||
|
Description:
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
#define SDK_MEM_MAGIC_NUMBER 12345U
|
||||||
|
|
||||||
|
typedef struct _mem_align_control_block
|
||||||
|
{
|
||||||
|
uint16_t identifier; /*!< Identifier for the memory control block. */
|
||||||
|
uint16_t offset; /*!< offset from aligned address to real address */
|
||||||
|
} mem_align_cb_t;
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.common"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||||
|
{
|
||||||
|
mem_align_cb_t *p_cb = NULL;
|
||||||
|
uint32_t alignedsize;
|
||||||
|
|
||||||
|
/* Check overflow. */
|
||||||
|
alignedsize = SDK_SIZEALIGN(size, alignbytes);
|
||||||
|
if (alignedsize < size)
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
alignedsize += alignbytes + sizeof(mem_align_cb_t);
|
||||||
|
|
||||||
|
union
|
||||||
|
{
|
||||||
|
void *pointer_value;
|
||||||
|
#if (defined(__DSC__) && defined(__CW__))
|
||||||
|
uint32_t unsigned_value;
|
||||||
|
#else
|
||||||
|
uintptr_t unsigned_value;
|
||||||
|
#endif
|
||||||
|
} p_align_addr, p_addr;
|
||||||
|
|
||||||
|
p_addr.pointer_value = malloc(alignedsize);
|
||||||
|
|
||||||
|
if (p_addr.pointer_value == NULL)
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
|
||||||
|
|
||||||
|
p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
|
||||||
|
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
||||||
|
p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
|
||||||
|
|
||||||
|
return p_align_addr.pointer_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SDK_Free(void *ptr)
|
||||||
|
{
|
||||||
|
union
|
||||||
|
{
|
||||||
|
void *pointer_value;
|
||||||
|
#if (defined(__DSC__) && defined(__CW__))
|
||||||
|
uint32_t unsigned_value;
|
||||||
|
#else
|
||||||
|
uintptr_t unsigned_value;
|
||||||
|
#endif
|
||||||
|
} p_free;
|
||||||
|
p_free.pointer_value = ptr;
|
||||||
|
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
|
||||||
|
|
||||||
|
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
|
||||||
|
|
||||||
|
free(p_free.pointer_value);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,252 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_common_arm.c
|
||||||
|
* @brief support imxrt1176-sbc interrupt
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_common_arm.c
|
||||||
|
Description: support imxrt1176-sbc interrupt
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.common_arm"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __GIC_PRIO_BITS
|
||||||
|
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||||
|
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||||
|
{
|
||||||
|
#ifdef __VECTOR_TABLE
|
||||||
|
#undef __VECTOR_TABLE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||||
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
extern uint32_t Image$$RW_m_data$$Base[];
|
||||||
|
|
||||||
|
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
|
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||||
|
extern uint32_t __VECTOR_TABLE[];
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
extern uint32_t __VECTOR_TABLE[];
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
|
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||||
|
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||||
|
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
|
||||||
|
uint32_t n;
|
||||||
|
uint32_t ret;
|
||||||
|
uint32_t irqMaskValue;
|
||||||
|
|
||||||
|
irqMaskValue = DisableGlobalIRQ();
|
||||||
|
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||||
|
{
|
||||||
|
/* Copy the vector table from ROM to RAM */
|
||||||
|
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||||
|
{
|
||||||
|
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||||
|
}
|
||||||
|
/* Point the VTOR to the position of vector table */
|
||||||
|
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = __VECTOR_RAM[(int32_t)irq + 16];
|
||||||
|
/* make sure the __VECTOR_RAM is noncachable */
|
||||||
|
__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
|
||||||
|
|
||||||
|
EnableGlobalIRQ(irqMaskValue);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||||
|
#endif /* __GIC_PRIO_BITS. */
|
||||||
|
|
||||||
|
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
|
||||||
|
* powerlib should be used instead of these functions.
|
||||||
|
*/
|
||||||
|
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When the SYSCON STARTER registers are discontinuous, these functions are
|
||||||
|
* implemented in fsl_power.c.
|
||||||
|
*/
|
||||||
|
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
|
||||||
|
|
||||||
|
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||||
|
{
|
||||||
|
uint32_t intNumber = (uint32_t)interrupt;
|
||||||
|
|
||||||
|
uint32_t index = 0;
|
||||||
|
|
||||||
|
while (intNumber >= 32u)
|
||||||
|
{
|
||||||
|
index++;
|
||||||
|
intNumber -= 32u;
|
||||||
|
}
|
||||||
|
|
||||||
|
SYSCON->STARTERSET[index] = 1UL << intNumber;
|
||||||
|
(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||||
|
}
|
||||||
|
|
||||||
|
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||||
|
{
|
||||||
|
uint32_t intNumber = (uint32_t)interrupt;
|
||||||
|
|
||||||
|
(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||||
|
uint32_t index = 0;
|
||||||
|
|
||||||
|
while (intNumber >= 32u)
|
||||||
|
{
|
||||||
|
index++;
|
||||||
|
intNumber -= 32u;
|
||||||
|
}
|
||||||
|
|
||||||
|
SYSCON->STARTERCLR[index] = 1UL << intNumber;
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
|
||||||
|
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
|
||||||
|
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||||
|
|
||||||
|
#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
|
||||||
|
/* Use WDT. */
|
||||||
|
static void enableCpuCycleCounter(void)
|
||||||
|
{
|
||||||
|
/* Make sure the DWT trace fucntion is enabled. */
|
||||||
|
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
|
||||||
|
{
|
||||||
|
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* CYCCNT not supported on this device. */
|
||||||
|
assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
|
||||||
|
|
||||||
|
/* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
|
||||||
|
if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
|
||||||
|
{
|
||||||
|
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t getCpuCycleCount(void)
|
||||||
|
{
|
||||||
|
return DWT->CYCCNT;
|
||||||
|
}
|
||||||
|
#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
|
||||||
|
/* Use software loop. */
|
||||||
|
#if defined(__CC_ARM) /* This macro is arm v5 specific */
|
||||||
|
/* clang-format off */
|
||||||
|
__ASM static void DelayLoop(uint32_t count)
|
||||||
|
{
|
||||||
|
loop
|
||||||
|
SUBS R0, R0, #1
|
||||||
|
CMP R0, #0
|
||||||
|
BNE loop
|
||||||
|
BX LR
|
||||||
|
}
|
||||||
|
/* clang-format on */
|
||||||
|
#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
|
||||||
|
/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
|
||||||
|
* use SUB and CMP here for compatibility */
|
||||||
|
static void DelayLoop(uint32_t count)
|
||||||
|
{
|
||||||
|
__ASM volatile(" MOV R0, %0" : : "r"(count));
|
||||||
|
__ASM volatile(
|
||||||
|
"loop: \n"
|
||||||
|
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||||
|
" SUB R0, R0, #1 \n"
|
||||||
|
#else
|
||||||
|
" SUBS R0, R0, #1 \n"
|
||||||
|
#endif
|
||||||
|
" CMP R0, #0 \n"
|
||||||
|
|
||||||
|
" BNE loop \n"
|
||||||
|
:
|
||||||
|
:
|
||||||
|
: "r0");
|
||||||
|
}
|
||||||
|
#endif /* defined(__CC_ARM) */
|
||||||
|
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Delay at least for some time.
|
||||||
|
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
|
||||||
|
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
|
||||||
|
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
|
||||||
|
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
|
||||||
|
*
|
||||||
|
* @param delayTime_us Delay time in unit of microsecond.
|
||||||
|
* @param coreClock_Hz Core clock frequency with Hz.
|
||||||
|
*/
|
||||||
|
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
|
||||||
|
{
|
||||||
|
uint64_t count;
|
||||||
|
|
||||||
|
if (delayTime_us > 0U)
|
||||||
|
{
|
||||||
|
count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
|
||||||
|
|
||||||
|
assert(count <= UINT32_MAX);
|
||||||
|
|
||||||
|
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
|
||||||
|
|
||||||
|
enableCpuCycleCounter();
|
||||||
|
/* Calculate the count ticks. */
|
||||||
|
count += getCpuCycleCount();
|
||||||
|
|
||||||
|
if (count > UINT32_MAX)
|
||||||
|
{
|
||||||
|
count -= UINT32_MAX;
|
||||||
|
/* Wait for cyccnt overflow. */
|
||||||
|
while (count < getCpuCycleCount())
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait for cyccnt reach count value. */
|
||||||
|
while (count > getCpuCycleCount())
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
/* Divide value may be different in various environment to ensure delay is precise.
|
||||||
|
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
|
||||||
|
* two instructions in one period, through test here set divide 1.5. Other M cores use
|
||||||
|
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
|
||||||
|
* not matter because other instructions outside while loop is enough to fill the time.
|
||||||
|
*/
|
||||||
|
#if (__CORTEX_M == 7)
|
||||||
|
count = count / 3U * 2U;
|
||||||
|
#else
|
||||||
|
count = count / 4U;
|
||||||
|
#endif
|
||||||
|
DelayLoop((uint32_t)count);
|
||||||
|
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,537 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_dcdc.c
|
||||||
|
* @brief
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_dcdc.c
|
||||||
|
Description:
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_dcdc.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.dcdc_soc"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
/*!
|
||||||
|
* brief Gets instance number for DCDC module.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address
|
||||||
|
*/
|
||||||
|
static uint32_t DCDC_GetInstance(DCDC_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Converts the byte array to word.
|
||||||
|
*
|
||||||
|
* param ptrArray Pointer to the byte array.
|
||||||
|
* return The converted result.
|
||||||
|
*/
|
||||||
|
static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray);
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
/*! brief Pointers to DCDC bases for each instance. */
|
||||||
|
static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
|
||||||
|
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/*! brief Pointers to DCDC clocks for each instance. */
|
||||||
|
static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CodDCDC_GetstatusFlagse
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
static uint32_t DCDC_GetInstance(DCDC_Type *base)
|
||||||
|
{
|
||||||
|
uint32_t instance;
|
||||||
|
|
||||||
|
/* Find the instance index from base address mappings. */
|
||||||
|
for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
|
||||||
|
{
|
||||||
|
if (s_dcdcBases[instance] == base)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(instance < ARRAY_SIZE(s_dcdcBases));
|
||||||
|
|
||||||
|
return instance;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
|
||||||
|
{
|
||||||
|
assert(ptrArray != NULL);
|
||||||
|
|
||||||
|
uint32_t temp32 = 0UL;
|
||||||
|
uint32_t index;
|
||||||
|
|
||||||
|
for (index = 0U; index < 4U; index++)
|
||||||
|
{
|
||||||
|
temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
return temp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initializes the basic resource of DCDC module, such as control mode, etc.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to the configuration structure.
|
||||||
|
*/
|
||||||
|
void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
|
||||||
|
{
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/* Enable the clock. */
|
||||||
|
CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
|
||||||
|
uint32_t tmp32 = base->CTRL0;
|
||||||
|
|
||||||
|
tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);
|
||||||
|
|
||||||
|
if (config->enableDcdcTimeout)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;
|
||||||
|
}
|
||||||
|
if (config->enableSwitchingConverterOutput)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_CTRL0_DIG_EN_MASK;
|
||||||
|
}
|
||||||
|
tmp32 |= DCDC_CTRL0_ENABLE_MASK;
|
||||||
|
base->CTRL0 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief De-initializes the DCDC module.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
*/
|
||||||
|
void DCDC_Deinit(DCDC_Type *base)
|
||||||
|
{
|
||||||
|
/* Disables DCDC. */
|
||||||
|
base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK;
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/* Disable the clock. */
|
||||||
|
CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default setting for DCDC, such as control mode, etc.
|
||||||
|
*
|
||||||
|
* This function initializes the user configuration structure to a default value. The default values are:
|
||||||
|
* code
|
||||||
|
* config->controlMode = kDCDC_StaticControl;
|
||||||
|
* config->trimInputMode = kDCDC_SampleTrimInput;
|
||||||
|
* config->enableDcdcTimeout = false;
|
||||||
|
* config->enableSwitchingConverterOutput = false;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to configuration structure. See to dcdc_config_t.
|
||||||
|
*/
|
||||||
|
void DCDC_GetDefaultConfig(dcdc_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
/* Initializes the configure structure to zero. */
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->controlMode = kDCDC_StaticControl;
|
||||||
|
config->trimInputMode = kDCDC_SampleTrimInput;
|
||||||
|
config->enableDcdcTimeout = false;
|
||||||
|
config->enableSwitchingConverterOutput = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default setting for detection configuration.
|
||||||
|
*
|
||||||
|
* The default configuration are set according to responding registers' setting when powered on.
|
||||||
|
* They are:
|
||||||
|
* code
|
||||||
|
* config->enableXtalokDetection = false;
|
||||||
|
* config->powerDownOverVoltageVdd1P8Detection = true;
|
||||||
|
* config->powerDownOverVoltageVdd1P0Detection = true;
|
||||||
|
* config->powerDownLowVoltageDetection = false;
|
||||||
|
* config->powerDownOverCurrentDetection = true;
|
||||||
|
* config->powerDownPeakCurrentDetection = true;
|
||||||
|
* config->powerDownZeroCrossDetection = true;
|
||||||
|
* config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
|
||||||
|
*/
|
||||||
|
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
/* Initializes the configure structure to zero. */
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->enableXtalokDetection = false;
|
||||||
|
config->powerDownOverVoltageVdd1P8Detection = true;
|
||||||
|
config->powerDownOverVoltageVdd1P0Detection = true;
|
||||||
|
config->powerDownLowVoltageDetection = false;
|
||||||
|
config->powerDownOverCurrentDetection = true;
|
||||||
|
config->powerDownPeakCurrentDetection = true;
|
||||||
|
config->powerDownZeroCrossDetection = true;
|
||||||
|
config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* breif Configures the DCDC detection.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
|
||||||
|
*/
|
||||||
|
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
/* Configure the DCDC_REG0 register. */
|
||||||
|
tmp32 = base->REG0 &
|
||||||
|
~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK |
|
||||||
|
DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK |
|
||||||
|
DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK);
|
||||||
|
|
||||||
|
tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold);
|
||||||
|
if (false == config->enableXtalokDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownOverVoltageVdd1P8Detection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownOverVoltageVdd1P0Detection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownLowVoltageDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownOverCurrentDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownPeakCurrentDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
|
||||||
|
}
|
||||||
|
if (config->powerDownZeroCrossDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
|
||||||
|
}
|
||||||
|
base->REG0 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures the DCDC clock source.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
|
||||||
|
*/
|
||||||
|
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
|
||||||
|
{
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
/* Configure the DCDC_REG0 register. */
|
||||||
|
tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
|
||||||
|
DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
|
||||||
|
switch (clockSource)
|
||||||
|
{
|
||||||
|
case kDCDC_ClockInternalOsc:
|
||||||
|
tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
|
||||||
|
break;
|
||||||
|
case kDCDC_ClockExternalOsc:
|
||||||
|
/* Choose the external clock and disable the internal clock. */
|
||||||
|
tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
|
||||||
|
break;
|
||||||
|
case kDCDC_ClockAutoSwitch:
|
||||||
|
/* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */
|
||||||
|
tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
assert(false);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
base->REG0 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default setting for low power configuration.
|
||||||
|
*
|
||||||
|
* The default configuration are set according to responding registers' setting when powered on.
|
||||||
|
* They are:
|
||||||
|
* code
|
||||||
|
* config->enableAdjustHystereticValue = false;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
|
||||||
|
*/
|
||||||
|
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
/* Initializes the configure structure to zero. */
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
config->enableAdjustHystereticValue = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures the DCDC low power.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
|
||||||
|
*/
|
||||||
|
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
/* Configure the DCDC_REG0 register. */
|
||||||
|
tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK);
|
||||||
|
|
||||||
|
if (config->enableAdjustHystereticValue)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
|
||||||
|
}
|
||||||
|
base->REG0 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default setting for loop control configuration.
|
||||||
|
*
|
||||||
|
* The default configuration are set according to responding registers' setting when powered on.
|
||||||
|
* They are:
|
||||||
|
* code
|
||||||
|
* config->enableCommonHysteresis = false;
|
||||||
|
* config->enableCommonThresholdDetection = false;
|
||||||
|
* config->enableInvertHysteresisSign = false;
|
||||||
|
* config->enableRCThresholdDetection = false;
|
||||||
|
* config->enableRCScaleCircuit = 0U;
|
||||||
|
* config->complementFeedForwardStep = 0U;
|
||||||
|
* config->controlParameterMagnitude = 2U;
|
||||||
|
* config->integralProportionalRatio = 2U;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
|
||||||
|
*/
|
||||||
|
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
/* Initializes the configure structure to zero. */
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->enableCommonHysteresis = false;
|
||||||
|
config->enableCommonThresholdDetection = false;
|
||||||
|
config->enableInvertHysteresisSign = false;
|
||||||
|
config->enableRCThresholdDetection = false;
|
||||||
|
config->enableRCScaleCircuit = 0U;
|
||||||
|
config->complementFeedForwardStep = 0U;
|
||||||
|
config->controlParameterMagnitude = 2U;
|
||||||
|
config->integralProportionalRatio = 2U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures the DCDC loop control.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
|
||||||
|
*/
|
||||||
|
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
/* Configure the DCDC_REG1 register. */
|
||||||
|
tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |
|
||||||
|
DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK);
|
||||||
|
if (config->enableCommonHysteresis)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;
|
||||||
|
}
|
||||||
|
if (config->enableCommonThresholdDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;
|
||||||
|
}
|
||||||
|
if (config->enableDifferentialHysteresis)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;
|
||||||
|
}
|
||||||
|
if (config->enableDifferentialThresholdDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
base->REG1 = tmp32;
|
||||||
|
|
||||||
|
/* configure the DCDC_REG2 register. */
|
||||||
|
tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
|
||||||
|
DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK |
|
||||||
|
DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK);
|
||||||
|
tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
|
||||||
|
DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
|
||||||
|
DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
|
||||||
|
DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
|
||||||
|
if (config->enableInvertHysteresisSign)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
|
||||||
|
}
|
||||||
|
if (config->enableRCThresholdDetection)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
|
||||||
|
}
|
||||||
|
base->REG2 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures for the min power.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
|
||||||
|
*/
|
||||||
|
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
|
||||||
|
if (config->enableUseHalfFreqForContinuous)
|
||||||
|
{
|
||||||
|
tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
|
||||||
|
}
|
||||||
|
base->REG3 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures the DCDC internal regulator.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
|
||||||
|
*/
|
||||||
|
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
|
||||||
|
{
|
||||||
|
assert(NULL != config);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
|
||||||
|
tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
|
||||||
|
base->REG3 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initializes DCDC module when the control mode selected as setpoint mode.
|
||||||
|
*
|
||||||
|
* note The function should be invoked in the initial step to config the
|
||||||
|
* DCDC via setpoint control mode.
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
* param config The pointer to the structure dcdc_setpoint_config_t.
|
||||||
|
*/
|
||||||
|
void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
/* Enable DCDC Dig Logic. */
|
||||||
|
base->REG5 = config->enableDigLogicMap;
|
||||||
|
|
||||||
|
/* Set DCDC power mode. */
|
||||||
|
base->REG6 = config->lowpowerMap;
|
||||||
|
base->REG7 = config->standbyMap;
|
||||||
|
base->REG7P = config->standbyLowpowerMap;
|
||||||
|
|
||||||
|
/* Set target voltage of VDD1P8 in buck mode. */
|
||||||
|
base->REG8 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage);
|
||||||
|
base->REG9 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 4U);
|
||||||
|
base->REG10 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 8U);
|
||||||
|
base->REG11 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 12U);
|
||||||
|
|
||||||
|
/* Set target voltage of VDD1P0 in buck mode. */
|
||||||
|
base->REG12 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage);
|
||||||
|
base->REG13 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 4U);
|
||||||
|
base->REG14 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 8U);
|
||||||
|
base->REG15 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 12U);
|
||||||
|
|
||||||
|
/* Set target voltage of VDD1P8 in low power mode. */
|
||||||
|
base->REG16 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage);
|
||||||
|
base->REG17 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 4U);
|
||||||
|
base->REG18 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 8U);
|
||||||
|
base->REG19 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 12U);
|
||||||
|
|
||||||
|
/* Set target voltage of VDD1P0 in low power mode. */
|
||||||
|
base->REG20 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage);
|
||||||
|
base->REG21 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 4U);
|
||||||
|
base->REG22 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 8U);
|
||||||
|
base->REG23 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 12U);
|
||||||
|
|
||||||
|
/* Enable DCDC module. */
|
||||||
|
base->REG4 = config->enableDCDCMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Boots DCDC into DCM(discontinous conduction mode).
|
||||||
|
*
|
||||||
|
* pwd_zcd=0x0;
|
||||||
|
* DM_CTRL = 1'b1;
|
||||||
|
* pwd_cmp_offset=0x0;
|
||||||
|
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
|
||||||
|
* DCM_set_ctrl=1'b1;
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
*/
|
||||||
|
void DCDC_BootIntoDCM(DCDC_Type *base)
|
||||||
|
{
|
||||||
|
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
|
||||||
|
base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK;
|
||||||
|
base->REG1 |= DCDC_REG1_DM_CTRL_MASK;
|
||||||
|
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U);
|
||||||
|
base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK);
|
||||||
|
base->REG3 |= DCDC_REG3_ENABLE_FF_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Boots DCDC into CCM(continous conduction mode).
|
||||||
|
*
|
||||||
|
* pwd_zcd=0x1;
|
||||||
|
* pwd_cmp_offset=0x0;
|
||||||
|
* dcdc_loopctrl_en_rcscale=0x3;
|
||||||
|
*
|
||||||
|
* param base DCDC peripheral base address.
|
||||||
|
*/
|
||||||
|
void DCDC_BootIntoCCM(DCDC_Type *base)
|
||||||
|
{
|
||||||
|
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
|
||||||
|
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,978 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_pmu.c
|
||||||
|
* @brief support imxrt1176-sbc pmu
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_pmu.c
|
||||||
|
Description: support imxrt1176-sbc pmu
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_pmu.h"
|
||||||
|
#include "fsl_anatop_ai.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.pmu_1"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
#define PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS 4U
|
||||||
|
#define PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH 8UL
|
||||||
|
|
||||||
|
#define PMU_POWER_DETECT_CTRL_REGISTER (ANADIG_PMU->PMU_POWER_DETECT_CTRL)
|
||||||
|
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK (0x1U)
|
||||||
|
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK (0x2U)
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT 1U
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT)) & \
|
||||||
|
PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK)
|
||||||
|
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK (0x1CU)
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT 2U
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT)) & \
|
||||||
|
PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK)
|
||||||
|
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK (0x1E0U)
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT 5U
|
||||||
|
#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT)) & \
|
||||||
|
PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK)
|
||||||
|
|
||||||
|
#define PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(member) \
|
||||||
|
((uint32_t)((ANADIG_PMU_BASE) + (uint32_t)offsetof(ANADIG_PMU_Type, member)))
|
||||||
|
|
||||||
|
#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_PLL_ENABLE_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_ENABLE_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_ENABLE_SP), 0UL \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \
|
||||||
|
{ \
|
||||||
|
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_LP_MODE_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_LP_MODE_SP), 0UL \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \
|
||||||
|
{ \
|
||||||
|
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_TRACKING_EN_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \
|
||||||
|
{ \
|
||||||
|
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_BYPASS_EN_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_BYPASS_EN_SP), 0UL \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PMU_LDO_STBY_EN_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(PLL_LDO_STBY_EN_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_STBY_EN_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_STBY_EN_SP), 0UL \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PMU_LPSR_DIG_TRG_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP0), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP1), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP2), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP3) \
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
#define PMU_BODY_BIAS_ENABLE_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define PMU_BODY_BIAS_ENABLE_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \
|
||||||
|
}
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
#define PMU_BODY_BIAS_STBY_EN_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define PMU_BODY_BIAS_STBY_EN_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \
|
||||||
|
}
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \
|
||||||
|
{ \
|
||||||
|
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \
|
||||||
|
}
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
/*******************************************************************************
|
||||||
|
* Prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Selects the control mode of the PLL LDO.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param mode The control mode of the PLL LDO. Please refer to pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)
|
||||||
|
{
|
||||||
|
if (mode == kPMU_StaticMode)
|
||||||
|
{
|
||||||
|
base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base)
|
||||||
|
{
|
||||||
|
if ((base->LDO_PLL_ENABLE_SP & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK) != 0UL)
|
||||||
|
{
|
||||||
|
base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables PLL LDO via AI interface in Static/Software mode.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base)
|
||||||
|
{
|
||||||
|
uint32_t temp32;
|
||||||
|
|
||||||
|
temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0);
|
||||||
|
|
||||||
|
if (temp32 !=
|
||||||
|
(AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK))
|
||||||
|
{
|
||||||
|
ANATOP_AI_Write(
|
||||||
|
kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0,
|
||||||
|
(AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK));
|
||||||
|
SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Enable Voltage Reference for PLLs before those PLLs were enabled. */
|
||||||
|
base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disables PLL LDO via AI interface in Static/Software mode.
|
||||||
|
*/
|
||||||
|
void PMU_StaticDisablePllLdo(void)
|
||||||
|
{
|
||||||
|
ANATOP_AI_Write(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Selects the control mode of the LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param mode The control mode of the LPSR ANA LDO. Please refer to pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)
|
||||||
|
{
|
||||||
|
if (mode == kPMU_StaticMode)
|
||||||
|
{
|
||||||
|
base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the Bypass mode of the LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* param enable Enable/Disable bypass mode.
|
||||||
|
* - \b true Enable LPSR ANA Bypass mode.
|
||||||
|
* - \b false Disable LPSR ANA Bypass mode.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable)
|
||||||
|
{
|
||||||
|
if (enable == false)
|
||||||
|
{
|
||||||
|
/* Enable LPSR ANA LDO and HP mode. */
|
||||||
|
base->PMU_LDO_LPSR_ANA &=
|
||||||
|
~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK);
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Clear Bypass. */
|
||||||
|
base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK);
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Disable Tracking mode. */
|
||||||
|
base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable HP mode. */
|
||||||
|
base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Enable Tracking mode. */
|
||||||
|
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Enabled Bypass. */
|
||||||
|
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Disable LPSR ANA LDO. */
|
||||||
|
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Fill the LPSR ANA LDO configuration structure with default settings.
|
||||||
|
*
|
||||||
|
* The default values are:
|
||||||
|
* code
|
||||||
|
* config->mode = kPMU_HighPowerMode;
|
||||||
|
config->enable2mALoad = true;
|
||||||
|
config->enable20uALoad = false;
|
||||||
|
config->enable4mALoad = true;
|
||||||
|
config->enableStandbyMode = false;
|
||||||
|
config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0;
|
||||||
|
config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable;
|
||||||
|
config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA;
|
||||||
|
config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to the structure pmu_static_lpsr_ana_ldo_config_t. Please refer to @ref
|
||||||
|
* pmu_static_lpsr_ana_ldo_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->mode = kPMU_HighPowerMode;
|
||||||
|
config->enable2mALoad = true;
|
||||||
|
config->enable20uALoad = false;
|
||||||
|
config->enable4mALoad = true;
|
||||||
|
config->enableStandbyMode = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initialize the LPSR ANA LDO in Static/Sofware Mode.
|
||||||
|
*
|
||||||
|
* param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* param config Pointer to the structure pmu_static_lpsr_ana_ldo_config_t. Please refer to @ref
|
||||||
|
* pmu_static_lpsr_ana_ldo_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
uint32_t regValue = base->PMU_LDO_LPSR_ANA;
|
||||||
|
|
||||||
|
regValue &=
|
||||||
|
~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK |
|
||||||
|
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK |
|
||||||
|
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK);
|
||||||
|
|
||||||
|
if ((config->mode) == kPMU_LowPowerMode)
|
||||||
|
{
|
||||||
|
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK;
|
||||||
|
}
|
||||||
|
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad);
|
||||||
|
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad);
|
||||||
|
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad);
|
||||||
|
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(config->enableStandbyMode);
|
||||||
|
|
||||||
|
base->PMU_LDO_LPSR_ANA = regValue;
|
||||||
|
|
||||||
|
/* Enable LPSR ANA DIG. */
|
||||||
|
base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disable the output of LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base)
|
||||||
|
{
|
||||||
|
/* Disable LPSR ANA LDO. */
|
||||||
|
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Selects the control mode of the LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* param mode The control mode of the LPSR DIG LDO. Please refer to pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)
|
||||||
|
{
|
||||||
|
if (mode == kPMU_StaticMode)
|
||||||
|
{
|
||||||
|
base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode.
|
||||||
|
*
|
||||||
|
* param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* param enable
|
||||||
|
* true - Turn on Bypass mode of the LPSR DIG LDO.
|
||||||
|
* false - Turn off Bypass mode of the LPSR DIG LDO.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable)
|
||||||
|
{
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
/* tracking */
|
||||||
|
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* set BYPASS */
|
||||||
|
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Disable LPSR DIG LDO */
|
||||||
|
base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable LPSR DIG LDO and HP mode */
|
||||||
|
base->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK);
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Clear BYPASS */
|
||||||
|
base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
|
||||||
|
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
|
||||||
|
/* Disable tracking */
|
||||||
|
base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the default configuration of LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* @param config Pointer to the structure pmu_static_lpsr_dig_config_t. Please refer to @ref
|
||||||
|
* pmu_static_lpsr_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us;
|
||||||
|
config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initialize the LPSR DIG LDO in static mode.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @param config Pointer to the structure pmu_static_lpsr_dig_config_t. Please refer to @ref
|
||||||
|
* pmu_static_lpsr_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
uint32_t temp32 = base->PMU_LDO_LPSR_DIG;
|
||||||
|
|
||||||
|
temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK;
|
||||||
|
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage);
|
||||||
|
base->PMU_LDO_LPSR_DIG = temp32;
|
||||||
|
|
||||||
|
temp32 = base->PMU_LDO_LPSR_DIG_2;
|
||||||
|
temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK;
|
||||||
|
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime);
|
||||||
|
base->PMU_LDO_LPSR_DIG_2 = temp32;
|
||||||
|
|
||||||
|
/* Enable LPSR DIG LDO. */
|
||||||
|
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
|
||||||
|
SDK_DelayAtLeastUs(125U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
||||||
|
PMU_POWER_DETECT_CTRL_REGISTER |= ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base)
|
||||||
|
{
|
||||||
|
PMU_POWER_DETECT_CTRL_REGISTER &= ~ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK;
|
||||||
|
base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the voltage step of LPSR DIG LDO in the certain setpoint during GPC mode.
|
||||||
|
*
|
||||||
|
* note The function provides the feature to set the voltage step to the different setpoints.
|
||||||
|
*
|
||||||
|
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
|
||||||
|
* param voltageStep The voltage step to be set.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue)
|
||||||
|
{
|
||||||
|
uint32_t regValue = 0UL;
|
||||||
|
const uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS;
|
||||||
|
uint8_t regIndex;
|
||||||
|
uint8_t temp8;
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for (regIndex = 0U; regIndex < ARRAY_SIZE(lpsrDigTrgRegArray); regIndex++)
|
||||||
|
{
|
||||||
|
temp8 = (((uint8_t)(setpointMap >> (PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS * regIndex))) & 0xFU);
|
||||||
|
if (temp8 != 0UL)
|
||||||
|
{
|
||||||
|
regValue = (*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]);
|
||||||
|
for (i = 0U; i < PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS; i++)
|
||||||
|
{
|
||||||
|
if (((temp8 >> (1U * i)) & 0x1U) != 0U)
|
||||||
|
{
|
||||||
|
regValue &= ~(0xFFUL << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i));
|
||||||
|
regValue |= (uint32_t)voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
(*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]) = regValue;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default config of the SNVS DIG LDO.
|
||||||
|
*
|
||||||
|
* The default values are:
|
||||||
|
* code
|
||||||
|
* config->mode = kPMU_LowPowerMode;
|
||||||
|
* config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA;
|
||||||
|
* config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K;
|
||||||
|
* config->trimValue = 0U;
|
||||||
|
* config->enablePullDown = true;
|
||||||
|
* config->enableLdoStable = false;
|
||||||
|
* endcode
|
||||||
|
*
|
||||||
|
* param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to pmu_snvs_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->mode = kPMU_LowPowerMode;
|
||||||
|
config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA;
|
||||||
|
config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K;
|
||||||
|
config->trimValue = 0U;
|
||||||
|
config->enablePullDown = true;
|
||||||
|
config->enableLdoStable = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initialize the SNVS DIG LDO.
|
||||||
|
*
|
||||||
|
* param base LDO SNVS DIG peripheral base address.
|
||||||
|
* param mode Used to control LDO power mode, please refer to pmu_ldo_operate_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode)
|
||||||
|
{
|
||||||
|
uint32_t temp32 = base->PMU_LDO_SNVS_DIG;
|
||||||
|
|
||||||
|
temp32 &= ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK);
|
||||||
|
|
||||||
|
temp32 |= (ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(mode) | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK);
|
||||||
|
|
||||||
|
base->PMU_LDO_SNVS_DIG = temp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Controls the ON/OFF of the selected LDO in the certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1
|
||||||
|
* means enable specific ldo in that setpoint.
|
||||||
|
* For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means enable PLL LDO in setpoint 0, disable
|
||||||
|
* PLL LDO in other setpoint.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
assert(name != kPMU_SnvsDigLdo);
|
||||||
|
|
||||||
|
uint32_t ldoEnableRegArray[] = PMU_LDO_ENABLE_SETPOINT_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) = ~setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the operating mode of the selected LDO in the certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
|
||||||
|
* param mode The operating mode of the selected ldo. Please refer to the enumeration pmu_ldo_operate_mode_t for
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode)
|
||||||
|
{
|
||||||
|
assert(name > kPMU_PllLdo);
|
||||||
|
assert(name < kPMU_SnvsDigLdo);
|
||||||
|
|
||||||
|
uint32_t ldoLpModeRegArray[] = PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS;
|
||||||
|
|
||||||
|
if (mode == kPMU_LowPowerMode)
|
||||||
|
{
|
||||||
|
(*(volatile uint32_t *)ldoLpModeRegArray[(uint8_t)name]) &= ~setpointMap;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
(*(volatile uint32_t *)ldoLpModeRegArray[(uint8_t)name]) |= setpointMap;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Controls the ON/OFF of the selected LDOs' Tracking mode in the certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
assert(name > kPMU_PllLdo);
|
||||||
|
assert(name < kPMU_SnvsDigLdo);
|
||||||
|
|
||||||
|
uint32_t ldoTrackingEnableRegArray[] = PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) = setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Controls the ON/OFF of the selected LDOs' Bypass mode in the certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
assert(name > kPMU_PllLdo);
|
||||||
|
assert(name < kPMU_SnvsDigLdo);
|
||||||
|
|
||||||
|
uint32_t ldoBypassEnableRegArray[] = PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) = setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief When STBY assert, enable/disable the selected LDO enter it's Low power mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY
|
||||||
|
* assert, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
assert(name != kPMU_SnvsDigLdo);
|
||||||
|
|
||||||
|
uint32_t ldoStandbyEnableRegArray[] = PMU_LDO_STBY_EN_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) = setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Selects the control mode of the Bandgap Reference.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param mode The control mode of the Bandgap Reference. Please refer to pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)
|
||||||
|
{
|
||||||
|
if (mode == kPMU_StaticMode)
|
||||||
|
{
|
||||||
|
base->PMU_REF_CTRL &= ~ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base)
|
||||||
|
{
|
||||||
|
if ((base->BANDGAP_ENABLE_SP & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK) == 0UL)
|
||||||
|
{
|
||||||
|
base->PMU_REF_CTRL &= ~ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Disables Bandgap self bias for best noise performance.
|
||||||
|
*
|
||||||
|
* This function waits for the bandgap to be stable and disables the bandgap self bias.
|
||||||
|
* After being powered up, it needs to wait for the bandgap stable to be stable and then disable Bandgap
|
||||||
|
* Self bias for best noise performance.
|
||||||
|
*/
|
||||||
|
void PMU_DisableBandgapSelfBiasAfterPowerUp(void)
|
||||||
|
{
|
||||||
|
uint32_t temp32;
|
||||||
|
uint32_t regValue;
|
||||||
|
|
||||||
|
/* Wait Bandgap stable. */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_STAT0);
|
||||||
|
} while ((regValue & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) == 0UL);
|
||||||
|
|
||||||
|
/* Disable Bandgap self bias for best noise performance. */
|
||||||
|
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
|
||||||
|
temp32 |= AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;
|
||||||
|
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables Bandgap self bias before power down.
|
||||||
|
*
|
||||||
|
* This function will enable Bandgap self bias feature before powering down or there
|
||||||
|
* will be risk of Bandgap not starting properly.
|
||||||
|
*/
|
||||||
|
void PMU_EnableBandgapSelfBiasBeforePowerDown(void)
|
||||||
|
{
|
||||||
|
uint32_t temp32;
|
||||||
|
|
||||||
|
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
|
||||||
|
temp32 &= ~AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;
|
||||||
|
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Init Bandgap.
|
||||||
|
*
|
||||||
|
* param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to pmu_static_bandgap_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
uint32_t temp32;
|
||||||
|
|
||||||
|
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
|
||||||
|
temp32 &= ~(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK |
|
||||||
|
AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK |
|
||||||
|
AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK);
|
||||||
|
temp32 |= ((uint32_t)(config->powerDownOption) &
|
||||||
|
(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK |
|
||||||
|
AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK));
|
||||||
|
temp32 |= AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode);
|
||||||
|
temp32 |= AI_BANDGAP_CTRL0_REFTOP_VBGADJ(config->outputVoltage);
|
||||||
|
temp32 |= AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent);
|
||||||
|
|
||||||
|
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Configures Well bias, such as power source, clock source and so on.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param config Pointer to the pmu_well_bias_config_t structure.
|
||||||
|
*/
|
||||||
|
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL;
|
||||||
|
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK);
|
||||||
|
tmp32 |= ((uint32_t)config->wellBiasOption.wellBiasData &
|
||||||
|
(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK));
|
||||||
|
base->PMU_BIAS_CTRL = tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
tmp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK;
|
||||||
|
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(config->adjustment);
|
||||||
|
base->PMU_BIAS_CTRL2 = tmp32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables/disables the selected body bias.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t.
|
||||||
|
* param enable Used to turn on/off the specific body bias.
|
||||||
|
* - \b true Enable the selected body bias.
|
||||||
|
* - \b false Disable the selected body bias.
|
||||||
|
*/
|
||||||
|
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
(void)memset(config, 0, sizeof(*config));
|
||||||
|
|
||||||
|
config->wellBiasOption.wellBiasData = 0U;
|
||||||
|
config->adjustment = kPMU_Cref0fFCspl0fFDeltaC0fF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Selects the control mode of the Body Bias.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param name The name of the body bias. Please refer to pmu_body_bias_name_t.
|
||||||
|
* param mode The control mode of the Body Bias. Please refer to pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode)
|
||||||
|
{
|
||||||
|
uint32_t temp32;
|
||||||
|
|
||||||
|
switch (name)
|
||||||
|
{
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
case kPMU_FBB_CM7:
|
||||||
|
{
|
||||||
|
temp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK;
|
||||||
|
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(mode);
|
||||||
|
base->PMU_BIAS_CTRL2 = temp32;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
case kPMU_RBB_SOC:
|
||||||
|
{
|
||||||
|
temp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK;
|
||||||
|
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(mode);
|
||||||
|
base->PMU_BIAS_CTRL2 = temp32;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case kPMU_RBB_LPSR:
|
||||||
|
{
|
||||||
|
temp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK;
|
||||||
|
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(mode);
|
||||||
|
base->PMU_BIAS_CTRL2 = temp32;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
default:
|
||||||
|
/* This branch should never be hit. */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Enables/disables the selected body bias.
|
||||||
|
*
|
||||||
|
* param base PMU peripheral base address.
|
||||||
|
* param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t.
|
||||||
|
* param enable Used to turn on/off the specific body bias.
|
||||||
|
* - \b true Enable the selected body bias.
|
||||||
|
* - \b false Disable the selected body bias.
|
||||||
|
*/
|
||||||
|
void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable)
|
||||||
|
{
|
||||||
|
uint32_t tmp32;
|
||||||
|
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
switch (name)
|
||||||
|
{
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
case kPMU_FBB_CM7:
|
||||||
|
{
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL;
|
||||||
|
tmp32 &= ~PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK;
|
||||||
|
tmp32 |= PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK;
|
||||||
|
base->PMU_BIAS_CTRL = tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
|
||||||
|
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(1U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
|
||||||
|
base->PMU_BIAS_CTRL2 = tmp32;
|
||||||
|
|
||||||
|
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
|
||||||
|
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
case kPMU_RBB_SOC:
|
||||||
|
{
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL;
|
||||||
|
tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK);
|
||||||
|
base->PMU_BIAS_CTRL = tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
|
||||||
|
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(2U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
|
||||||
|
base->PMU_BIAS_CTRL2 = tmp32;
|
||||||
|
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
|
||||||
|
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case kPMU_RBB_LPSR:
|
||||||
|
{
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL;
|
||||||
|
tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK);
|
||||||
|
base->PMU_BIAS_CTRL = tmp32;
|
||||||
|
|
||||||
|
tmp32 = base->PMU_BIAS_CTRL2;
|
||||||
|
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
|
||||||
|
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(4U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
|
||||||
|
base->PMU_BIAS_CTRL2 = tmp32;
|
||||||
|
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
|
||||||
|
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
default:
|
||||||
|
/* This branch should never be hit. */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
base->PMU_BIAS_CTRL2 &=
|
||||||
|
~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Controls the ON/OFF of the selected body bias in the certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
uint32_t bodyBiasEnableRegArray[] = PMU_BODY_BIAS_ENABLE_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) = ~setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Controls the ON/OFF of the selected Body Bias' Wbias power switch in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
|
||||||
|
* param setpointMap The map of setpoints that the specific body bias's wbias power switch will be turn on in those
|
||||||
|
* setpoints, this value should be the OR'ed Value of _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
uint32_t BBStandbyEnableRegArray[] = PMU_BODY_BIAS_STBY_EN_REGISTERS;
|
||||||
|
|
||||||
|
(*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) = setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Gets the default config of body bias in GPC mode.
|
||||||
|
*
|
||||||
|
* param config Pointer to the structure pmu_gpc_body_bias_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
config->PWELLRegulatorSize = 1U;
|
||||||
|
config->NWELLRegulatorSize = 1U;
|
||||||
|
config->oscillatorSize = 7U;
|
||||||
|
config->regulatorStrength = 5U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the config of the selected Body Bias in GPC mode.
|
||||||
|
*
|
||||||
|
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
|
||||||
|
* param config Pointer to the structure pmu_gpc_body_bias_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config)
|
||||||
|
{
|
||||||
|
assert(config != NULL);
|
||||||
|
|
||||||
|
uint32_t bodyBiasConfigRegArray[] = PMU_BODY_BIAS_CONFIGURE_REGISTERS;
|
||||||
|
uint32_t temp32;
|
||||||
|
|
||||||
|
temp32 = (*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]);
|
||||||
|
temp32 &=
|
||||||
|
(ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK |
|
||||||
|
ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK);
|
||||||
|
temp32 |= ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(config->PWELLRegulatorSize) |
|
||||||
|
ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(config->NWELLRegulatorSize) |
|
||||||
|
ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(config->oscillatorSize) |
|
||||||
|
ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(config->regulatorStrength);
|
||||||
|
(*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]) = temp32;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,102 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file pin_mux.c
|
||||||
|
* @brief support imxrt1176-sbc pinmux
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: pin_mux.c
|
||||||
|
Description: support imxrt1176-sbc pinmux
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
!!GlobalInfo
|
||||||
|
product: Pins v7.0
|
||||||
|
processor: MIMXRT1176xxxxx
|
||||||
|
package_id: MIMXRT1176DVMAA
|
||||||
|
mcu_data: ksdk2_0
|
||||||
|
processor_version: 0.0.2
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
#include "pin_mux.h"
|
||||||
|
|
||||||
|
/* FUNCTION ************************************************************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : BOARD_InitBootPins
|
||||||
|
* Description : Calls initialization functions.
|
||||||
|
*
|
||||||
|
* END ****************************************************************************************************************/
|
||||||
|
void BOARD_InitBootPins(void) {
|
||||||
|
BOARD_InitPins();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||||
|
BOARD_InitPins:
|
||||||
|
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
|
||||||
|
- pin_list:
|
||||||
|
- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
|
||||||
|
open_drain: Disable, drive_strength: High, slew_rate: Slow}
|
||||||
|
- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
|
||||||
|
open_drain: Disable, drive_strength: High, slew_rate: Slow}
|
||||||
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* FUNCTION ************************************************************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : BOARD_InitPins
|
||||||
|
* Description : Configures pin routing and optionally pin electrical features.
|
||||||
|
*
|
||||||
|
* END ****************************************************************************************************************/
|
||||||
|
void BOARD_InitPins(void) {
|
||||||
|
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
|
||||||
|
|
||||||
|
IOMUXC_SetPinMux(
|
||||||
|
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
|
||||||
|
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||||
|
IOMUXC_SetPinMux(
|
||||||
|
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
|
||||||
|
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||||
|
IOMUXC_SetPinConfig(
|
||||||
|
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
|
||||||
|
0x02U); /* Slew Rate Field: Slow Slew Rate
|
||||||
|
Drive Strength Field: high driver
|
||||||
|
Pull / Keep Select Field: Pull Disable, Highz
|
||||||
|
Pull Up / Down Config. Field: Weak pull down
|
||||||
|
Open Drain Field: Disabled */
|
||||||
|
IOMUXC_SetPinConfig(
|
||||||
|
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
|
||||||
|
0x02U); /* Slew Rate Field: Slow Slew Rate
|
||||||
|
Drive Strength Field: high driver
|
||||||
|
Pull / Keep Select Field: Pull Disable, Highz
|
||||||
|
Pull Up / Down Config. Field: Weak pull down
|
||||||
|
Open Drain Field: Disabled */
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* EOF
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
@ -0,0 +1,84 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file pin_mux.h
|
||||||
|
* @brief support imxrt1176-sbc pinmux
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: pin_mux.h
|
||||||
|
Description: support imxrt1176-sbc pinmux
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||||
|
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _PIN_MUX_H_
|
||||||
|
#define _PIN_MUX_H_
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief Direction type */
|
||||||
|
typedef enum _pin_mux_direction
|
||||||
|
{
|
||||||
|
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||||
|
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||||
|
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||||
|
} pin_mux_direction_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup pin_mux
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* API
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Calls initialization functions.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitBootPins(void);
|
||||||
|
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Configures pin routing and optionally pin electrical features.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_InitPins(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* _PIN_MUX_H_ */
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* EOF
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
@ -0,0 +1,197 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Processors: MIMXRT1176AVM8A_cm4
|
||||||
|
** MIMXRT1176CVM8A_cm4
|
||||||
|
** MIMXRT1176DVMAA_cm4
|
||||||
|
**
|
||||||
|
** Compilers: Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
** Keil ARM C/C++ Compiler
|
||||||
|
** MCUXpresso Compiler
|
||||||
|
**
|
||||||
|
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210615
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Provides a system configuration function and a global variable that
|
||||||
|
** contains the system frequency. It configures the device and initializes
|
||||||
|
** the oscillator (PLL) that is part of the microcontroller device.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update header files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @file MIMXRT1176_cm4
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021-06-15
|
||||||
|
* @brief Device specific configuration file for MIMXRT1176_cm4 (implementation
|
||||||
|
* file)
|
||||||
|
*
|
||||||
|
* Provides a system configuration function and a global variable that contains
|
||||||
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
|
* (PLL) that is part of the microcontroller device.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file system_MIMXRT1176_cm4.c
|
||||||
|
* @brief support imxrt1176-sbc cm4 core system init
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: system_MIMXRT1176_cm4.c
|
||||||
|
Description: support imxrt1176-sbc cm4 system init
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- Core clock
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemInit()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void SystemInit (void) {
|
||||||
|
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||||
|
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||||
|
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||||
|
|
||||||
|
#if defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
|
||||||
|
SCB->VTOR = (uint32_t)g_pfnVectors;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Watchdog disable */
|
||||||
|
|
||||||
|
#if (DISABLE_WDOG)
|
||||||
|
if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
|
||||||
|
{
|
||||||
|
WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
|
||||||
|
}
|
||||||
|
if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
|
||||||
|
{
|
||||||
|
WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
|
||||||
|
}
|
||||||
|
if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
|
||||||
|
{
|
||||||
|
RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTWDOG3->CNT = 0xC520U;
|
||||||
|
RTWDOG3->CNT = 0xD928U;
|
||||||
|
}
|
||||||
|
RTWDOG3->TOVAL = 0xFFFF;
|
||||||
|
RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||||
|
if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
|
||||||
|
{
|
||||||
|
RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTWDOG4->CNT = 0xC520U;
|
||||||
|
RTWDOG4->CNT = 0xD928U;
|
||||||
|
}
|
||||||
|
RTWDOG4->TOVAL = 0xFFFF;
|
||||||
|
RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||||
|
#endif /* (DISABLE_WDOG) */
|
||||||
|
|
||||||
|
/* Disable Systick which might be enabled by bootrom */
|
||||||
|
if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
|
||||||
|
{
|
||||||
|
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize Cache */
|
||||||
|
/* Enable Code Bus Cache */
|
||||||
|
if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK))
|
||||||
|
{
|
||||||
|
/* set command to invalidate all ways, and write GO bit to initiate command */
|
||||||
|
LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
|
||||||
|
/* Wait until the command completes */
|
||||||
|
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
|
||||||
|
}
|
||||||
|
/* Enable cache, enable write buffer */
|
||||||
|
LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable System Bus Cache */
|
||||||
|
if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK))
|
||||||
|
{
|
||||||
|
/* set command to invalidate all ways, and write GO bit to initiate command */
|
||||||
|
LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
|
||||||
|
/* Wait until the command completes */
|
||||||
|
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
|
||||||
|
}
|
||||||
|
/* Enable cache, enable write buffer */
|
||||||
|
LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear bit 13 to its reset value since it might be set by ROM. */
|
||||||
|
IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
|
||||||
|
|
||||||
|
#if defined(ROM_ECC_ENABLED)
|
||||||
|
/* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
|
||||||
|
Save SRSR to SRC->GPR[11] so that application can still check SRSR value from SRC->GPR[11]. */
|
||||||
|
SRC->GPR[11] = SRC->SRSR;
|
||||||
|
/* clear SRSR */
|
||||||
|
SRC->SRSR = 0xFFFFFFFFU;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable entry to thread mode when divide by zero */
|
||||||
|
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
|
||||||
|
SystemInitHook();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemCoreClockUpdate()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void SystemCoreClockUpdate (void) {
|
||||||
|
|
||||||
|
/* TBD */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemInitHook()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||||
|
/* Void implementation of the weak function. */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,180 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Processors: MIMXRT1176AVM8A_cm7
|
||||||
|
** MIMXRT1176CVM8A_cm7
|
||||||
|
** MIMXRT1176DVMAA_cm7
|
||||||
|
**
|
||||||
|
** Compilers: Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
** Keil ARM C/C++ Compiler
|
||||||
|
** MCUXpresso Compiler
|
||||||
|
**
|
||||||
|
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210615
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Provides a system configuration function and a global variable that
|
||||||
|
** contains the system frequency. It configures the device and initializes
|
||||||
|
** the oscillator (PLL) that is part of the microcontroller device.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update header files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @file MIMXRT1176_cm7
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021-06-15
|
||||||
|
* @brief Device specific configuration file for MIMXRT1176_cm7 (implementation
|
||||||
|
* file)
|
||||||
|
*
|
||||||
|
* Provides a system configuration function and a global variable that contains
|
||||||
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
|
* (PLL) that is part of the microcontroller device.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file system_MIMXRT1176_cm7.c
|
||||||
|
* @brief support imxrt1176-sbc cm7 core system init
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: system_MIMXRT1176_cm7.c
|
||||||
|
Description: support imxrt1176-sbc cm7 system init
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- Core clock
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemInit()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void SystemInit (void) {
|
||||||
|
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||||
|
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||||
|
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||||
|
|
||||||
|
#if defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
|
||||||
|
SCB->VTOR = (uint32_t)g_pfnVectors;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Watchdog disable */
|
||||||
|
|
||||||
|
#if (DISABLE_WDOG)
|
||||||
|
if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
|
||||||
|
{
|
||||||
|
WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
|
||||||
|
}
|
||||||
|
if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
|
||||||
|
{
|
||||||
|
WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
|
||||||
|
}
|
||||||
|
if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
|
||||||
|
{
|
||||||
|
RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTWDOG3->CNT = 0xC520U;
|
||||||
|
RTWDOG3->CNT = 0xD928U;
|
||||||
|
}
|
||||||
|
RTWDOG3->TOVAL = 0xFFFF;
|
||||||
|
RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||||
|
if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
|
||||||
|
{
|
||||||
|
RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTWDOG4->CNT = 0xC520U;
|
||||||
|
RTWDOG4->CNT = 0xD928U;
|
||||||
|
}
|
||||||
|
RTWDOG4->TOVAL = 0xFFFF;
|
||||||
|
RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||||
|
#endif /* (DISABLE_WDOG) */
|
||||||
|
|
||||||
|
/* Disable Systick which might be enabled by bootrom */
|
||||||
|
if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
|
||||||
|
{
|
||||||
|
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable instruction and data caches */
|
||||||
|
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
|
||||||
|
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
|
||||||
|
SCB_EnableICache();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Clear bit 13 to its reset value since it might be set by ROM. */
|
||||||
|
IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
|
||||||
|
|
||||||
|
#if defined(ROM_ECC_ENABLED)
|
||||||
|
/* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
|
||||||
|
Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */
|
||||||
|
SRC->GPR[10] = SRC->SRSR;
|
||||||
|
/* clear SRSR */
|
||||||
|
SRC->SRSR = 0xFFFFFFFFU;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable entry to thread mode when divide by zero */
|
||||||
|
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
|
||||||
|
SystemInitHook();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemCoreClockUpdate()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void SystemCoreClockUpdate (void) {
|
||||||
|
|
||||||
|
/* TBD */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- SystemInitHook()
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||||
|
/* Void implementation of the weak function. */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
|
||||||
|
config PIN_BUS_NAME
|
||||||
|
string "pin bus name"
|
||||||
|
default "pin"
|
||||||
|
|
||||||
|
config PIN_DRIVER_NAME
|
||||||
|
string "pin driver name"
|
||||||
|
default "pin_drv"
|
||||||
|
|
||||||
|
config PIN_DEVICE_NAME
|
||||||
|
string "pin device name"
|
||||||
|
default "pin_dev"
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
SRC_FILES := connect_gpio.c fsl_gpio.c
|
||||||
|
|
||||||
|
include $(KERNEL_ROOT)/compiler.mk
|
||||||
|
|
@ -0,0 +1,759 @@
|
||||||
|
/**
|
||||||
|
* @file connect_gpio.c
|
||||||
|
* @brief support imxrt1176-sbc gpio
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <connect_gpio.h>
|
||||||
|
#include <fsl_gpio.h>
|
||||||
|
#include <fsl_iomuxc.h>
|
||||||
|
|
||||||
|
struct PinIndex
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
GPIO_Type *gpio;
|
||||||
|
uint32_t pin;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PinIrq
|
||||||
|
{
|
||||||
|
uint8 port_source;
|
||||||
|
uint8 pin_source;
|
||||||
|
enum IRQn irq_exti_channel;
|
||||||
|
uint32 exti_line;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PinMask
|
||||||
|
{
|
||||||
|
GPIO_Type *gpio;
|
||||||
|
uint32 valid_mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const IRQn_Type irq_tab[10] =
|
||||||
|
{
|
||||||
|
GPIO1_Combined_0_15_IRQn,
|
||||||
|
GPIO1_Combined_16_31_IRQn,
|
||||||
|
GPIO2_Combined_0_15_IRQn,
|
||||||
|
GPIO2_Combined_16_31_IRQn,
|
||||||
|
GPIO3_Combined_0_15_IRQn,
|
||||||
|
GPIO3_Combined_16_31_IRQn,
|
||||||
|
GPIO4_Combined_0_15_IRQn,
|
||||||
|
GPIO4_Combined_16_31_IRQn,
|
||||||
|
GPIO5_Combined_0_15_IRQn,
|
||||||
|
GPIO5_Combined_16_31_IRQn
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct PinMask pin_mask[] =
|
||||||
|
{
|
||||||
|
{GPIO1, 0xFFFFFFFF}, /* GPIO1 */
|
||||||
|
{GPIO2, 0xFFFFFFFF}, /* GPIO2 */
|
||||||
|
{GPIO3, 0x0FFFFFFF}, /* GPIO3,28~31 not supported */
|
||||||
|
{GPIO4, 0xFFFFFFFF}, /* GPIO4 */
|
||||||
|
{GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PinIrqHdr pin_irq_hdr_tab[] =
|
||||||
|
{
|
||||||
|
/* GPIO1 */
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
/* GPIO2 */
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
/* GPIO3 */
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
/* GPIO4 */
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
/* GPIO5 */
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
{-1, 0, NONE, NONE},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MUX_BASE 0x401f8014
|
||||||
|
#define CONFIG_BASE 0x401f8204
|
||||||
|
|
||||||
|
#define GPIO5_MUX_BASE 0x400A8000
|
||||||
|
#define GPIO5_CONFIG_BASE 0x400A8018
|
||||||
|
|
||||||
|
const uint8_t reg_offset[] =
|
||||||
|
{
|
||||||
|
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
|
||||||
|
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
|
||||||
|
112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
|
||||||
|
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int GetPin(struct PinIndex *pin_index, uint8_t pin)
|
||||||
|
{
|
||||||
|
pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5
|
||||||
|
pin_index->pin = pin & 31;//each GPIOx support 32 io
|
||||||
|
|
||||||
|
if ((pin_index->index > 4) || ((pin_mask[pin_index->index].valid_mask & (1 << pin_index->pin)) == 0)) {
|
||||||
|
KPrintf("GetPin unsupport pin index %u pin %u\n", pin_index->index, pin_index->pin);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
pin_index->gpio = pin_mask[pin_index->index].gpio;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin)
|
||||||
|
{
|
||||||
|
gpio_pin_config_t gpio_config;
|
||||||
|
uint32_t config_value = 0;
|
||||||
|
NULL_PARAM_CHECK(pin_index);
|
||||||
|
|
||||||
|
gpio_config.outputLogic = 0;
|
||||||
|
gpio_config.interruptMode = kGPIO_NoIntmode;
|
||||||
|
|
||||||
|
switch (mode)
|
||||||
|
{
|
||||||
|
case GPIO_CFG_OUTPUT:
|
||||||
|
gpio_config.direction = kGPIO_DigitalOutput;
|
||||||
|
config_value = 0x0030U; /* Drive Strength R0/6 */
|
||||||
|
break;
|
||||||
|
case GPIO_CFG_INPUT:
|
||||||
|
gpio_config.direction = kGPIO_DigitalInput;
|
||||||
|
config_value = 0x0830U; /* Open Drain Enable */
|
||||||
|
break;
|
||||||
|
case GPIO_CFG_INPUT_PULLUP:
|
||||||
|
gpio_config.direction = kGPIO_DigitalInput;
|
||||||
|
config_value = 0xB030U; /* 100K Ohm Pull Up */
|
||||||
|
break;
|
||||||
|
case GPIO_CFG_INPUT_PULLDOWN:
|
||||||
|
gpio_config.direction = kGPIO_DigitalInput;
|
||||||
|
config_value = 0x3030U; /* 100K Ohm Pull Down */
|
||||||
|
break;
|
||||||
|
case GPIO_CFG_OUTPUT_OD:
|
||||||
|
gpio_config.direction = kGPIO_DigitalOutput;
|
||||||
|
config_value = 0x0830U; /* Open Drain Enable */
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pin_mask[pin_index->index].gpio != GPIO5) {
|
||||||
|
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||||
|
IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
|
||||||
|
IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
|
||||||
|
} else {
|
||||||
|
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
|
||||||
|
IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1);
|
||||||
|
IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value);
|
||||||
|
}
|
||||||
|
|
||||||
|
GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config);
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
|
||||||
|
{
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
x_base level = CriticalAreaLock();
|
||||||
|
if (pin_irq_hdr_tab[pin].pin == pin &&
|
||||||
|
pin_irq_hdr_tab[pin].hdr == hdr &&
|
||||||
|
pin_irq_hdr_tab[pin].mode == mode &&
|
||||||
|
pin_irq_hdr_tab[pin].args == args
|
||||||
|
)
|
||||||
|
{
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pin_irq_hdr_tab[pin].pin != -1) {
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
return -EDEV_BUSY;
|
||||||
|
}
|
||||||
|
pin_irq_hdr_tab[pin].pin = pin;
|
||||||
|
pin_irq_hdr_tab[pin].hdr = hdr;
|
||||||
|
pin_irq_hdr_tab[pin].mode = mode;
|
||||||
|
pin_irq_hdr_tab[pin].args = args;
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 GpioIrqFree(int32 pin)
|
||||||
|
{
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
x_base level = CriticalAreaLock();
|
||||||
|
if (pin_irq_hdr_tab[pin].pin == -1){
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
pin_irq_hdr_tab[pin].pin = -1;
|
||||||
|
pin_irq_hdr_tab[pin].hdr = NONE;
|
||||||
|
pin_irq_hdr_tab[pin].mode = 0;
|
||||||
|
pin_irq_hdr_tab[pin].args = NONE;
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32 GpioIrqEnable(x_base pin)
|
||||||
|
{
|
||||||
|
uint8_t irq_index;
|
||||||
|
gpio_interrupt_mode_t gpio_int_mode;
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
x_base level = CriticalAreaLock();
|
||||||
|
if (pin_irq_hdr_tab[pin].pin == -1) {
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
return -ENONESYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (pin_irq_hdr_tab[pin].mode)
|
||||||
|
{
|
||||||
|
case GPIO_IRQ_EDGE_RISING:
|
||||||
|
gpio_int_mode = kGPIO_IntRisingEdge;
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_EDGE_FALLING:
|
||||||
|
gpio_int_mode = kGPIO_IntFallingEdge;
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_EDGE_BOTH:
|
||||||
|
gpio_int_mode = kGPIO_IntRisingOrFallingEdge;
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_LEVEL_HIGH:
|
||||||
|
gpio_int_mode = kGPIO_IntHighLevel;
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_LEVEL_LOW:
|
||||||
|
gpio_int_mode = kGPIO_IntLowLevel;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
gpio_int_mode = kGPIO_IntRisingEdge;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
irq_index = (pin_index.index << 1) + (pin_index.pin >> 4);
|
||||||
|
GPIO_PinSetInterruptConfig(pin_index.gpio, pin_index.pin, gpio_int_mode);
|
||||||
|
GPIO_PortEnableInterrupts(pin_index.gpio, 1U << pin_index.pin);
|
||||||
|
NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
||||||
|
EnableIRQ(irq_tab[irq_index]);
|
||||||
|
CriticalAreaUnLock(level);
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int32 GpioIrqDisable(x_base pin)
|
||||||
|
{
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
GPIO_PortDisableInterrupts(pin_index.gpio, 1U << pin_index.pin);
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 Imxrt1052PinConfigure(struct PinParam *param)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(param);
|
||||||
|
int ret = EOK;
|
||||||
|
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, param->pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch(param->cmd)
|
||||||
|
{
|
||||||
|
case GPIO_CONFIG_MODE:
|
||||||
|
GpioConfigMode(param->mode, &pin_index, param->pin);
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_REGISTER:
|
||||||
|
ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_FREE:
|
||||||
|
ret = GpioIrqFree(param->pin);
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_ENABLE:
|
||||||
|
ret = GpioIrqEnable(param->pin);
|
||||||
|
break;
|
||||||
|
case GPIO_IRQ_DISABLE:
|
||||||
|
ret = GpioIrqDisable(param->pin);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
ret = -EINVALED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 Imxrt1052PinInit(void)
|
||||||
|
{
|
||||||
|
static x_bool pin_init_flag = RET_FALSE;
|
||||||
|
|
||||||
|
if (!pin_init_flag) {
|
||||||
|
pin_init_flag = RET_TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 Imxrt1052GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(drv);
|
||||||
|
NULL_PARAM_CHECK(configure_info);
|
||||||
|
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
struct PinParam *param;
|
||||||
|
|
||||||
|
switch (configure_info->configure_cmd)
|
||||||
|
{
|
||||||
|
case OPE_INT:
|
||||||
|
ret = Imxrt1052PinInit();
|
||||||
|
break;
|
||||||
|
case OPE_CFG:
|
||||||
|
param = (struct PinParam *)configure_info->private_data;
|
||||||
|
ret = Imxrt1052PinConfigure(param);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32 Imxrt1052PinWrite(void *dev, struct BusBlockWriteParam *write_param)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(dev);
|
||||||
|
NULL_PARAM_CHECK(write_param);
|
||||||
|
struct PinStat *pin_stat = (struct PinStat *)write_param->buffer;
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin_stat->pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (GPIO_LOW == pin_stat->val) {
|
||||||
|
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 0);
|
||||||
|
} else {
|
||||||
|
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 1);
|
||||||
|
}
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32 Imxrt1052PinRead(void *dev, struct BusBlockReadParam *read_param)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(dev);
|
||||||
|
NULL_PARAM_CHECK(read_param);
|
||||||
|
struct PinStat *pin_stat = (struct PinStat *)read_param->buffer;
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, pin_stat->pin) < 0) {
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(GPIO_LOW == GPIO_PinRead(pin_index.gpio, pin_index.pin)) {
|
||||||
|
pin_stat->val = GPIO_LOW;
|
||||||
|
} else {
|
||||||
|
pin_stat->val = GPIO_HIGH;
|
||||||
|
}
|
||||||
|
return pin_stat->val;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct PinDevDone dev_done =
|
||||||
|
{
|
||||||
|
.open = NONE,
|
||||||
|
.close = NONE,
|
||||||
|
.write = Imxrt1052PinWrite,
|
||||||
|
.read = Imxrt1052PinRead,
|
||||||
|
};
|
||||||
|
|
||||||
|
int Imxrt1176HwGpioInit(void)
|
||||||
|
{
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
|
||||||
|
static struct PinBus pin;
|
||||||
|
|
||||||
|
ret = PinBusInit(&pin, PIN_BUS_NAME);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("gpio bus init error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct PinDriver drv;
|
||||||
|
drv.configure = Imxrt1052GpioDrvConfigure;
|
||||||
|
|
||||||
|
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("pin driver init error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("pin driver attach error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct PinHardwareDevice dev;
|
||||||
|
dev.dev_done = &dev_done;
|
||||||
|
|
||||||
|
ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("pin device register error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("pin device register error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Type *gpio)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
uint32_t isr_status, pin;
|
||||||
|
struct PinIndex pin_index;
|
||||||
|
|
||||||
|
isr_status = GPIO_PortGetInterruptFlags(gpio) & gpio->IMR;
|
||||||
|
|
||||||
|
for (i = pin_start; i <= pin_start + 15 ; i ++) {
|
||||||
|
|
||||||
|
if (GetPin(&pin_index, i + index_offset) < 0) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isr_status & (1 << i)) {
|
||||||
|
GPIO_PortClearInterruptFlags(gpio, (1 << i));
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
pin = index_offset + i;
|
||||||
|
if (pin_irq_hdr_tab[pin].hdr) {
|
||||||
|
pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void GPIO1_0_15_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(0, 0, GPIO1);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO1_Combined_0_15_IRQn, GPIO1_0_15_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO1_16_31_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(0, 15, GPIO1);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO1_Combined_16_31_IRQn, GPIO1_16_31_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO2_0_15_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(32, 0, GPIO2);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO2_Combined_0_15_IRQn, GPIO2_0_15_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO2_16_31_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(32, 15, GPIO2);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO2_Combined_16_31_IRQn, GPIO2_16_31_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO3_0_15_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(64, 0, GPIO3);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO3_Combined_0_15_IRQn, GPIO3_0_15_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO3_16_31_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(64, 15, GPIO3);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO3_Combined_16_31_IRQn, GPIO3_16_31_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO4_0_15_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(96, 0, GPIO4);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO4_Combined_0_15_IRQn, GPIO4_0_15_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO4_16_31_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(96, 15, GPIO4);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO4_Combined_16_31_IRQn, GPIO4_16_31_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO5_0_15_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(128, 0, GPIO5);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO5_Combined_0_15_IRQn, GPIO5_0_15_IRQHandler, NONE);
|
||||||
|
|
||||||
|
void GPIO5_16_31_IRQHandler(int irq_num, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
PinIrqHdr(128, 15, GPIO5);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(GPIO5_Combined_16_31_IRQn, GPIO5_16_31_IRQHandler, NONE);
|
||||||
|
|
||||||
|
#ifdef GPIO_LED_TEST
|
||||||
|
static void GpioLedDelay(void)
|
||||||
|
{
|
||||||
|
volatile uint32_t i = 0;
|
||||||
|
for (i = 0; i < 8000000; ++i)
|
||||||
|
{
|
||||||
|
__asm("NOP"); /* delay */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void GpioLedTest(void)
|
||||||
|
{
|
||||||
|
BusType pin;
|
||||||
|
struct BusConfigureInfo configure_info;
|
||||||
|
struct BusBlockWriteParam write_param;
|
||||||
|
|
||||||
|
int ret = 0;
|
||||||
|
bool pinSet = 1;
|
||||||
|
|
||||||
|
pin = BusFind(PIN_BUS_NAME);
|
||||||
|
if (!pin) {
|
||||||
|
KPrintf("find %s failed!\n", PIN_BUS_NAME);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME);
|
||||||
|
pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME);
|
||||||
|
|
||||||
|
configure_info.configure_cmd = OPE_INT;
|
||||||
|
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct PinParam led_gpio_param;
|
||||||
|
struct PinStat led_gpio_stat;
|
||||||
|
|
||||||
|
/* config led pin as output*/
|
||||||
|
led_gpio_param.cmd = GPIO_CONFIG_MODE;
|
||||||
|
led_gpio_param.pin = IMXRT_GET_PIN(1, 9);
|
||||||
|
led_gpio_param.mode = GPIO_CFG_OUTPUT_OD;
|
||||||
|
|
||||||
|
configure_info.configure_cmd = OPE_CFG;
|
||||||
|
configure_info.private_data = (void *)&led_gpio_param;
|
||||||
|
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
|
||||||
|
if (ret != EOK) {
|
||||||
|
KPrintf("config pin %d failed!\n", IMXRT_GET_PIN(1, 9));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
|
||||||
|
GpioLedDelay();
|
||||||
|
|
||||||
|
if (pinSet) {
|
||||||
|
/* set led pin as high*/
|
||||||
|
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
|
||||||
|
led_gpio_stat.val = GPIO_HIGH;
|
||||||
|
write_param.buffer = (void *)&led_gpio_stat;
|
||||||
|
BusDevWriteData(pin->owner_haldev, &write_param);
|
||||||
|
pinSet = 0;
|
||||||
|
} else {
|
||||||
|
/* set led pin as low*/
|
||||||
|
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
|
||||||
|
led_gpio_stat.val = GPIO_LOW;
|
||||||
|
write_param.buffer = (void *)&led_gpio_stat;
|
||||||
|
BusDevWriteData(pin->owner_haldev, &write_param);
|
||||||
|
pinSet = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
|
||||||
|
GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,198 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2017, 2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_gpio.c
|
||||||
|
* @brief support imxrt1176-sbc gpio
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_gpio.c
|
||||||
|
Description: support imxrt1176-sbc gpio
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.igpio"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/* Array of GPIO peripheral base address. */
|
||||||
|
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
|
||||||
|
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/* Array of GPIO clock name. */
|
||||||
|
static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the GPIO instance according to the GPIO base
|
||||||
|
*
|
||||||
|
* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||||||
|
* @retval GPIO instance
|
||||||
|
*/
|
||||||
|
static uint32_t GPIO_GetInstance(GPIO_Type *base);
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
static uint32_t GPIO_GetInstance(GPIO_Type *base)
|
||||||
|
{
|
||||||
|
uint32_t instance;
|
||||||
|
|
||||||
|
/* Find the instance index from base address mappings. */
|
||||||
|
for (instance = 0U; instance < ARRAY_SIZE(s_gpioBases); instance++)
|
||||||
|
{
|
||||||
|
if (s_gpioBases[instance] == base)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(instance < ARRAY_SIZE(s_gpioBases));
|
||||||
|
|
||||||
|
return instance;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Initializes the GPIO peripheral according to the specified
|
||||||
|
* parameters in the initConfig.
|
||||||
|
*
|
||||||
|
* param base GPIO base pointer.
|
||||||
|
* param pin Specifies the pin number
|
||||||
|
* param initConfig pointer to a ref gpio_pin_config_t structure that
|
||||||
|
* contains the configuration information.
|
||||||
|
*/
|
||||||
|
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
|
||||||
|
{
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/* Enable GPIO clock. */
|
||||||
|
uint32_t instance = GPIO_GetInstance(base);
|
||||||
|
|
||||||
|
/* If The clock IP is valid, enable the clock gate. */
|
||||||
|
if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
|
||||||
|
{
|
||||||
|
(void)CLOCK_EnableClock(s_gpioClock[instance]);
|
||||||
|
}
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
|
||||||
|
/* Register reset to default value */
|
||||||
|
base->IMR &= ~(1UL << pin);
|
||||||
|
|
||||||
|
/* Configure GPIO pin direction */
|
||||||
|
if (Config->direction == kGPIO_DigitalInput)
|
||||||
|
{
|
||||||
|
base->GDIR &= ~(1UL << pin);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIO_PinWrite(base, pin, Config->outputLogic);
|
||||||
|
base->GDIR |= (1UL << pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure GPIO pin interrupt mode */
|
||||||
|
GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||||
|
*
|
||||||
|
* param base GPIO base pointer.
|
||||||
|
* param pin GPIO port pin number.
|
||||||
|
* param output GPIOpin output logic level.
|
||||||
|
* - 0: corresponding pin output low-logic level.
|
||||||
|
* - 1: corresponding pin output high-logic level.
|
||||||
|
*/
|
||||||
|
void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
|
||||||
|
{
|
||||||
|
assert(pin < 32U);
|
||||||
|
if (output == 0U)
|
||||||
|
{
|
||||||
|
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
|
||||||
|
base->DR_CLEAR = (1UL << pin);
|
||||||
|
#else
|
||||||
|
base->DR &= ~(1UL << pin); /* Set pin output to low level.*/
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
|
||||||
|
base->DR_SET = (1UL << pin);
|
||||||
|
#else
|
||||||
|
base->DR |= (1UL << pin); /* Set pin output to high level.*/
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* brief Sets the current pin interrupt mode.
|
||||||
|
*
|
||||||
|
* param base GPIO base pointer.
|
||||||
|
* param pin GPIO port pin number.
|
||||||
|
* param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure
|
||||||
|
* that contains the interrupt mode information.
|
||||||
|
*/
|
||||||
|
void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
|
||||||
|
{
|
||||||
|
volatile uint32_t *icr;
|
||||||
|
uint32_t icrShift;
|
||||||
|
|
||||||
|
icrShift = pin;
|
||||||
|
|
||||||
|
/* Register reset to default value */
|
||||||
|
base->EDGE_SEL &= ~(1UL << pin);
|
||||||
|
|
||||||
|
if (pin < 16U)
|
||||||
|
{
|
||||||
|
icr = &(base->ICR1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
icr = &(base->ICR2);
|
||||||
|
icrShift -= 16U;
|
||||||
|
}
|
||||||
|
switch (pinInterruptMode)
|
||||||
|
{
|
||||||
|
case (kGPIO_IntLowLevel):
|
||||||
|
*icr &= ~(3UL << (2UL * icrShift));
|
||||||
|
break;
|
||||||
|
case (kGPIO_IntHighLevel):
|
||||||
|
*icr = (*icr & (~(3UL << (2UL * icrShift)))) | (1UL << (2UL * icrShift));
|
||||||
|
break;
|
||||||
|
case (kGPIO_IntRisingEdge):
|
||||||
|
*icr = (*icr & (~(3UL << (2UL * icrShift)))) | (2UL << (2UL * icrShift));
|
||||||
|
break;
|
||||||
|
case (kGPIO_IntFallingEdge):
|
||||||
|
*icr |= (3UL << (2UL * icrShift));
|
||||||
|
break;
|
||||||
|
case (kGPIO_IntRisingOrFallingEdge):
|
||||||
|
base->EDGE_SEL |= (1UL << pin);
|
||||||
|
break;
|
||||||
|
default:; /* Intentional empty default */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,884 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210910
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Chip specific module features.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update feature files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file MIMXRT1176_cm4_features.h
|
||||||
|
* @brief support imxrt1176-sbc cm4 features
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: MIMXRT1176_cm4_features.h
|
||||||
|
Description: support imxrt1176-sbc cm4 features
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _MIMXRT1176_cm4_FEATURES_H_
|
||||||
|
#define _MIMXRT1176_cm4_FEATURES_H_
|
||||||
|
|
||||||
|
/* SOC module features */
|
||||||
|
|
||||||
|
/* @brief ACMP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ACMP_COUNT (4)
|
||||||
|
/* @brief AOI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_AOI_COUNT (2)
|
||||||
|
/* @brief ASRC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ASRC_COUNT (1)
|
||||||
|
/* @brief CAAM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CAAM_COUNT (1)
|
||||||
|
/* @brief CAU availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CAU_COUNT (1)
|
||||||
|
/* @brief CCM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CCM_COUNT (1)
|
||||||
|
/* @brief CSI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CSI_COUNT (1)
|
||||||
|
/* @brief CDOG availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CDOG_COUNT (1)
|
||||||
|
/* @brief DAC12 availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DAC12_COUNT (1)
|
||||||
|
/* @brief DCDC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
|
||||||
|
/* @brief DMAMUX availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
|
||||||
|
/* @brief EDMA availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
|
||||||
|
/* @brief EMVSIM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
|
||||||
|
/* @brief ENC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENC_COUNT (4)
|
||||||
|
/* @brief ENET availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENET_COUNT (2)
|
||||||
|
/* @brief ENET_QOS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENET_QOS_COUNT (1)
|
||||||
|
/* @brief EWM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EWM_COUNT (1)
|
||||||
|
/* @brief FLEXCAN availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (3)
|
||||||
|
/* @brief FLEXIO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
|
||||||
|
/* @brief FLEXRAM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
|
||||||
|
/* @brief FLEXSPI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (2)
|
||||||
|
/* @brief GPT availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_GPT_COUNT (6)
|
||||||
|
/* @brief I2S availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_I2S_COUNT (4)
|
||||||
|
/* @brief IEE availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IEE_COUNT (1)
|
||||||
|
/* @brief IGPIO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IGPIO_COUNT (15)
|
||||||
|
/* @brief IOMUXC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
|
||||||
|
/* @brief IOMUXC_LPSR availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (1)
|
||||||
|
/* @brief KPP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_KPP_COUNT (1)
|
||||||
|
/* @brief LCDIF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
|
||||||
|
/* @brief LMEM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LMEM_COUNT (1)
|
||||||
|
/* @brief LPADC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPADC_COUNT (2)
|
||||||
|
/* @brief LPI2C availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPI2C_COUNT (6)
|
||||||
|
/* @brief LPSPI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPSPI_COUNT (6)
|
||||||
|
/* @brief LPUART availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPUART_COUNT (12)
|
||||||
|
/* @brief MCM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_MCM_COUNT (1)
|
||||||
|
/* @brief MU availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_MU_COUNT (1)
|
||||||
|
/* @brief OCOTP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
|
||||||
|
/* @brief OTFAD availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_OTFAD_COUNT (2)
|
||||||
|
/* @brief PDM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PDM_COUNT (1)
|
||||||
|
/* @brief PIT availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PIT_COUNT (2)
|
||||||
|
/* @brief PWM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PWM_COUNT (4)
|
||||||
|
/* @brief PXP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PXP_COUNT (1)
|
||||||
|
/* @brief PUF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PUF_COUNT (1)
|
||||||
|
/* @brief RDC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_RDC_COUNT (1)
|
||||||
|
/* @brief RDC_SEMAPHORE availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2)
|
||||||
|
/* @brief SEMA4 availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SEMA4_COUNT (1)
|
||||||
|
/* @brief SEMC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
|
||||||
|
/* @brief SNVS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
|
||||||
|
/* @brief SPDIF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
|
||||||
|
/* @brief SRC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SRC_COUNT (1)
|
||||||
|
/* @brief TMR availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_TMR_COUNT (4)
|
||||||
|
/* @brief USBHS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
|
||||||
|
/* @brief USBHSDCD availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2)
|
||||||
|
/* @brief USBNC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
|
||||||
|
/* @brief USBPHY availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
|
||||||
|
/* @brief USDHC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
|
||||||
|
/* @brief WDOG availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
|
||||||
|
/* @brief XBARA availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
|
||||||
|
/* @brief XBARB availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
|
||||||
|
/* @brief ROM API Availability */
|
||||||
|
#define FSL_FEATURE_BOOT_ROM_HAS_ROMAPI (1)
|
||||||
|
|
||||||
|
/* ADC_ETC module features */
|
||||||
|
|
||||||
|
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
|
||||||
|
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
|
||||||
|
/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1)
|
||||||
|
/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1)
|
||||||
|
|
||||||
|
/* AOI module features */
|
||||||
|
|
||||||
|
/* @brief Maximum value of input mux. */
|
||||||
|
#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
|
||||||
|
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
|
||||||
|
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
|
||||||
|
|
||||||
|
/* ASRC module features */
|
||||||
|
|
||||||
|
/* @brief Register name is ASRPM or ASRPMn */
|
||||||
|
#define FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASRPM (1)
|
||||||
|
|
||||||
|
/* FLEXCAN module features */
|
||||||
|
|
||||||
|
/* @brief Message buffer size */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
|
||||||
|
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
|
||||||
|
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
|
||||||
|
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
|
||||||
|
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
|
||||||
|
/* @brief Instance has extended bit timing register (register CBT). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
|
||||||
|
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
|
||||||
|
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
|
||||||
|
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0)
|
||||||
|
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0)
|
||||||
|
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
|
||||||
|
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
|
||||||
|
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
|
||||||
|
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
|
||||||
|
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
|
||||||
|
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
|
||||||
|
/* @brief Has memory error control (register MECR). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1)
|
||||||
|
/* @brief Init memory base 1 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80)
|
||||||
|
/* @brief Init memory size 1 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60)
|
||||||
|
/* @brief Init memory base 2 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xF28)
|
||||||
|
/* @brief Init memory size 2 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0xD8)
|
||||||
|
/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0)
|
||||||
|
/* @brief Has Pretended Networking mode support. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0)
|
||||||
|
|
||||||
|
/* CCM module features */
|
||||||
|
|
||||||
|
/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
|
||||||
|
#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0)
|
||||||
|
|
||||||
|
/* CDOG module features */
|
||||||
|
|
||||||
|
/* @brief SOC has no reset driver. */
|
||||||
|
#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
|
||||||
|
|
||||||
|
/* IGPIO module features */
|
||||||
|
|
||||||
|
/* @brief Has data register set DR_SET. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
|
||||||
|
/* @brief Has data register clear DR_CLEAR. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
|
||||||
|
/* @brief Has data register toggle DR_TOGGLE. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
|
||||||
|
|
||||||
|
/* ACMP module features */
|
||||||
|
|
||||||
|
/* @brief Has CMP_C3. */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C3_REG (1)
|
||||||
|
/* @brief Has C0 LINKEN Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1)
|
||||||
|
/* @brief Has C0 OFFSET Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0)
|
||||||
|
/* @brief Has C1 INPSEL Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0)
|
||||||
|
/* @brief Has C1 INNSEL Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
|
||||||
|
/* @brief Has C1 DACOE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0)
|
||||||
|
/* @brief Has C1 DMODE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
|
||||||
|
/* @brief Has C2 RRE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
|
||||||
|
|
||||||
|
/* CSI module features */
|
||||||
|
|
||||||
|
/* @brief If CSI registers don't have prefix. */
|
||||||
|
#define FSL_FEATURE_CSI_NO_REG_PREFIX (1)
|
||||||
|
|
||||||
|
/* DAC12 module features */
|
||||||
|
|
||||||
|
/* @brief Has no ITRM register. */
|
||||||
|
#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
|
||||||
|
|
||||||
|
/* DCDC module features */
|
||||||
|
|
||||||
|
/* @brief Has CTRL register (register CTRL0/1). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_CTRL_REG (1)
|
||||||
|
/* @brief DCDC VDD output count. */
|
||||||
|
#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (2)
|
||||||
|
/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (1)
|
||||||
|
/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (1)
|
||||||
|
/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (1)
|
||||||
|
/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (1)
|
||||||
|
/* @brief Has register bit field REG3[REG_FBK_SEL]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (1)
|
||||||
|
|
||||||
|
/* EDMA module features */
|
||||||
|
|
||||||
|
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
|
||||||
|
/* @brief Total number of DMA channels on all modules. */
|
||||||
|
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
||||||
|
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
||||||
|
/* @brief Has DMA_Error interrupt vector. */
|
||||||
|
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
||||||
|
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
||||||
|
/* @brief Channel IRQ entry shared offset. */
|
||||||
|
#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
|
||||||
|
/* @brief If 8 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
|
||||||
|
/* @brief If 16 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
|
||||||
|
/* @brief If 32 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
|
||||||
|
|
||||||
|
/* DMAMUX module features */
|
||||||
|
|
||||||
|
/* @brief Number of DMA channels (related to number of register CHCFGn). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
|
||||||
|
/* @brief Total number of DMA channels on all modules. */
|
||||||
|
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (64)
|
||||||
|
/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
|
||||||
|
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
|
||||||
|
/* @brief Register CHCFGn width. */
|
||||||
|
#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
|
||||||
|
|
||||||
|
/* DSI_HOST module features */
|
||||||
|
|
||||||
|
/* @brief Has separate submodules */
|
||||||
|
#define FSL_FEATURE_MIPI_DSI_HAS_SEPARATE_SUBMODULE (1)
|
||||||
|
|
||||||
|
/* ENC module features */
|
||||||
|
|
||||||
|
/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0)
|
||||||
|
/* @brief Has register CTRL3. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_CTRL3 (1)
|
||||||
|
/* @brief Has register LASTEDGE or LASTEDGEH. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_LASTEDGE (1)
|
||||||
|
/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_POSDPER (1)
|
||||||
|
|
||||||
|
/* ENET module features */
|
||||||
|
|
||||||
|
/* @brief Support Interrupt Coalesce */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
||||||
|
/* @brief Queue Size. */
|
||||||
|
#define FSL_FEATURE_ENET_QUEUE (3)
|
||||||
|
/* @brief Has AVB Support. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_AVB (1)
|
||||||
|
/* @brief Has Timer Pulse Width control. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
||||||
|
/* @brief Has Extend MDIO Support. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
||||||
|
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1)
|
||||||
|
/* @brief Support Interrupt Coalesce for each instance */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1)
|
||||||
|
/* @brief Queue Size for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) \
|
||||||
|
(((x) == ENET) ? (1) : \
|
||||||
|
(((x) == ENET_1G) ? (3) : (-1)))
|
||||||
|
/* @brief Has AVB Support for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) \
|
||||||
|
(((x) == ENET) ? (0) : \
|
||||||
|
(((x) == ENET_1G) ? (1) : (-1)))
|
||||||
|
/* @brief Has Timer Pulse Width control for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) \
|
||||||
|
(((x) == ENET) ? (1) : \
|
||||||
|
(((x) == ENET_1G) ? (0) : (-1)))
|
||||||
|
/* @brief Has Extend MDIO Support for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
|
||||||
|
/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1)
|
||||||
|
/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
|
||||||
|
/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1)
|
||||||
|
/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
|
||||||
|
/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
|
||||||
|
#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
|
||||||
|
|
||||||
|
/* ENET_QOS module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* EWM module features */
|
||||||
|
|
||||||
|
/* @brief Has clock select (register CLKCTRL). */
|
||||||
|
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
|
||||||
|
/* @brief Has clock prescaler (register CLKPRESCALER). */
|
||||||
|
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
|
||||||
|
|
||||||
|
/* FLEXIO module features */
|
||||||
|
|
||||||
|
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
|
||||||
|
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
|
||||||
|
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
|
||||||
|
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
|
||||||
|
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
|
||||||
|
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
|
||||||
|
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
|
||||||
|
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
|
||||||
|
/* @brief Reset value of the FLEXIO_VERID register */
|
||||||
|
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2000001)
|
||||||
|
/* @brief Reset value of the FLEXIO_PARAM register */
|
||||||
|
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808)
|
||||||
|
/* @brief Flexio DMA request base channel */
|
||||||
|
#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
|
||||||
|
|
||||||
|
/* FLEXRAM module features */
|
||||||
|
|
||||||
|
/* @brief Bank size */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
|
||||||
|
/* @brief Total Bank numbers */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
|
||||||
|
/* @brief Has FLEXRAM_MAGIC_ADDR. */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
|
||||||
|
/* @brief If FLEXRAM has ECC function. */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_HAS_ECC (1)
|
||||||
|
|
||||||
|
/* FLEXSPI module features */
|
||||||
|
|
||||||
|
/* @brief FlexSPI AHB buffer count */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
|
||||||
|
/* @brief FlexSPI has no data learn. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
|
||||||
|
/* @brief There is AHBBUSERROREN bit in INTEN register. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1)
|
||||||
|
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
|
||||||
|
|
||||||
|
/* GPC_CPU_CTRL module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* KEY_MANAGER module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* PUF module features */
|
||||||
|
|
||||||
|
/* @brief PUF need to setup SRAM manually */
|
||||||
|
#define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1)
|
||||||
|
/* @brief PUF has SHIFT_STATUS register. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0)
|
||||||
|
/* @brief PUF has IDXBLK_SHIFT register. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (1)
|
||||||
|
/* @brief SOC has no reset driver. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_NO_RESET (1)
|
||||||
|
|
||||||
|
/* LCDIF module features */
|
||||||
|
|
||||||
|
/* @brief LCDIF does not support alpha support. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
||||||
|
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
||||||
|
/* @brief LCDIF supports LUT. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
||||||
|
|
||||||
|
/* LCDIFV2 module features */
|
||||||
|
|
||||||
|
/* @brief Clut RAM offset, see datail in RM */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_CLUT_RAM_OFFSET (0x2000)
|
||||||
|
/* @brief Init doamin count, register INIT[n]_ENABLE. */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_INT_DOMAIN_COUNT (2)
|
||||||
|
/* @brief Layer count */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_LAYER_COUNT (8)
|
||||||
|
/* @brief CSC count in layer, register CSC_COEF[n]. */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_LAYER_CSC_COUNT (2)
|
||||||
|
|
||||||
|
/* LMEM module features */
|
||||||
|
|
||||||
|
/* @brief Has process identifier support. */
|
||||||
|
#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1)
|
||||||
|
/* @brief Has L1 cache. */
|
||||||
|
#define FSL_FEATURE_HAS_L1CACHE (1)
|
||||||
|
/* @brief L1 ICACHE line size in byte. */
|
||||||
|
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
|
||||||
|
/* @brief L1 DCACHE line size in byte. */
|
||||||
|
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
|
||||||
|
|
||||||
|
/* LPADC module features */
|
||||||
|
|
||||||
|
/* @brief FIFO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_LPADC_FIFO_COUNT (1)
|
||||||
|
/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
|
||||||
|
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1)
|
||||||
|
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1)
|
||||||
|
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
|
||||||
|
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
|
||||||
|
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0)
|
||||||
|
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
|
||||||
|
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
|
||||||
|
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
|
||||||
|
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
|
||||||
|
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
|
||||||
|
/* @brief Has calibration (bitfield CFG[CALOFS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
|
||||||
|
/* @brief Has offset trim (register OFSTRIM). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
|
||||||
|
|
||||||
|
/* LPI2C module features */
|
||||||
|
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||||
|
|
||||||
|
/* LPSPI module features */
|
||||||
|
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||||
|
/* @brief Has CCR1 (related to existence of registers CCR1). */
|
||||||
|
#define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
|
||||||
|
|
||||||
|
/* LPUART module features */
|
||||||
|
|
||||||
|
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||||
|
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||||
|
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||||
|
/* @brief Has 32-bit register MODIR */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||||
|
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||||
|
/* @brief Infrared (modulation) is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||||
|
/* @brief 2 bits long stop bit is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||||
|
/* @brief If 10-bit mode is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||||
|
/* @brief If 7-bit mode is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||||
|
/* @brief Baud rate fine adjustment is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||||
|
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||||
|
/* @brief Baud rate oversampling is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||||
|
/* @brief Baud rate oversampling is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||||
|
/* @brief Peripheral type. */
|
||||||
|
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
|
||||||
|
/* @brief Supports two match addresses to filter incoming frames. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||||
|
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||||
|
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||||
|
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||||
|
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||||
|
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||||
|
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||||
|
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||||
|
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||||
|
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||||
|
/* @brief Has separate RX and TX interrupts. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||||
|
/* @brief Has LPAURT_PARAM. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||||
|
/* @brief Has LPUART_VERID. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||||
|
/* @brief Has LPUART_GLOBAL. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||||
|
/* @brief Has LPUART_PINCFG. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||||
|
|
||||||
|
/* MEMORY module features */
|
||||||
|
|
||||||
|
/* @brief Memory map has offset between subsystems. */
|
||||||
|
#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1)
|
||||||
|
|
||||||
|
/* CSI2RX module features */
|
||||||
|
|
||||||
|
/* @brief If MIPI_CSI2RX registers don't have prefix. */
|
||||||
|
#define FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX (1)
|
||||||
|
|
||||||
|
/* MU module features */
|
||||||
|
|
||||||
|
/* @brief MU side for current core */
|
||||||
|
#define FSL_FEATURE_MU_SIDE_B (1)
|
||||||
|
/* @brief MU Has register CCR */
|
||||||
|
#define FSL_FEATURE_MU_HAS_CCR (0)
|
||||||
|
/* @brief MU Has register SR[RS], BSR[ARS] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_RS (1)
|
||||||
|
/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_INT (0)
|
||||||
|
/* @brief MU Has register SR[MURIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
|
||||||
|
/* @brief MU Has register SR[HRIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_HRIP (0)
|
||||||
|
/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_CLKE (1)
|
||||||
|
/* @brief MU does not support NMI, CR[NMI]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_NMI (1)
|
||||||
|
/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_RSTH (1)
|
||||||
|
/* @brief MU does not supports MU reset, CR[MUR]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_MUR (1)
|
||||||
|
/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_HR (1)
|
||||||
|
/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_HRM (0)
|
||||||
|
/* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_PM (1)
|
||||||
|
/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0)
|
||||||
|
/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0)
|
||||||
|
|
||||||
|
/* interrupt module features */
|
||||||
|
|
||||||
|
/* @brief Lowest interrupt request number. */
|
||||||
|
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
|
||||||
|
/* @brief Highest interrupt request number. */
|
||||||
|
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
|
||||||
|
|
||||||
|
/* OCOTP module features */
|
||||||
|
|
||||||
|
/* @brief Has timing control, (register TIMING). */
|
||||||
|
#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (0)
|
||||||
|
/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
|
||||||
|
#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (1)
|
||||||
|
|
||||||
|
/* PDM module features */
|
||||||
|
|
||||||
|
/* @brief PDM FIFO offset */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_OFFSET (4)
|
||||||
|
/* @brief PDM Channel Number */
|
||||||
|
#define FSL_FEATURE_PDM_CHANNEL_NUM (8)
|
||||||
|
/* @brief PDM FIFO WIDTH Size */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_WIDTH (4)
|
||||||
|
/* @brief PDM FIFO DEPTH Size */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_DEPTH (8)
|
||||||
|
/* @brief PDM has RANGE_CTRL register */
|
||||||
|
#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
|
||||||
|
/* @brief PDM Has Low Frequency */
|
||||||
|
#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1)
|
||||||
|
|
||||||
|
/* PIT module features */
|
||||||
|
|
||||||
|
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||||
|
#define FSL_FEATURE_PIT_TIMER_COUNT (4)
|
||||||
|
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
|
||||||
|
/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
|
||||||
|
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||||
|
/* @brief Has timer enable control. */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_MDIS (1)
|
||||||
|
|
||||||
|
/* PWM module features */
|
||||||
|
|
||||||
|
/* @brief If (e)FlexPWM has module A channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
|
||||||
|
/* @brief If (e)FlexPWM has module B channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
|
||||||
|
/* @brief If (e)FlexPWM has module X channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
|
||||||
|
/* @brief If (e)FlexPWM has fractional feature. */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
|
||||||
|
/* @brief If (e)FlexPWM has mux trigger source select bit field. */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
|
||||||
|
/* @brief Number of submodules in each (e)FlexPWM module. */
|
||||||
|
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
|
||||||
|
/* @brief Number of fault channel in each (e)FlexPWM module. */
|
||||||
|
#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
|
||||||
|
|
||||||
|
/* PXP module features */
|
||||||
|
|
||||||
|
/* @brief PXP module has dither engine. */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_DITHER (0)
|
||||||
|
/* @brief PXP module supports repeat run */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
|
||||||
|
/* @brief PXP doesn't have CSC */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
|
||||||
|
/* @brief PXP doesn't have LUT */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
|
||||||
|
|
||||||
|
/* RTWDOG module features */
|
||||||
|
|
||||||
|
/* @brief Watchdog is available. */
|
||||||
|
#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
|
||||||
|
/* @brief RTWDOG_CNT can be 32-bit written. */
|
||||||
|
#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
|
||||||
|
|
||||||
|
/* SAI module features */
|
||||||
|
|
||||||
|
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||||
|
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
|
||||||
|
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||||
|
#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
|
||||||
|
(((x) == SAI1) ? (4) : \
|
||||||
|
(((x) == SAI2) ? (1) : \
|
||||||
|
(((x) == SAI3) ? (1) : \
|
||||||
|
(((x) == SAI4) ? (1) : (-1)))))
|
||||||
|
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||||
|
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||||
|
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||||
|
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||||
|
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||||
|
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||||
|
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||||
|
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||||
|
/* @brief Interrupt source number */
|
||||||
|
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
|
||||||
|
/* @brief Has register of MCR. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||||
|
/* @brief Has bit field MICS of the MCR register. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
|
||||||
|
/* @brief Has register of MDR */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||||
|
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1)
|
||||||
|
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
|
||||||
|
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
|
||||||
|
|
||||||
|
/* SEMC module features */
|
||||||
|
|
||||||
|
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (0)
|
||||||
|
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (0)
|
||||||
|
/* @brief Has LC time in NOR controller (register bit field NORCR2[LC]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_LC_TIME (1)
|
||||||
|
/* @brief Has RD time in NOR controller (register bit field NORCR2[RD]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_RD_TIME (1)
|
||||||
|
/* @brief Has WDH time in SRAM controller (register bit field SRAMCR2[WDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME (1)
|
||||||
|
/* @brief Has WDS time in SRAM controller (register bit field SRAMCR2[WDS]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME (1)
|
||||||
|
/* @brief Has LC time in SRAM controller (register bit field SRAMCR2[LC]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME (1)
|
||||||
|
/* @brief Has RD time in SRAM controller (register bit field SRAMCR2[RD]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME (1)
|
||||||
|
/* @brief SRAM count SEMC can support (register BRx). */
|
||||||
|
#define FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT (4)
|
||||||
|
/* @brief If SEMC support delay chain control (register DCCR). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1)
|
||||||
|
/* @brief Has read hold time feature (register bit field SRAMCR6[RDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1)
|
||||||
|
/* @brief Width of SDRAMCR0[PS] bitfields. */
|
||||||
|
#define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2)
|
||||||
|
/* @brief If SEMC has errata 050577. */
|
||||||
|
#define FSL_FEATURE_SEMC_ERRATA_050577 (0)
|
||||||
|
/* @brief If sdram support column address 8 bit (register bit field SRAMCR0[CLO8]). */
|
||||||
|
#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1)
|
||||||
|
/* @brief If SEMC has register DBICR2 (register DBICR2). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_DBICR2 (1)
|
||||||
|
|
||||||
|
/* SNVS module features */
|
||||||
|
|
||||||
|
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
|
||||||
|
/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
|
||||||
|
#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
|
||||||
|
/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (1)
|
||||||
|
/* @brief Number of TAMPER. */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10)
|
||||||
|
|
||||||
|
/* SSARC_HP module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* SSARC_LP module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* USBPHY module features */
|
||||||
|
|
||||||
|
/* @brief USBPHY contain DCD analog module */
|
||||||
|
#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
|
||||||
|
/* @brief USBPHY has register TRIM_OVERRIDE_EN */
|
||||||
|
#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1)
|
||||||
|
/* @brief USBPHY is 28FDSOI */
|
||||||
|
#define FSL_FEATURE_USBPHY_28FDSOI (1)
|
||||||
|
|
||||||
|
/* USBHS module features */
|
||||||
|
|
||||||
|
/* @brief EHCI module instance count */
|
||||||
|
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
|
||||||
|
/* @brief Number of endpoints supported */
|
||||||
|
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||||
|
|
||||||
|
/* USDHC module features */
|
||||||
|
|
||||||
|
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||||
|
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1)
|
||||||
|
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||||
|
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||||
|
/* @brief USDHC has reset control */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_RESET (0)
|
||||||
|
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1)
|
||||||
|
/* @brief If USDHC instance support 8 bit width */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \
|
||||||
|
(((x) == USDHC1) ? (0) : \
|
||||||
|
(((x) == USDHC2) ? (1) : (-1)))
|
||||||
|
/* @brief If USDHC instance support HS400 mode */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (1)
|
||||||
|
/* @brief If USDHC instance support 1v8 signal */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
|
||||||
|
/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
|
||||||
|
#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
|
||||||
|
|
||||||
|
/* XBARA module features */
|
||||||
|
|
||||||
|
/* @brief Number of interrupt requests. */
|
||||||
|
#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
|
||||||
|
|
||||||
|
/* XRDC2 module features */
|
||||||
|
|
||||||
|
/* @brief XRDC2 supports how many domains */
|
||||||
|
#define FSL_FEATURE_XRDC2_DOMAIN_COUNT (16)
|
||||||
|
|
||||||
|
#endif /* _MIMXRT1176_cm4_FEATURES_H_ */
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,870 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210910
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Chip specific module features.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update feature files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file MIMXRT1176_cm7_features.h
|
||||||
|
* @brief support imxrt1176-sbc cm7 features
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: MIMXRT1176_cm7_features.h
|
||||||
|
Description: support imxrt1176-sbc cm7 features
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
#ifndef _MIMXRT1176_cm7_FEATURES_H_
|
||||||
|
#define _MIMXRT1176_cm7_FEATURES_H_
|
||||||
|
|
||||||
|
/* SOC module features */
|
||||||
|
|
||||||
|
/* @brief ACMP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ACMP_COUNT (4)
|
||||||
|
/* @brief AOI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_AOI_COUNT (2)
|
||||||
|
/* @brief ASRC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ASRC_COUNT (1)
|
||||||
|
/* @brief CAAM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CAAM_COUNT (1)
|
||||||
|
/* @brief CCM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CCM_COUNT (1)
|
||||||
|
/* @brief CSI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CSI_COUNT (1)
|
||||||
|
/* @brief CDOG availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_CDOG_COUNT (1)
|
||||||
|
/* @brief DAC12 availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DAC12_COUNT (1)
|
||||||
|
/* @brief DCDC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
|
||||||
|
/* @brief DMAMUX availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
|
||||||
|
/* @brief EDMA availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
|
||||||
|
/* @brief EMVSIM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
|
||||||
|
/* @brief ENC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENC_COUNT (4)
|
||||||
|
/* @brief ENET availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENET_COUNT (2)
|
||||||
|
/* @brief ENET_QOS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_ENET_QOS_COUNT (1)
|
||||||
|
/* @brief EWM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_EWM_COUNT (1)
|
||||||
|
/* @brief FLEXCAN availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (3)
|
||||||
|
/* @brief FLEXIO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
|
||||||
|
/* @brief FLEXRAM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
|
||||||
|
/* @brief FLEXSPI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (2)
|
||||||
|
/* @brief GPT availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_GPT_COUNT (6)
|
||||||
|
/* @brief I2S availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_I2S_COUNT (4)
|
||||||
|
/* @brief IEE availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IEE_COUNT (1)
|
||||||
|
/* @brief IGPIO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IGPIO_COUNT (15)
|
||||||
|
/* @brief IOMUXC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
|
||||||
|
/* @brief IOMUXC_LPSR availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (1)
|
||||||
|
/* @brief KPP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_KPP_COUNT (1)
|
||||||
|
/* @brief LCDIF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
|
||||||
|
/* @brief LPADC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPADC_COUNT (2)
|
||||||
|
/* @brief LPI2C availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPI2C_COUNT (6)
|
||||||
|
/* @brief LPSPI availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPSPI_COUNT (6)
|
||||||
|
/* @brief LPUART availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_LPUART_COUNT (12)
|
||||||
|
/* @brief MCM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_MCM_COUNT (1)
|
||||||
|
/* @brief MU availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_MU_COUNT (1)
|
||||||
|
/* @brief OCOTP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
|
||||||
|
/* @brief OTFAD availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_OTFAD_COUNT (2)
|
||||||
|
/* @brief PDM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PDM_COUNT (1)
|
||||||
|
/* @brief PIT availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PIT_COUNT (2)
|
||||||
|
/* @brief PWM availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PWM_COUNT (4)
|
||||||
|
/* @brief PXP availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PXP_COUNT (1)
|
||||||
|
/* @brief PUF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_PUF_COUNT (1)
|
||||||
|
/* @brief RDC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_RDC_COUNT (1)
|
||||||
|
/* @brief RDC_SEMAPHORE availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2)
|
||||||
|
/* @brief SEMA4 availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SEMA4_COUNT (1)
|
||||||
|
/* @brief SEMC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
|
||||||
|
/* @brief SNVS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
|
||||||
|
/* @brief SPDIF availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
|
||||||
|
/* @brief SRC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_SRC_COUNT (1)
|
||||||
|
/* @brief TMR availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_TMR_COUNT (4)
|
||||||
|
/* @brief USBHS availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
|
||||||
|
/* @brief USBHSDCD availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2)
|
||||||
|
/* @brief USBNC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
|
||||||
|
/* @brief USBPHY availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
|
||||||
|
/* @brief USDHC availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
|
||||||
|
/* @brief WDOG availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
|
||||||
|
/* @brief XBARA availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
|
||||||
|
/* @brief XBARB availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
|
||||||
|
/* @brief ROM API Availability */
|
||||||
|
#define FSL_FEATURE_BOOT_ROM_HAS_ROMAPI (1)
|
||||||
|
|
||||||
|
/* ADC_ETC module features */
|
||||||
|
|
||||||
|
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
|
||||||
|
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
|
||||||
|
/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1)
|
||||||
|
/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
|
||||||
|
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1)
|
||||||
|
|
||||||
|
/* AOI module features */
|
||||||
|
|
||||||
|
/* @brief Maximum value of input mux. */
|
||||||
|
#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
|
||||||
|
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
|
||||||
|
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
|
||||||
|
|
||||||
|
/* ASRC module features */
|
||||||
|
|
||||||
|
/* @brief Register name is ASRPM or ASRPMn */
|
||||||
|
#define FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASRPM (1)
|
||||||
|
|
||||||
|
/* FLEXCAN module features */
|
||||||
|
|
||||||
|
/* @brief Message buffer size */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
|
||||||
|
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
|
||||||
|
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
|
||||||
|
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
|
||||||
|
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
|
||||||
|
/* @brief Instance has extended bit timing register (register CBT). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
|
||||||
|
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
|
||||||
|
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
|
||||||
|
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0)
|
||||||
|
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0)
|
||||||
|
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
|
||||||
|
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
|
||||||
|
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
|
||||||
|
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
|
||||||
|
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
|
||||||
|
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
|
||||||
|
/* @brief Has memory error control (register MECR). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1)
|
||||||
|
/* @brief Init memory base 1 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80)
|
||||||
|
/* @brief Init memory size 1 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60)
|
||||||
|
/* @brief Init memory base 2 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xF28)
|
||||||
|
/* @brief Init memory size 2 */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0xD8)
|
||||||
|
/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0)
|
||||||
|
/* @brief Has Pretended Networking mode support. */
|
||||||
|
#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0)
|
||||||
|
|
||||||
|
/* CCM module features */
|
||||||
|
|
||||||
|
/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
|
||||||
|
#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0)
|
||||||
|
|
||||||
|
/* CDOG module features */
|
||||||
|
|
||||||
|
/* @brief SOC has no reset driver. */
|
||||||
|
#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
|
||||||
|
|
||||||
|
/* IGPIO module features */
|
||||||
|
|
||||||
|
/* @brief Has data register set DR_SET. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
|
||||||
|
/* @brief Has data register clear DR_CLEAR. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
|
||||||
|
/* @brief Has data register toggle DR_TOGGLE. */
|
||||||
|
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
|
||||||
|
|
||||||
|
/* ACMP module features */
|
||||||
|
|
||||||
|
/* @brief Has CMP_C3. */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C3_REG (1)
|
||||||
|
/* @brief Has C0 LINKEN Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1)
|
||||||
|
/* @brief Has C0 OFFSET Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0)
|
||||||
|
/* @brief Has C1 INPSEL Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0)
|
||||||
|
/* @brief Has C1 INNSEL Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
|
||||||
|
/* @brief Has C1 DACOE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0)
|
||||||
|
/* @brief Has C1 DMODE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
|
||||||
|
/* @brief Has C2 RRE Bit */
|
||||||
|
#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
|
||||||
|
|
||||||
|
/* CSI module features */
|
||||||
|
|
||||||
|
/* @brief If CSI registers don't have prefix. */
|
||||||
|
#define FSL_FEATURE_CSI_NO_REG_PREFIX (1)
|
||||||
|
|
||||||
|
/* DAC12 module features */
|
||||||
|
|
||||||
|
/* @brief Has no ITRM register. */
|
||||||
|
#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
|
||||||
|
|
||||||
|
/* DCDC module features */
|
||||||
|
|
||||||
|
/* @brief Has CTRL register (register CTRL0/1). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_CTRL_REG (1)
|
||||||
|
/* @brief DCDC VDD output count. */
|
||||||
|
#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (2)
|
||||||
|
/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (1)
|
||||||
|
/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (1)
|
||||||
|
/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (1)
|
||||||
|
/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (1)
|
||||||
|
/* @brief Has register bit field REG3[REG_FBK_SEL]). */
|
||||||
|
#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (1)
|
||||||
|
|
||||||
|
/* EDMA module features */
|
||||||
|
|
||||||
|
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
|
||||||
|
/* @brief Total number of DMA channels on all modules. */
|
||||||
|
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
||||||
|
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
||||||
|
/* @brief Has DMA_Error interrupt vector. */
|
||||||
|
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
||||||
|
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
||||||
|
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
||||||
|
/* @brief Channel IRQ entry shared offset. */
|
||||||
|
#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
|
||||||
|
/* @brief If 8 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
|
||||||
|
/* @brief If 16 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
|
||||||
|
/* @brief If 32 bytes transfer supported. */
|
||||||
|
#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
|
||||||
|
|
||||||
|
/* DMAMUX module features */
|
||||||
|
|
||||||
|
/* @brief Number of DMA channels (related to number of register CHCFGn). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
|
||||||
|
/* @brief Total number of DMA channels on all modules. */
|
||||||
|
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (64)
|
||||||
|
/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
|
||||||
|
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
|
||||||
|
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
|
||||||
|
/* @brief Register CHCFGn width. */
|
||||||
|
#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
|
||||||
|
|
||||||
|
/* DSI_HOST module features */
|
||||||
|
|
||||||
|
/* @brief Has separate submodules */
|
||||||
|
#define FSL_FEATURE_MIPI_DSI_HAS_SEPARATE_SUBMODULE (1)
|
||||||
|
|
||||||
|
/* ENC module features */
|
||||||
|
|
||||||
|
/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0)
|
||||||
|
/* @brief Has register CTRL3. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_CTRL3 (1)
|
||||||
|
/* @brief Has register LASTEDGE or LASTEDGEH. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_LASTEDGE (1)
|
||||||
|
/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
|
||||||
|
#define FSL_FEATURE_ENC_HAS_POSDPER (1)
|
||||||
|
|
||||||
|
/* ENET module features */
|
||||||
|
|
||||||
|
/* @brief Support Interrupt Coalesce */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
||||||
|
/* @brief Queue Size. */
|
||||||
|
#define FSL_FEATURE_ENET_QUEUE (3)
|
||||||
|
/* @brief Has AVB Support. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_AVB (1)
|
||||||
|
/* @brief Has Timer Pulse Width control. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
||||||
|
/* @brief Has Extend MDIO Support. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
||||||
|
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1)
|
||||||
|
/* @brief Support Interrupt Coalesce for each instance */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1)
|
||||||
|
/* @brief Queue Size for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) \
|
||||||
|
(((x) == ENET) ? (1) : \
|
||||||
|
(((x) == ENET_1G) ? (3) : (-1)))
|
||||||
|
/* @brief Has AVB Support for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) \
|
||||||
|
(((x) == ENET) ? (0) : \
|
||||||
|
(((x) == ENET_1G) ? (1) : (-1)))
|
||||||
|
/* @brief Has Timer Pulse Width control for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) \
|
||||||
|
(((x) == ENET) ? (1) : \
|
||||||
|
(((x) == ENET_1G) ? (0) : (-1)))
|
||||||
|
/* @brief Has Extend MDIO Support for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
|
||||||
|
/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
|
||||||
|
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1)
|
||||||
|
/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
|
||||||
|
/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1)
|
||||||
|
/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */
|
||||||
|
#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
|
||||||
|
/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
|
||||||
|
#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
|
||||||
|
|
||||||
|
/* ENET_QOS module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* EWM module features */
|
||||||
|
|
||||||
|
/* @brief Has clock select (register CLKCTRL). */
|
||||||
|
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
|
||||||
|
/* @brief Has clock prescaler (register CLKPRESCALER). */
|
||||||
|
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
|
||||||
|
|
||||||
|
/* FLEXIO module features */
|
||||||
|
|
||||||
|
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
|
||||||
|
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
|
||||||
|
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
|
||||||
|
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
|
||||||
|
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
|
||||||
|
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
|
||||||
|
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
|
||||||
|
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
|
||||||
|
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
|
||||||
|
/* @brief Reset value of the FLEXIO_VERID register */
|
||||||
|
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2000001)
|
||||||
|
/* @brief Reset value of the FLEXIO_PARAM register */
|
||||||
|
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808)
|
||||||
|
/* @brief Flexio DMA request base channel */
|
||||||
|
#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
|
||||||
|
|
||||||
|
/* FLEXRAM module features */
|
||||||
|
|
||||||
|
/* @brief Bank size */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
|
||||||
|
/* @brief Total Bank numbers */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
|
||||||
|
/* @brief Has FLEXRAM_MAGIC_ADDR. */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
|
||||||
|
/* @brief If FLEXRAM has ECC function. */
|
||||||
|
#define FSL_FEATURE_FLEXRAM_HAS_ECC (1)
|
||||||
|
|
||||||
|
/* FLEXSPI module features */
|
||||||
|
|
||||||
|
/* @brief FlexSPI AHB buffer count */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
|
||||||
|
/* @brief FlexSPI has no data learn. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
|
||||||
|
/* @brief There is AHBBUSERROREN bit in INTEN register. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1)
|
||||||
|
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
|
||||||
|
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
|
||||||
|
|
||||||
|
/* GPC_CPU_CTRL module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* KEY_MANAGER module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* PUF module features */
|
||||||
|
|
||||||
|
/* @brief PUF need to setup SRAM manually */
|
||||||
|
#define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1)
|
||||||
|
/* @brief PUF has SHIFT_STATUS register. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0)
|
||||||
|
/* @brief PUF has IDXBLK_SHIFT register. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (1)
|
||||||
|
/* @brief SOC has no reset driver. */
|
||||||
|
#define FSL_FEATURE_PUF_HAS_NO_RESET (1)
|
||||||
|
|
||||||
|
/* LCDIF module features */
|
||||||
|
|
||||||
|
/* @brief LCDIF does not support alpha support. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
||||||
|
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
||||||
|
/* @brief LCDIF supports LUT. */
|
||||||
|
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
||||||
|
|
||||||
|
/* LCDIFV2 module features */
|
||||||
|
|
||||||
|
/* @brief Clut RAM offset, see datail in RM */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_CLUT_RAM_OFFSET (0x2000)
|
||||||
|
/* @brief Init doamin count, register INIT[n]_ENABLE. */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_INT_DOMAIN_COUNT (2)
|
||||||
|
/* @brief Layer count */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_LAYER_COUNT (8)
|
||||||
|
/* @brief CSC count in layer, register CSC_COEF[n]. */
|
||||||
|
#define FSL_FEATURE_LCDIFV2_LAYER_CSC_COUNT (2)
|
||||||
|
|
||||||
|
/* LPADC module features */
|
||||||
|
|
||||||
|
/* @brief FIFO availability on the SoC. */
|
||||||
|
#define FSL_FEATURE_LPADC_FIFO_COUNT (1)
|
||||||
|
/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
|
||||||
|
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1)
|
||||||
|
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1)
|
||||||
|
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
|
||||||
|
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
|
||||||
|
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0)
|
||||||
|
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
|
||||||
|
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
|
||||||
|
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
|
||||||
|
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
|
||||||
|
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
|
||||||
|
/* @brief Has calibration (bitfield CFG[CALOFS]). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
|
||||||
|
/* @brief Has offset trim (register OFSTRIM). */
|
||||||
|
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
|
||||||
|
|
||||||
|
/* LPI2C module features */
|
||||||
|
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||||
|
|
||||||
|
/* LPSPI module features */
|
||||||
|
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||||
|
/* @brief Has CCR1 (related to existence of registers CCR1). */
|
||||||
|
#define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
|
||||||
|
|
||||||
|
/* LPUART module features */
|
||||||
|
|
||||||
|
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||||
|
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||||
|
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||||
|
/* @brief Has 32-bit register MODIR */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||||
|
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||||
|
/* @brief Infrared (modulation) is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||||
|
/* @brief 2 bits long stop bit is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||||
|
/* @brief If 10-bit mode is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||||
|
/* @brief If 7-bit mode is supported. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||||
|
/* @brief Baud rate fine adjustment is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||||
|
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||||
|
/* @brief Baud rate oversampling is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||||
|
/* @brief Baud rate oversampling is available. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||||
|
/* @brief Peripheral type. */
|
||||||
|
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||||
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||||
|
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
|
||||||
|
/* @brief Supports two match addresses to filter incoming frames. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||||
|
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||||
|
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||||
|
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||||
|
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||||
|
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||||
|
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||||
|
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||||
|
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||||
|
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||||
|
/* @brief Has separate DMA RX and TX requests. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||||
|
/* @brief Has separate RX and TX interrupts. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||||
|
/* @brief Has LPAURT_PARAM. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||||
|
/* @brief Has LPUART_VERID. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||||
|
/* @brief Has LPUART_GLOBAL. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||||
|
/* @brief Has LPUART_PINCFG. */
|
||||||
|
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||||
|
|
||||||
|
/* CSI2RX module features */
|
||||||
|
|
||||||
|
/* @brief If MIPI_CSI2RX registers don't have prefix. */
|
||||||
|
#define FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX (1)
|
||||||
|
|
||||||
|
/* MU module features */
|
||||||
|
|
||||||
|
/* @brief MU side for current core */
|
||||||
|
#define FSL_FEATURE_MU_SIDE_A (1)
|
||||||
|
/* @brief MU Has register CCR */
|
||||||
|
#define FSL_FEATURE_MU_HAS_CCR (0)
|
||||||
|
/* @brief MU Has register SR[RS], BSR[ARS] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_RS (1)
|
||||||
|
/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_INT (0)
|
||||||
|
/* @brief MU Has register SR[MURIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
|
||||||
|
/* @brief MU Has register SR[HRIP] */
|
||||||
|
#define FSL_FEATURE_MU_HAS_SR_HRIP (0)
|
||||||
|
/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_CLKE (1)
|
||||||
|
/* @brief MU does not support NMI, CR[NMI]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_NMI (1)
|
||||||
|
/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_RSTH (1)
|
||||||
|
/* @brief MU does not supports MU reset, CR[MUR]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_MUR (0)
|
||||||
|
/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_HR (1)
|
||||||
|
/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_HRM (0)
|
||||||
|
/* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */
|
||||||
|
#define FSL_FEATURE_MU_NO_PM (1)
|
||||||
|
/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0)
|
||||||
|
/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
|
||||||
|
#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0)
|
||||||
|
|
||||||
|
/* interrupt module features */
|
||||||
|
|
||||||
|
/* @brief Lowest interrupt request number. */
|
||||||
|
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
|
||||||
|
/* @brief Highest interrupt request number. */
|
||||||
|
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
|
||||||
|
|
||||||
|
/* OCOTP module features */
|
||||||
|
|
||||||
|
/* @brief Has timing control, (register TIMING). */
|
||||||
|
#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (0)
|
||||||
|
/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
|
||||||
|
#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (1)
|
||||||
|
|
||||||
|
/* PDM module features */
|
||||||
|
|
||||||
|
/* @brief PDM FIFO offset */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_OFFSET (4)
|
||||||
|
/* @brief PDM Channel Number */
|
||||||
|
#define FSL_FEATURE_PDM_CHANNEL_NUM (8)
|
||||||
|
/* @brief PDM FIFO WIDTH Size */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_WIDTH (4)
|
||||||
|
/* @brief PDM FIFO DEPTH Size */
|
||||||
|
#define FSL_FEATURE_PDM_FIFO_DEPTH (8)
|
||||||
|
/* @brief PDM has RANGE_CTRL register */
|
||||||
|
#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
|
||||||
|
/* @brief PDM Has Low Frequency */
|
||||||
|
#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1)
|
||||||
|
|
||||||
|
/* PIT module features */
|
||||||
|
|
||||||
|
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||||
|
#define FSL_FEATURE_PIT_TIMER_COUNT (4)
|
||||||
|
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
|
||||||
|
/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
|
||||||
|
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||||
|
/* @brief Has timer enable control. */
|
||||||
|
#define FSL_FEATURE_PIT_HAS_MDIS (1)
|
||||||
|
|
||||||
|
/* PWM module features */
|
||||||
|
|
||||||
|
/* @brief If (e)FlexPWM has module A channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
|
||||||
|
/* @brief If (e)FlexPWM has module B channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
|
||||||
|
/* @brief If (e)FlexPWM has module X channels (outputs). */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
|
||||||
|
/* @brief If (e)FlexPWM has fractional feature. */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
|
||||||
|
/* @brief If (e)FlexPWM has mux trigger source select bit field. */
|
||||||
|
#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
|
||||||
|
/* @brief Number of submodules in each (e)FlexPWM module. */
|
||||||
|
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
|
||||||
|
/* @brief Number of fault channel in each (e)FlexPWM module. */
|
||||||
|
#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
|
||||||
|
|
||||||
|
/* PXP module features */
|
||||||
|
|
||||||
|
/* @brief PXP module has dither engine. */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_DITHER (0)
|
||||||
|
/* @brief PXP module supports repeat run */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
|
||||||
|
/* @brief PXP doesn't have CSC */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
|
||||||
|
/* @brief PXP doesn't have LUT */
|
||||||
|
#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
|
||||||
|
|
||||||
|
/* RTWDOG module features */
|
||||||
|
|
||||||
|
/* @brief Watchdog is available. */
|
||||||
|
#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
|
||||||
|
/* @brief RTWDOG_CNT can be 32-bit written. */
|
||||||
|
#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
|
||||||
|
|
||||||
|
/* SAI module features */
|
||||||
|
|
||||||
|
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||||
|
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
|
||||||
|
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||||
|
#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
|
||||||
|
(((x) == SAI1) ? (4) : \
|
||||||
|
(((x) == SAI2) ? (1) : \
|
||||||
|
(((x) == SAI3) ? (1) : \
|
||||||
|
(((x) == SAI4) ? (1) : (-1)))))
|
||||||
|
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||||
|
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||||
|
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||||
|
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||||
|
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||||
|
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||||
|
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||||
|
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||||
|
/* @brief Interrupt source number */
|
||||||
|
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
|
||||||
|
/* @brief Has register of MCR. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||||
|
/* @brief Has bit field MICS of the MCR register. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
|
||||||
|
/* @brief Has register of MDR */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||||
|
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1)
|
||||||
|
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
|
||||||
|
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
|
||||||
|
#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
|
||||||
|
|
||||||
|
/* SEMC module features */
|
||||||
|
|
||||||
|
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (0)
|
||||||
|
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (0)
|
||||||
|
/* @brief Has LC time in NOR controller (register bit field NORCR2[LC]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_LC_TIME (1)
|
||||||
|
/* @brief Has RD time in NOR controller (register bit field NORCR2[RD]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_NOR_RD_TIME (1)
|
||||||
|
/* @brief Has WDH time in SRAM controller (register bit field SRAMCR2[WDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME (1)
|
||||||
|
/* @brief Has WDS time in SRAM controller (register bit field SRAMCR2[WDS]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME (1)
|
||||||
|
/* @brief Has LC time in SRAM controller (register bit field SRAMCR2[LC]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME (1)
|
||||||
|
/* @brief Has RD time in SRAM controller (register bit field SRAMCR2[RD]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME (1)
|
||||||
|
/* @brief SRAM count SEMC can support (register BRx). */
|
||||||
|
#define FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT (4)
|
||||||
|
/* @brief If SEMC support delay chain control (register DCCR). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1)
|
||||||
|
/* @brief Has read hold time feature (register bit field SRAMCR6[RDH]). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1)
|
||||||
|
/* @brief Width of SDRAMCR0[PS] bitfields. */
|
||||||
|
#define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2)
|
||||||
|
/* @brief If SEMC has errata 050577. */
|
||||||
|
#define FSL_FEATURE_SEMC_ERRATA_050577 (0)
|
||||||
|
/* @brief If sdram support column address 8 bit (register bit field SRAMCR0[CLO8]). */
|
||||||
|
#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1)
|
||||||
|
/* @brief If SEMC has register DBICR2 (register DBICR2). */
|
||||||
|
#define FSL_FEATURE_SEMC_HAS_DBICR2 (1)
|
||||||
|
|
||||||
|
/* SNVS module features */
|
||||||
|
|
||||||
|
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
|
||||||
|
/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
|
||||||
|
#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
|
||||||
|
/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (1)
|
||||||
|
/* @brief Number of TAMPER. */
|
||||||
|
#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10)
|
||||||
|
|
||||||
|
/* SSARC_HP module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* SSARC_LP module features */
|
||||||
|
|
||||||
|
/* No feature definitions */
|
||||||
|
|
||||||
|
/* SCB module features */
|
||||||
|
|
||||||
|
/* @brief L1 ICACHE line size in byte. */
|
||||||
|
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
|
||||||
|
/* @brief L1 DCACHE line size in byte. */
|
||||||
|
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
|
||||||
|
|
||||||
|
/* USBPHY module features */
|
||||||
|
|
||||||
|
/* @brief USBPHY contain DCD analog module */
|
||||||
|
#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
|
||||||
|
/* @brief USBPHY has register TRIM_OVERRIDE_EN */
|
||||||
|
#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1)
|
||||||
|
/* @brief USBPHY is 28FDSOI */
|
||||||
|
#define FSL_FEATURE_USBPHY_28FDSOI (1)
|
||||||
|
|
||||||
|
/* USBHS module features */
|
||||||
|
|
||||||
|
/* @brief EHCI module instance count */
|
||||||
|
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
|
||||||
|
/* @brief Number of endpoints supported */
|
||||||
|
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||||
|
|
||||||
|
/* USDHC module features */
|
||||||
|
|
||||||
|
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||||
|
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1)
|
||||||
|
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||||
|
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||||
|
/* @brief USDHC has reset control */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_RESET (0)
|
||||||
|
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
|
||||||
|
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1)
|
||||||
|
/* @brief If USDHC instance support 8 bit width */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \
|
||||||
|
(((x) == USDHC1) ? (0) : \
|
||||||
|
(((x) == USDHC2) ? (1) : (-1)))
|
||||||
|
/* @brief If USDHC instance support HS400 mode */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (1)
|
||||||
|
/* @brief If USDHC instance support 1v8 signal */
|
||||||
|
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
|
||||||
|
/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
|
||||||
|
#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
|
||||||
|
|
||||||
|
/* XBARA module features */
|
||||||
|
|
||||||
|
/* @brief Number of interrupt requests. */
|
||||||
|
#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
|
||||||
|
|
||||||
|
/* XRDC2 module features */
|
||||||
|
|
||||||
|
/* @brief XRDC2 supports how many domains */
|
||||||
|
#define FSL_FEATURE_XRDC2_DOMAIN_COUNT (16)
|
||||||
|
|
||||||
|
#endif /* _MIMXRT1176_cm7_FEATURES_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 AIIT XUOS Lab
|
||||||
|
* XiUOS is licensed under Mulan PSL v2.
|
||||||
|
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||||
|
* You may obtain a copy of Mulan PSL v2 at:
|
||||||
|
* http://license.coscl.org.cn/MulanPSL2
|
||||||
|
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||||
|
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||||
|
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||||
|
* See the Mulan PSL v2 for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file connect_gpio.h
|
||||||
|
* @brief define ok1052-c board gpio function and struct
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-03-01
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONNECT_GPIO_H_
|
||||||
|
#define __CONNECT_GPIO_H_
|
||||||
|
|
||||||
|
#include <device.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */
|
||||||
|
|
||||||
|
int Imxrt1176HwGpioInit(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2021 AIIT XUOS Lab
|
||||||
|
* XiUOS is licensed under Mulan PSL v2.
|
||||||
|
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||||
|
* You may obtain a copy of Mulan PSL v2 at:
|
||||||
|
* http://license.coscl.org.cn/MulanPSL2
|
||||||
|
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||||
|
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||||
|
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||||
|
* See the Mulan PSL v2 for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file connect_uart.h
|
||||||
|
* @brief define imxrt1176-sbc board usart function and struct
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2021-05-28
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CONNECT_UART_H
|
||||||
|
#define CONNECT_UART_H
|
||||||
|
|
||||||
|
#include <device.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
|
||||||
|
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
|
||||||
|
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
|
||||||
|
|
||||||
|
int Imxrt1176HwUartInit(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,552 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2019,2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsl_anatop_ai.h
|
||||||
|
* @brief support imxrt1176-sbc ai
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_anatop_ai.h
|
||||||
|
Description: support imxrt1176-sbc ai
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_ANATOP_AI_H_
|
||||||
|
#define _FSL_ANATOP_AI_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
/*! @addtogroup anatop_ai */
|
||||||
|
/*! @{ */
|
||||||
|
|
||||||
|
/*! @file */
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief Anatop AI driver version 1.0.0. */
|
||||||
|
#define FSL_ANATOP_AI_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Anatop AI ITF enumeration.
|
||||||
|
*/
|
||||||
|
typedef enum _anatop_ai_itf
|
||||||
|
{
|
||||||
|
kAI_Itf_Ldo = 0, /*!< LDO ITF. */
|
||||||
|
kAI_Itf_1g = 1, /*!< 1G PLL ITF. */
|
||||||
|
kAI_Itf_Audio = 2, /*!< Audio PLL ITF. */
|
||||||
|
kAI_Itf_Video = 3, /*!< Video PLL ITF. */
|
||||||
|
kAI_Itf_400m = 4, /*!< 400M OSC ITF. */
|
||||||
|
kAI_Itf_Temp = 5, /*!< Temperature Sensor ITF. */
|
||||||
|
kAI_Itf_Bandgap = 6, /*!< Bandgap ITF. */
|
||||||
|
} anatop_ai_itf_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of ANATOP AI Register.
|
||||||
|
*/
|
||||||
|
typedef enum _anatop_ai_reg
|
||||||
|
{
|
||||||
|
kAI_PHY_LDO_CTRL0 = 0x0, /*!< PHY LDO CTRL0 Register. */
|
||||||
|
kAI_PHY_LDO_CTRL0_SET = 0x4, /*!< PHY LDO CTRL0 Set Register. */
|
||||||
|
kAI_PHY_LDO_CTRL0_CLR = 0x8, /*!< PHY LDO CTRL0 Clr Register. */
|
||||||
|
kAI_PHY_LDO_CTRL0_TOG = 0xC, /*!< PHY LDO CTRL0 TOG Register. */
|
||||||
|
kAI_PHY_LDO_STAT0 = 0x50, /*!< PHY LDO STAT0 Register. */
|
||||||
|
kAI_PHY_LDO_STAT0_SET = 0x54, /*!< PHY LDO STAT0 Set Register. */
|
||||||
|
kAI_PHY_LDO_STAT0_CLR = 0x58, /*!< PHY LDO STAT0 Clr Register. */
|
||||||
|
kAI_PHY_LDO_STAT0_TOG = 0x5C, /*!< PHY LDO STAT0 Tog Register. */
|
||||||
|
|
||||||
|
kAI_BANDGAP_CTRL0 = 0x0, /*!< BANDGAP CTRL0 Register. */
|
||||||
|
kAI_BANDGAP_STAT0 = 0x50, /*!< BANDGAP STAT0 Register. */
|
||||||
|
|
||||||
|
kAI_RCOSC400M_CTRL0 = 0x0, /*!< RC OSC 400M CTRL0 Register. */
|
||||||
|
kAI_RCOSC400M_CTRL0_SET = 0x4, /*!< RC OSC 400M CTRL0 SET Register. */
|
||||||
|
kAI_RCOSC400M_CTRL0_CLR = 0x8, /*!< RC OSC 400M CTRL0 CLR Register. */
|
||||||
|
kAI_RCOSC400M_CTRL0_TOG = 0xC, /*!< RC OSC 400M CTRL0 TOG Register. */
|
||||||
|
kAI_RCOSC400M_CTRL1 = 0x10, /*!< RC OSC 400M CTRL1 Register. */
|
||||||
|
kAI_RCOSC400M_CTRL1_SET = 0x14, /*!< RC OSC 400M CTRL1 SET Register. */
|
||||||
|
kAI_RCOSC400M_CTRL1_CLR = 0x18, /*!< RC OSC 400M CTRL1 CLR Register. */
|
||||||
|
kAI_RCOSC400M_CTRL1_TOG = 0x1C, /*!< RC OSC 400M CTRL1 TOG Register. */
|
||||||
|
kAI_RCOSC400M_CTRL2 = 0x20, /*!< RC OSC 400M CTRL2 Register. */
|
||||||
|
kAI_RCOSC400M_CTRL2_SET = 0x24, /*!< RC OSC 400M CTRL2 SET Register. */
|
||||||
|
kAI_RCOSC400M_CTRL2_CLR = 0x28, /*!< RC OSC 400M CTRL2 CLR Register. */
|
||||||
|
kAI_RCOSC400M_CTRL2_TOG = 0x2C, /*!< RC OSC 400M CTRL2 TOG Register. */
|
||||||
|
kAI_RCOSC400M_CTRL3 = 0x30, /*!< RC OSC 400M CTRL3 Register. */
|
||||||
|
kAI_RCOSC400M_CTRL3_SET = 0x34, /*!< RC OSC 400M CTRL3 SET Register. */
|
||||||
|
kAI_RCOSC400M_CTRL3_CLR = 0x38, /*!< RC OSC 400M CTRL3 CLR Register. */
|
||||||
|
kAI_RCOSC400M_CTRL3_TOG = 0x3C, /*!< RC OSC 400M CTRL3 TOG Register. */
|
||||||
|
kAI_RCOSC400M_STAT0 = 0x50, /*!< RC OSC 400M STAT0 Register. */
|
||||||
|
kAI_RCOSC400M_STAT0_SET = 0x54, /*!< RC OSC 400M STAT0 SET Register. */
|
||||||
|
kAI_RCOSC400M_STAT0_CLR = 0x58, /*!< RC OSC 400M STAT0 CLR Register. */
|
||||||
|
kAI_RCOSC400M_STAT0_TOG = 0x5C, /*!< RC OSC 400M STAT0 TOG Register. */
|
||||||
|
kAI_RCOSC400M_STAT1 = 0x60, /*!< RC OSC 400M STAT1 Register. */
|
||||||
|
kAI_RCOSC400M_STAT1_SET = 0x64, /*!< RC OSC 400M STAT1 SET Register. */
|
||||||
|
kAI_RCOSC400M_STAT1_CLR = 0x68, /*!< RC OSC 400M STAT1 CLR Register. */
|
||||||
|
kAI_RCOSC400M_STAT1_TOG = 0x6C, /*!< RC OSC 400M STAT1 TOG Register. */
|
||||||
|
kAI_RCOSC400M_STAT2 = 0x70, /*!< RC OSC 400M STAT2 Register. */
|
||||||
|
kAI_RCOSC400M_STAT2_SET = 0x74, /*!< RC OSC 400M STAT2 SET Register. */
|
||||||
|
kAI_RCOSC400M_STAT2_CLR = 0x78, /*!< RC OSC 400M STAT2 CLR Register. */
|
||||||
|
kAI_RCOSC400M_STAT2_TOG = 0x7C, /*!< RC OSC 400M STAT2 TOG Register. */
|
||||||
|
|
||||||
|
kAI_PLL1G_CTRL0 = 0x0, /*!< 1G PLL CTRL0 Register. */
|
||||||
|
kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */
|
||||||
|
kAI_PLL1G_CTRL0_CLR = 0x8, /*!< 1G PLL CTRL0 CLR Register. */
|
||||||
|
kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */
|
||||||
|
kAI_PLL1G_CTRL1_SET = 0x14, /*!< 1G PLL CTRL1 SET Register. */
|
||||||
|
kAI_PLL1G_CTRL1_CLR = 0x18, /*!< 1G PLL CTRL1 CLR Register. */
|
||||||
|
kAI_PLL1G_CTRL2 = 0x20, /*!< 1G PLL CTRL2 Register. */
|
||||||
|
kAI_PLL1G_CTRL2_SET = 0x24, /*!< 1G PLL CTRL2 SET Register. */
|
||||||
|
kAI_PLL1G_CTRL2_CLR = 0x28, /*!< 1G PLL CTRL2 CLR Register. */
|
||||||
|
kAI_PLL1G_CTRL3 = 0x30, /*!< 1G PLL CTRL3 Register. */
|
||||||
|
kAI_PLL1G_CTRL3_SET = 0x34, /*!< 1G PLL CTRL3 SET Register. */
|
||||||
|
kAI_PLL1G_CTRL3_CLR = 0x38, /*!< 1G PLL CTRL3 CLR Register. */
|
||||||
|
|
||||||
|
kAI_PLLAUDIO_CTRL0 = 0x0, /*!< AUDIO PLL CTRL0 Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL0_SET = 0x4, /*!< AUDIO PLL CTRL0 SET Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL0_CLR = 0x8, /*!< AUDIO PLL CTRL0 CLR Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL1 = 0x10, /*!< AUDIO PLL CTRL1 Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL1_SET = 0x14, /*!< AUDIO PLL CTRL1 SET Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL1_CLR = 0x18, /*!< AUDIO PLL CTRL1 CLR Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL2 = 0x20, /*!< AUDIO PLL CTRL2 Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL2_SET = 0x24, /*!< AUDIO PLL CTRL2 SET Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL2_CLR = 0x28, /*!< AUDIO PLL CTRL2 CLR Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL3 = 0x30, /*!< AUDIO PLL CTRL3 Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL3_SET = 0x34, /*!< AUDIO PLL CTRL3 SET Register. */
|
||||||
|
kAI_PLLAUDIO_CTRL3_CLR = 0x38, /*!< AUDIO PLL CTRL3 CLR Register. */
|
||||||
|
|
||||||
|
kAI_PLLVIDEO_CTRL0 = 0x0, /*!< VIDEO PLL CTRL0 Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL0_SET = 0x4, /*!< VIDEO PLL CTRL0 SET Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL0_CLR = 0x8, /*!< VIDEO PLL CTRL0 CLR Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL1 = 0x10, /*!< VIDEO PLL CTRL1 Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL1_SET = 0x14, /*!< VIDEO PLL CTRL1 SET Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL1_CLR = 0x18, /*!< VIDEO PLL CTRL1 CLR Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL2 = 0x20, /*!< VIDEO PLL CTRL2 Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL2_SET = 0x24, /*!< VIDEO PLL CTRL2 SET Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL2_CLR = 0x28, /*!< VIDEO PLL CTRL2 CLR Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL3 = 0x30, /*!< VIDEO PLL CTRL3 Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL3_SET = 0x34, /*!< VIDEO PLL CTRL3 SET Register. */
|
||||||
|
kAI_PLLVIDEO_CTRL3_CLR = 0x38, /*!< VIDEO PLL CTRL3 CLR Register. */
|
||||||
|
} anatop_ai_reg_t;
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
-- AI PHY_LDO CTRL0 Register Masks
|
||||||
|
---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_PHY_LDO_CTRL0_LINREG_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK)
|
||||||
|
#define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U)
|
||||||
|
#define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U)
|
||||||
|
|
||||||
|
/*! LINREG_EN - LinReg master enable
|
||||||
|
* LinReg master enable. Setting this bit will enable the regular
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK)
|
||||||
|
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U)
|
||||||
|
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U)
|
||||||
|
/*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
|
||||||
|
* 0b0..Internal pull-down enabled
|
||||||
|
* 0b1..Internal pull-down disabled
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_PHY_LDO_CTRL0_LIMIT_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)
|
||||||
|
#define AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U)
|
||||||
|
#define AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U)
|
||||||
|
/*! LINREG_LIMIT_EN - LinReg current limit enable
|
||||||
|
* LinReg current-limit enable. Setting this bit will enable the
|
||||||
|
* current-limiter in the regulator
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK)
|
||||||
|
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U)
|
||||||
|
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U)
|
||||||
|
/*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
|
||||||
|
* 0b00000..Set output voltage to x.xV
|
||||||
|
* 0b10000..Set output voltage to 1.0V
|
||||||
|
* 0b11111..Set output voltage to x.xV
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_PHY_LDO_CTRL0_PHY_ISO_B(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK)
|
||||||
|
#define AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U)
|
||||||
|
#define AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U)
|
||||||
|
/*! LINREG_PHY_ISO_B - Isolation control for attached PHY load
|
||||||
|
* This control bit is to be used by the system controller to isolate the
|
||||||
|
* attached PHY load when the LinReg is powered down. During a power-up
|
||||||
|
* event of the regulator it is expected that this control signal is set high
|
||||||
|
* at least 100us after the main regulator is enabled. During a power-down
|
||||||
|
* event of the regulator it is expected that this control signal is set low
|
||||||
|
* before the main regulator is disabled/power-down.
|
||||||
|
*/
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name STAT0 - STAT0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_PHY_LDO_STAT0_LINREG_STAT(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK)
|
||||||
|
#define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU)
|
||||||
|
#define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U)
|
||||||
|
|
||||||
|
/*! LINREG_STAT - LinReg status bits
|
||||||
|
* LinReg status bits.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWD(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U)
|
||||||
|
/*! REFTOP_PWD - This bit fully powers down the bandgap module.
|
||||||
|
* Setting this bit high will disable reference output currents and voltages from the
|
||||||
|
* bandgap and will affect functionality and validity of the voltage detectors.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & \
|
||||||
|
AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
|
||||||
|
/*!
|
||||||
|
* REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap.
|
||||||
|
* Setting this bit high will affect functionality and validity
|
||||||
|
* of the voltage detectors.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U)
|
||||||
|
/*!
|
||||||
|
* REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap
|
||||||
|
* without affecting any additional functionality.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)
|
||||||
|
/*!
|
||||||
|
* REFTOP_LOWPOWER - This bit enables the low-power operation of the
|
||||||
|
* bandgap by cutting the bias currents in half to the main amplifiers.
|
||||||
|
* This will save power but could affect the accuracy of the output voltages and currents.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \
|
||||||
|
AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
|
||||||
|
/*!
|
||||||
|
* REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap.
|
||||||
|
* The self-bias circuit is used by the bandgap during startup. This bit should be
|
||||||
|
* set high after the bandgap has stabilized and is necessary for best noise performance
|
||||||
|
* of modules using the outputs of the bandgap. It is expected that this control bit
|
||||||
|
* be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U)
|
||||||
|
/*!
|
||||||
|
* REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed
|
||||||
|
* 000 : nominal
|
||||||
|
* 001 : +10mV
|
||||||
|
* 010 : +20mV
|
||||||
|
* 011 : +30mV
|
||||||
|
* 100 : -10mV
|
||||||
|
* 101 : -20mV
|
||||||
|
* 110 : -30mV
|
||||||
|
* 111 : -40mV
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U)
|
||||||
|
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U)
|
||||||
|
/*!
|
||||||
|
* REFTOP_IBZTCADJ - These bits allow trimming of the ZTC bias currents from the bandgap to
|
||||||
|
* the temperature sensors. Assuming a typical process corner the expected values of output
|
||||||
|
* currents are:
|
||||||
|
* 000 : 11.5 uA
|
||||||
|
* 001 : 11.8 uA
|
||||||
|
* 010 : 12.1 uA
|
||||||
|
* 100 : 12.4 uA (Nominal expected from MX8QM tempsensor)
|
||||||
|
* 101 : 12.7 uA
|
||||||
|
* 110 : 13.0 uA
|
||||||
|
* 111 : 13.3 uA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name STAT0 - STAT0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_BANDGAP_STAT0_REFTOP_VBGUP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK)
|
||||||
|
#define AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U)
|
||||||
|
#define AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U)
|
||||||
|
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL1 - CTRL1 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_MINUS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU)
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_PLUS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U)
|
||||||
|
#define AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL1_TARGET_COUNT(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U)
|
||||||
|
#define AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL2 - CTRL2 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_BYP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_START(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U)
|
||||||
|
#define AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
|
||||||
|
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL3 - CTRL3 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_CTRL3_CLR_ERR(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U)
|
||||||
|
#define AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL3_EN_1M_CLK(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U)
|
||||||
|
#define AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U)
|
||||||
|
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U)
|
||||||
|
|
||||||
|
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK)
|
||||||
|
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U)
|
||||||
|
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name STAT0 - STAT0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_STAT0_CLK1M_ERR(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
|
||||||
|
#define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U)
|
||||||
|
#define AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name STAT1 - STAT1 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK)
|
||||||
|
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U)
|
||||||
|
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name STAT2 - STAT2 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & \
|
||||||
|
AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
|
||||||
|
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
|
||||||
|
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_PLL1G_CTRL0_HOLD_RING_OFF(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK)
|
||||||
|
#define AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
|
||||||
|
#define AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U)
|
||||||
|
|
||||||
|
#define AI_PLL1G_CTRL0_POWER_UP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK)
|
||||||
|
#define AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL)
|
||||||
|
#define AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U)
|
||||||
|
|
||||||
|
#define AI_PLL1G_CTRL0_ENABLE(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK)
|
||||||
|
#define AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL)
|
||||||
|
#define AI_PLL1G_CTRL0_ENABLE_SHIFT (15U)
|
||||||
|
|
||||||
|
#define AI_PLL1G_CTRL0_BYPASS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK)
|
||||||
|
#define AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL)
|
||||||
|
#define AI_PLL1G_CTRL0_BYPASS_SHIFT (16U)
|
||||||
|
|
||||||
|
#define AI_PLL1G_CTRL0_PLL_REG_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK)
|
||||||
|
#define AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL)
|
||||||
|
#define AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U)
|
||||||
|
|
||||||
|
#define AI_PLLAUDIO_CTRL0_POWER_UP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U)
|
||||||
|
|
||||||
|
#define AI_PLLAUDIO_CTRL0_ENABLE(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U)
|
||||||
|
|
||||||
|
#define AI_PLLAUDIO_CTRL0_BYPASS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U)
|
||||||
|
|
||||||
|
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL)
|
||||||
|
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @name CTRL0 - CTRL0 Register */
|
||||||
|
/*! @{ */
|
||||||
|
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U)
|
||||||
|
|
||||||
|
#define AI_PLLVIDEO_CTRL0_POWER_UP(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U)
|
||||||
|
|
||||||
|
#define AI_PLLVIDEO_CTRL0_ENABLE(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U)
|
||||||
|
|
||||||
|
#define AI_PLLVIDEO_CTRL0_BYPASS(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U)
|
||||||
|
|
||||||
|
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) \
|
||||||
|
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL)
|
||||||
|
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U)
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief AI interface access
|
||||||
|
*
|
||||||
|
* @param itf AI interface name
|
||||||
|
* @param isWrite write enable
|
||||||
|
* @param addr address
|
||||||
|
* @param wdata data to be set
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief AI interface writing
|
||||||
|
*
|
||||||
|
* @param itf AI interface name
|
||||||
|
* @param addr address
|
||||||
|
* @param wdata data to be set
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief AI interface reading
|
||||||
|
*
|
||||||
|
* @param itf AI interface name
|
||||||
|
* @param addr address
|
||||||
|
* @return data read
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief AI interface write with mask and shift
|
||||||
|
*
|
||||||
|
* @param itf AI interface name
|
||||||
|
* @param addr address
|
||||||
|
* @param wdata data to be written
|
||||||
|
* @param mask bit field mask
|
||||||
|
* @param shift bit field shift
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void ANATOP_AI_WriteWithMaskShift(
|
||||||
|
anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
|
||||||
|
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
#endif /* _FSL_ANATOP_AI_H_ */
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,331 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file fsl_common.h
|
||||||
|
* @brief
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_common.h
|
||||||
|
Description:
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_COMMON_H_
|
||||||
|
#define _FSL_COMMON_H_
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
/* if need hperflash driver must define these macor */
|
||||||
|
// #define XIP_BOOT_HEADER_ENABLE (1)
|
||||||
|
// #define XIP_BOOT_HEADER_DCD_ENABLE (1)
|
||||||
|
|
||||||
|
#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
|
||||||
|
#include <stddef.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup ksdk_common
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Configurations
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief Macro to use the default weak IRQ handler in drivers. */
|
||||||
|
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
||||||
|
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief Construct a status code value from a group and code number. */
|
||||||
|
#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
|
||||||
|
|
||||||
|
/*! @brief Construct the version number for drivers.
|
||||||
|
*
|
||||||
|
* The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
|
||||||
|
* and 16-bit platforms(such as DSC).
|
||||||
|
*
|
||||||
|
* @verbatim
|
||||||
|
|
||||||
|
| Unused || Major Version || Minor Version || Bug Fix |
|
||||||
|
31 25 24 17 16 9 8 0
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
*/
|
||||||
|
#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix))
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief common driver version. */
|
||||||
|
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/* Debug console type definition. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
||||||
|
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
|
||||||
|
|
||||||
|
/*! @brief Status group numbers. */
|
||||||
|
enum _status_groups
|
||||||
|
{
|
||||||
|
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||||
|
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||||
|
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||||
|
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||||
|
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||||
|
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||||
|
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||||
|
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||||
|
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||||
|
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||||
|
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||||
|
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||||
|
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||||
|
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||||
|
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||||
|
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||||
|
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||||
|
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||||
|
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||||
|
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||||
|
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||||
|
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||||
|
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||||
|
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||||
|
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||||
|
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||||
|
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||||
|
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||||
|
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||||
|
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||||
|
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||||
|
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||||
|
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||||
|
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||||
|
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||||
|
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||||
|
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||||
|
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||||
|
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||||
|
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||||
|
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||||
|
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||||
|
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||||
|
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||||
|
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||||
|
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||||
|
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||||
|
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||||
|
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||||
|
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||||
|
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||||
|
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||||
|
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||||
|
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||||
|
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||||
|
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||||
|
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||||
|
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||||
|
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||||
|
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
||||||
|
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||||
|
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||||
|
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||||
|
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||||
|
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||||
|
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||||
|
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
|
||||||
|
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||||
|
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||||
|
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||||
|
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||||
|
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||||
|
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
||||||
|
kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
|
||||||
|
kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
|
||||||
|
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
|
||||||
|
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
|
||||||
|
|
||||||
|
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
||||||
|
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
||||||
|
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
||||||
|
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
||||||
|
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
||||||
|
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
||||||
|
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
||||||
|
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
||||||
|
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
|
||||||
|
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
||||||
|
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
||||||
|
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
||||||
|
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
||||||
|
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
||||||
|
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
||||||
|
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
||||||
|
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
||||||
|
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||||
|
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||||
|
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||||
|
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
|
||||||
|
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
|
||||||
|
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
|
||||||
|
kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
|
||||||
|
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
|
||||||
|
kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
|
||||||
|
kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
|
||||||
|
kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
|
||||||
|
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
|
||||||
|
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
|
||||||
|
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
|
||||||
|
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
|
||||||
|
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
|
||||||
|
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*! \public
|
||||||
|
* @brief Generic status return codes.
|
||||||
|
*/
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
|
||||||
|
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
|
||||||
|
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
|
||||||
|
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
|
||||||
|
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
|
||||||
|
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
|
||||||
|
kStatus_NoTransferInProgress =
|
||||||
|
MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
|
||||||
|
kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
|
||||||
|
kStatus_NoData =
|
||||||
|
MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*! @brief Type used for all status and error return values. */
|
||||||
|
typedef int32_t status_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Min/max macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if !defined(MIN)
|
||||||
|
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MAX)
|
||||||
|
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||||
|
#endif
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @brief Computes the number of elements in an array. */
|
||||||
|
#if !defined(ARRAY_SIZE)
|
||||||
|
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||||
|
/* @{ */
|
||||||
|
#if !defined(UINT16_MAX)
|
||||||
|
#define UINT16_MAX ((uint16_t)-1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(UINT32_MAX)
|
||||||
|
#define UINT32_MAX ((uint32_t)-1)
|
||||||
|
#endif
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @name Suppress fallthrough warning macro */
|
||||||
|
/* For switch case code block, if case section ends without "break;" statement, there wil be
|
||||||
|
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
|
||||||
|
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
|
||||||
|
case section which misses "break;"statement.
|
||||||
|
*/
|
||||||
|
/* @{ */
|
||||||
|
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||||
|
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
|
||||||
|
#else
|
||||||
|
#define SUPPRESS_FALL_THROUGH_WARNING()
|
||||||
|
#endif
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Allocate memory with given alignment and aligned size.
|
||||||
|
*
|
||||||
|
* This is provided to support the dynamically allocated memory
|
||||||
|
* used in cache-able region.
|
||||||
|
* @param size The length required to malloc.
|
||||||
|
* @param alignbytes The alignment size.
|
||||||
|
* @retval The allocated memory.
|
||||||
|
*/
|
||||||
|
void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Free memory.
|
||||||
|
*
|
||||||
|
* @param ptr The memory to be release.
|
||||||
|
*/
|
||||||
|
void SDK_Free(void *ptr);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Delay at least for some time.
|
||||||
|
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
|
||||||
|
* if precise delay count was needed, please implement a new delay function with hardware timer.
|
||||||
|
*
|
||||||
|
* @param delayTime_us Delay time in unit of microsecond.
|
||||||
|
* @param coreClock_Hz Core clock frequency with Hz.
|
||||||
|
*/
|
||||||
|
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
#if (defined(__DSC__) && defined(__CW__))
|
||||||
|
#include "fsl_common_dsc.h"
|
||||||
|
#elif defined(__XCC__)
|
||||||
|
#include "fsl_common_dsp.h"
|
||||||
|
#else
|
||||||
|
#include "fsl_common_arm.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _FSL_COMMON_H_ */
|
||||||
|
|
@ -0,0 +1,689 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file fsl_common_arm.h
|
||||||
|
* @brief support imxrt1176-sbc interrupt
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_common_arm.h
|
||||||
|
Description: support imxrt1176-sbc interrupt
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_COMMON_ARM_H_
|
||||||
|
#define _FSL_COMMON_ARM_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For CMSIS pack RTE.
|
||||||
|
* CMSIS pack RTE generates "RTC_Components.h" which contains the statements
|
||||||
|
* of the related <RTE_Components_h> element for all selected software components.
|
||||||
|
*/
|
||||||
|
#ifdef _RTE_
|
||||||
|
#include "RTE_Components.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup ksdk_common
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*! @name Atomic modification
|
||||||
|
*
|
||||||
|
* These macros are used for atomic access, such as read-modify-write
|
||||||
|
* to the peripheral registers.
|
||||||
|
*
|
||||||
|
* - SDK_ATOMIC_LOCAL_ADD
|
||||||
|
* - SDK_ATOMIC_LOCAL_SET
|
||||||
|
* - SDK_ATOMIC_LOCAL_CLEAR
|
||||||
|
* - SDK_ATOMIC_LOCAL_TOGGLE
|
||||||
|
* - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
|
||||||
|
*
|
||||||
|
* Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
|
||||||
|
* means the address of the peripheral register or variable you want to modify
|
||||||
|
* atomically, the parameter @c clearBits is the bits to clear, the parameter
|
||||||
|
* @c setBits it the bits to set.
|
||||||
|
* For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
|
||||||
|
*
|
||||||
|
* @code
|
||||||
|
volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
|
||||||
|
|
||||||
|
SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
|
||||||
|
@endcode
|
||||||
|
*
|
||||||
|
* In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
|
||||||
|
* register bit1:bit0 = 0b10.
|
||||||
|
*
|
||||||
|
* @note For the platforms don't support exclusive load and store, these macros
|
||||||
|
* disable the global interrupt to pretect the modification.
|
||||||
|
*
|
||||||
|
* @note These macros only guarantee the local processor atomic operations. For
|
||||||
|
* the multi-processor devices, use hardware semaphore such as SEMA42 to
|
||||||
|
* guarantee exclusive access if necessary.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* clang-format off */
|
||||||
|
#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||||
|
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
|
||||||
|
/* clang-format on */
|
||||||
|
|
||||||
|
/* If the LDREX and STREX are supported, use them. */
|
||||||
|
#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
(val) = __LDREXB(addr); \
|
||||||
|
(ops); \
|
||||||
|
} while (0UL != __STREXB((val), (addr)))
|
||||||
|
|
||||||
|
#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
(val) = __LDREXH(addr); \
|
||||||
|
(ops); \
|
||||||
|
} while (0UL != __STREXH((val), (addr)))
|
||||||
|
|
||||||
|
#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
(val) = __LDREXW(addr); \
|
||||||
|
(ops); \
|
||||||
|
} while (0UL != __STREXW((val), (addr)))
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
|
||||||
|
{
|
||||||
|
uint8_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
|
||||||
|
{
|
||||||
|
uint16_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
|
||||||
|
{
|
||||||
|
uint32_t s_val;
|
||||||
|
|
||||||
|
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
|
||||||
|
((1UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \
|
||||||
|
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
|
||||||
|
_SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
|
||||||
|
((1UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||||
|
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||||
|
_SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
|
||||||
|
((1UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||||
|
((2UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||||
|
_SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
|
||||||
|
((1UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||||
|
((2UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||||
|
_SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
|
||||||
|
((1UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \
|
||||||
|
((2UL == sizeof(*(addr))) ? \
|
||||||
|
_SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
|
||||||
|
_SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
uint32_t s_atomicOldInt; \
|
||||||
|
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||||
|
*(addr) += (val); \
|
||||||
|
EnableGlobalIRQ(s_atomicOldInt); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
uint32_t s_atomicOldInt; \
|
||||||
|
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||||
|
*(addr) |= (bits); \
|
||||||
|
EnableGlobalIRQ(s_atomicOldInt); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
uint32_t s_atomicOldInt; \
|
||||||
|
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||||
|
*(addr) &= ~(bits); \
|
||||||
|
EnableGlobalIRQ(s_atomicOldInt); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
uint32_t s_atomicOldInt; \
|
||||||
|
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||||
|
*(addr) ^= (bits); \
|
||||||
|
EnableGlobalIRQ(s_atomicOldInt); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
|
||||||
|
do \
|
||||||
|
{ \
|
||||||
|
uint32_t s_atomicOldInt; \
|
||||||
|
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||||
|
*(addr) = (*(addr) & ~(clearBits)) | (setBits); \
|
||||||
|
EnableGlobalIRQ(s_atomicOldInt); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @name Timer utilities */
|
||||||
|
/* @{ */
|
||||||
|
/*! Macro to convert a microsecond period to raw count value */
|
||||||
|
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
|
||||||
|
/*! Macro to convert a raw count value to microsecond */
|
||||||
|
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
|
||||||
|
|
||||||
|
/*! Macro to convert a millisecond period to raw count value */
|
||||||
|
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
|
||||||
|
/*! Macro to convert a raw count value to millisecond */
|
||||||
|
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @name ISR exit barrier
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||||
|
* exception return operation might vector to incorrect interrupt.
|
||||||
|
* For Cortex-M7, if core speed much faster than peripheral register write speed,
|
||||||
|
* the peripheral interrupt flags may be still set after exiting ISR, this results to
|
||||||
|
* the same error similar with errata 83869.
|
||||||
|
*/
|
||||||
|
#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
|
||||||
|
#define SDK_ISR_EXIT_BARRIER __DSB()
|
||||||
|
#else
|
||||||
|
#define SDK_ISR_EXIT_BARRIER
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @name Alignment variable definition macros */
|
||||||
|
/* @{ */
|
||||||
|
#if (defined(__ICCARM__))
|
||||||
|
/*
|
||||||
|
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||||
|
* http:/ /supp.iar.com/Support/?note=24725
|
||||||
|
*/
|
||||||
|
_Pragma("diag_suppress=Pm120")
|
||||||
|
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||||
|
_Pragma("diag_error=Pm120")
|
||||||
|
/*! Macro to define a variable with alignbytes alignment */
|
||||||
|
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||||
|
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
/*! Macro to define a variable with alignbytes alignment */
|
||||||
|
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
/*! Macro to define a variable with alignbytes alignment */
|
||||||
|
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||||
|
#else
|
||||||
|
#error Toolchain not supported
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||||
|
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||||
|
#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||||
|
#endif
|
||||||
|
/*! Macro to define a variable with L2 cache line size alignment */
|
||||||
|
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||||
|
#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! Macro to change a value to a given size aligned value */
|
||||||
|
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||||
|
((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*! @name Non-cacheable region definition macros */
|
||||||
|
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||||
|
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
|
||||||
|
* variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
|
||||||
|
* these zero-inited variables will be initialized to zero in system startup.
|
||||||
|
*/
|
||||||
|
/* @{ */
|
||||||
|
|
||||||
|
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
|
||||||
|
defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||||
|
|
||||||
|
#if (defined(__ICCARM__))
|
||||||
|
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||||
|
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||||
|
SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||||
|
|
||||||
|
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||||
|
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||||
|
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
||||||
|
#if (defined(__CC_ARM))
|
||||||
|
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||||
|
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
||||||
|
#else
|
||||||
|
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||||
|
__attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif (defined(__GNUC__))
|
||||||
|
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||||
|
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||||
|
*/
|
||||||
|
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||||
|
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||||
|
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||||
|
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||||
|
#else
|
||||||
|
#error Toolchain not supported.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define AT_NONCACHEABLE_SECTION(var) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
|
||||||
|
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||||
|
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Time sensitive region
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if (defined(__ICCARM__))
|
||||||
|
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess"
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||||
|
SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
|
||||||
|
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||||
|
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||||
|
__attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
|
||||||
|
#elif (defined(__GNUC__))
|
||||||
|
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
||||||
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||||
|
__attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
|
||||||
|
#else
|
||||||
|
#error Toolchain not supported.
|
||||||
|
#endif /* defined(__ICCARM__) */
|
||||||
|
|
||||||
|
/*! @name Ram Function */
|
||||||
|
#if (defined(__ICCARM__))
|
||||||
|
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
||||||
|
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||||
|
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||||
|
#elif (defined(__GNUC__))
|
||||||
|
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||||
|
#else
|
||||||
|
#error Toolchain not supported.
|
||||||
|
#endif /* defined(__ICCARM__) */
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
void DefaultISR(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||||
|
* defined in previous of this file.
|
||||||
|
*/
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||||
|
*/
|
||||||
|
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||||
|
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||||
|
#include "fsl_reset.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable specific interrupt.
|
||||||
|
*
|
||||||
|
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||||
|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||||
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||||
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||||
|
* to NVIC first then routed to core.
|
||||||
|
*
|
||||||
|
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||||
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||||
|
*
|
||||||
|
* @param interrupt The IRQ number.
|
||||||
|
* @retval kStatus_Success Interrupt enabled successfully
|
||||||
|
* @retval kStatus_Fail Failed to enable the interrupt
|
||||||
|
*/
|
||||||
|
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||||
|
{
|
||||||
|
status_t status = kStatus_Success;
|
||||||
|
|
||||||
|
if (NotAvail_IRQn == interrupt)
|
||||||
|
{
|
||||||
|
status = kStatus_Fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||||
|
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||||
|
{
|
||||||
|
status = kStatus_Fail;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(__GIC_PRIO_BITS)
|
||||||
|
GIC_EnableIRQ(interrupt);
|
||||||
|
#else
|
||||||
|
NVIC_EnableIRQ(interrupt);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable specific interrupt.
|
||||||
|
*
|
||||||
|
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||||
|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||||
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||||
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||||
|
* to NVIC first then routed to core.
|
||||||
|
*
|
||||||
|
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||||
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||||
|
*
|
||||||
|
* @param interrupt The IRQ number.
|
||||||
|
* @retval kStatus_Success Interrupt disabled successfully
|
||||||
|
* @retval kStatus_Fail Failed to disable the interrupt
|
||||||
|
*/
|
||||||
|
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||||
|
{
|
||||||
|
status_t status = kStatus_Success;
|
||||||
|
|
||||||
|
if (NotAvail_IRQn == interrupt)
|
||||||
|
{
|
||||||
|
status = kStatus_Fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||||
|
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||||
|
{
|
||||||
|
status = kStatus_Fail;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(__GIC_PRIO_BITS)
|
||||||
|
GIC_DisableIRQ(interrupt);
|
||||||
|
#else
|
||||||
|
NVIC_DisableIRQ(interrupt);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the global IRQ
|
||||||
|
*
|
||||||
|
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||||
|
* register for the EnableGlobalIRQ().
|
||||||
|
*
|
||||||
|
* @return Current primask value.
|
||||||
|
*/
|
||||||
|
static inline uint32_t DisableGlobalIRQ(void)
|
||||||
|
{
|
||||||
|
#if defined(CPSR_I_Msk)
|
||||||
|
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||||
|
|
||||||
|
__disable_irq();
|
||||||
|
|
||||||
|
return cpsr;
|
||||||
|
#else
|
||||||
|
uint32_t regPrimask = __get_PRIMASK();
|
||||||
|
|
||||||
|
__disable_irq();
|
||||||
|
|
||||||
|
return regPrimask;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable the global IRQ
|
||||||
|
*
|
||||||
|
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||||
|
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||||
|
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||||
|
*
|
||||||
|
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||||
|
* DisableGlobalIRQ().
|
||||||
|
*/
|
||||||
|
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||||
|
{
|
||||||
|
#if defined(CPSR_I_Msk)
|
||||||
|
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||||
|
#else
|
||||||
|
__set_PRIMASK(primask);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||||
|
/*!
|
||||||
|
* @brief install IRQ handler
|
||||||
|
*
|
||||||
|
* @param irq IRQ number
|
||||||
|
* @param irqHandler IRQ handler address
|
||||||
|
* @return The old IRQ handler address
|
||||||
|
*/
|
||||||
|
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||||
|
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||||
|
|
||||||
|
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
|
||||||
|
* powerlib should be used instead of these functions.
|
||||||
|
*/
|
||||||
|
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
|
||||||
|
/*!
|
||||||
|
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||||
|
*
|
||||||
|
* Enable the interrupt for wake-up from deep sleep mode.
|
||||||
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||||
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||||
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||||
|
* making these wake-ups possible.
|
||||||
|
*
|
||||||
|
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
||||||
|
*
|
||||||
|
* @param interrupt The IRQ number.
|
||||||
|
*/
|
||||||
|
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||||
|
*
|
||||||
|
* Disable the interrupt for wake-up from deep sleep mode.
|
||||||
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||||
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||||
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||||
|
* making these wake-ups possible.
|
||||||
|
*
|
||||||
|
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
||||||
|
*
|
||||||
|
* @param interrupt The IRQ number.
|
||||||
|
*/
|
||||||
|
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||||
|
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
|
||||||
|
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*! @} */
|
||||||
|
|
||||||
|
#endif /* _FSL_COMMON_ARM_H_ */
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2019 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file fsl_device_registers.h
|
||||||
|
* @brief
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_device_registers.h
|
||||||
|
Description:
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||||
|
#define __FSL_DEVICE_REGISTERS_H__
|
||||||
|
|
||||||
|
#define CPU_MIMXRT1176DVMAA_cm7
|
||||||
|
/*
|
||||||
|
* Include the cpu specific register header files.
|
||||||
|
*
|
||||||
|
* The CPU macro should be declared in the project or makefile.
|
||||||
|
*/
|
||||||
|
#if (defined(CPU_MIMXRT1176AVM8A_cm7) || defined(CPU_MIMXRT1176CVM8A_cm7) || defined(CPU_MIMXRT1176DVMAA_cm7))
|
||||||
|
|
||||||
|
#define MIMXRT1176_cm7_SERIES
|
||||||
|
|
||||||
|
/* CMSIS-style register definitions */
|
||||||
|
#include "MIMXRT1176_cm7.h"
|
||||||
|
/* CPU specific feature definitions */
|
||||||
|
#include "MIMXRT1176_cm7_features.h"
|
||||||
|
|
||||||
|
#elif (defined(CPU_MIMXRT1176AVM8A_cm4) || defined(CPU_MIMXRT1176CVM8A_cm4) || defined(CPU_MIMXRT1176DVMAA_cm4))
|
||||||
|
|
||||||
|
#define MIMXRT1176_cm4_SERIES
|
||||||
|
|
||||||
|
/* CMSIS-style register definitions */
|
||||||
|
#include "MIMXRT1176_cm4.h"
|
||||||
|
/* CPU specific feature definitions */
|
||||||
|
#include "MIMXRT1176_cm4_features.h"
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error "No valid CPU defined!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* EOF
|
||||||
|
******************************************************************************/
|
||||||
|
|
@ -0,0 +1,362 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file fsl_gpio.h
|
||||||
|
* @brief support imxrt1176-sbc gpio
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_gpio.h
|
||||||
|
Description: support imxrt1176-sbc gpio
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_GPIO_H_
|
||||||
|
#define _FSL_GPIO_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup gpio_driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief GPIO driver version. */
|
||||||
|
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*! @brief GPIO direction definition. */
|
||||||
|
typedef enum _gpio_pin_direction
|
||||||
|
{
|
||||||
|
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/
|
||||||
|
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/
|
||||||
|
} gpio_pin_direction_t;
|
||||||
|
|
||||||
|
/*! @brief GPIO interrupt mode definition. */
|
||||||
|
typedef enum _gpio_interrupt_mode
|
||||||
|
{
|
||||||
|
kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/
|
||||||
|
kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/
|
||||||
|
kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/
|
||||||
|
kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/
|
||||||
|
kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/
|
||||||
|
kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/
|
||||||
|
} gpio_interrupt_mode_t;
|
||||||
|
|
||||||
|
/*! @brief GPIO Init structure definition. */
|
||||||
|
typedef struct _gpio_pin_config
|
||||||
|
{
|
||||||
|
gpio_pin_direction_t direction; /*!< Specifies the pin direction. */
|
||||||
|
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
|
||||||
|
gpio_interrupt_mode_t
|
||||||
|
interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */
|
||||||
|
} gpio_pin_config_t;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name GPIO Initialization and Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initializes the GPIO peripheral according to the specified
|
||||||
|
* parameters in the initConfig.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param pin Specifies the pin number
|
||||||
|
* @param Config pointer to a @ref gpio_pin_config_t structure that
|
||||||
|
* contains the configuration information.
|
||||||
|
*/
|
||||||
|
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name GPIO Reads and Write Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param pin GPIO port pin number.
|
||||||
|
* @param output GPIOpin output logic level.
|
||||||
|
* - 0: corresponding pin output low-logic level.
|
||||||
|
* - 1: corresponding pin output high-logic level.
|
||||||
|
*/
|
||||||
|
void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
|
||||||
|
{
|
||||||
|
GPIO_PinWrite(base, pin, output);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||||
|
*
|
||||||
|
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||||
|
* @param mask GPIO pin number macro
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1))
|
||||||
|
base->DR_SET = mask;
|
||||||
|
#else
|
||||||
|
base->DR |= mask;
|
||||||
|
#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
GPIO_PortSet(base, mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||||
|
*
|
||||||
|
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||||
|
* @param mask GPIO pin number macro
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1))
|
||||||
|
base->DR_CLEAR = mask;
|
||||||
|
#else
|
||||||
|
base->DR &= ~mask;
|
||||||
|
#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
GPIO_PortClear(base, mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reverses the current output logic of the multiple GPIO pins.
|
||||||
|
*
|
||||||
|
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||||
|
* @param mask GPIO pin number macro
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
|
||||||
|
base->DR_TOGGLE = mask;
|
||||||
|
#else
|
||||||
|
base->DR ^= mask;
|
||||||
|
#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads the current input value of the GPIO port.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param pin GPIO port pin number.
|
||||||
|
* @retval GPIO port input value.
|
||||||
|
*/
|
||||||
|
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
|
||||||
|
{
|
||||||
|
assert(pin < 32U);
|
||||||
|
|
||||||
|
return (((base->DR) >> pin) & 0x1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads the current input value of the GPIO port.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead.
|
||||||
|
*/
|
||||||
|
static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
|
||||||
|
{
|
||||||
|
return GPIO_PinRead(base, pin);
|
||||||
|
}
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name GPIO Reads Pad Status Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads the current GPIO pin pad status.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param pin GPIO port pin number.
|
||||||
|
* @retval GPIO pin pad status value.
|
||||||
|
*/
|
||||||
|
static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
|
||||||
|
{
|
||||||
|
assert(pin < 32U);
|
||||||
|
|
||||||
|
return (uint8_t)(((base->PSR) >> pin) & 0x1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads the current GPIO pin pad status.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus.
|
||||||
|
*/
|
||||||
|
static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)
|
||||||
|
{
|
||||||
|
return GPIO_PinReadPadStatus(base, pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Interrupts and flags management functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the current pin interrupt mode.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param pin GPIO port pin number.
|
||||||
|
* @param pinInterruptMode pointer to a @ref gpio_interrupt_mode_t structure
|
||||||
|
* that contains the interrupt mode information.
|
||||||
|
*/
|
||||||
|
void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the current pin interrupt mode.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
|
||||||
|
{
|
||||||
|
GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables the specific pin interrupt.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param mask GPIO pin number macro.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
base->IMR |= mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables the specific pin interrupt.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param mask GPIO pin number macro.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
GPIO_PortEnableInterrupts(base, mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables the specific pin interrupt.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param mask GPIO pin number macro.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
base->IMR &= ~mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables the specific pin interrupt.
|
||||||
|
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
GPIO_PortDisableInterrupts(base, mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads individual pin interrupt status.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @retval current pin interrupt status flag.
|
||||||
|
*/
|
||||||
|
static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
|
||||||
|
{
|
||||||
|
return base->ISR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Reads individual pin interrupt status.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @retval current pin interrupt status flag.
|
||||||
|
*/
|
||||||
|
static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
|
||||||
|
{
|
||||||
|
return GPIO_PortGetInterruptFlags(base);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Clears pin interrupt flag. Status flags are cleared by
|
||||||
|
* writing a 1 to the corresponding bit position.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param mask GPIO pin number macro.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
base->ISR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Clears pin interrupt flag. Status flags are cleared by
|
||||||
|
* writing a 1 to the corresponding bit position.
|
||||||
|
*
|
||||||
|
* @param base GPIO base pointer.
|
||||||
|
* @param mask GPIO pin number macro.
|
||||||
|
*/
|
||||||
|
static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||||
|
{
|
||||||
|
GPIO_PortClearInterruptFlags(base, mask);
|
||||||
|
}
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* _FSL_GPIO_H_*/
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,873 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file fsl_pmu.c
|
||||||
|
* @brief support imxrt1176-sbc pmu
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: fsl_pmu.c
|
||||||
|
Description: support imxrt1176-sbc pmu
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#ifndef _FSL_PMU_H_
|
||||||
|
#define _FSL_PMU_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup pmu
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @name Driver version
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*! @brief PMU driver version */
|
||||||
|
#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
|
||||||
|
#define PMU_HAS_FBB (1U)
|
||||||
|
#else
|
||||||
|
#define PMU_HAS_FBB (0U)
|
||||||
|
#endif /* ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK */
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief System setpoints enumeration.
|
||||||
|
*/
|
||||||
|
enum _pmu_setpoint_map
|
||||||
|
{
|
||||||
|
kPMU_SetPoint0 = 1UL << 0UL, /*!< Set point 0. */
|
||||||
|
kPMU_SetPoint1 = 1UL << 1UL, /*!< Set point 1. */
|
||||||
|
kPMU_SetPoint2 = 1UL << 2UL, /*!< Set point 2. */
|
||||||
|
kPMU_SetPoint3 = 1UL << 3UL, /*!< Set point 3. */
|
||||||
|
kPMU_SetPoint4 = 1UL << 4UL, /*!< Set point 4. */
|
||||||
|
kPMU_SetPoint5 = 1UL << 5UL, /*!< Set point 5. */
|
||||||
|
kPMU_SetPoint6 = 1UL << 6UL, /*!< Set point 6. */
|
||||||
|
kPMU_SetPoint7 = 1UL << 7UL, /*!< Set point 7. */
|
||||||
|
kPMU_SetPoint8 = 1UL << 8UL, /*!< Set point 8. */
|
||||||
|
kPMU_SetPoint9 = 1UL << 9UL, /*!< Set point 9. */
|
||||||
|
kPMU_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */
|
||||||
|
kPMU_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */
|
||||||
|
kPMU_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */
|
||||||
|
kPMU_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */
|
||||||
|
kPMU_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */
|
||||||
|
kPMU_SetPoint15 = 1UL << 15UL /*!< Set point 15. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The name of LDOs
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_ldo_name
|
||||||
|
{
|
||||||
|
kPMU_PllLdo = 0U, /*!< The PLL LDO in SOC domain. */
|
||||||
|
kPMU_LpsrAnaLdo = 1U, /*!< The LPSR ANA LDO in LPSR domain. */
|
||||||
|
kPMU_LpsrDigLdo = 2U, /*!< The LPSR DIG LDO in LPSR domain. */
|
||||||
|
kPMU_SnvsDigLdo = 3U /*!< The SNVS DIG LDO in SNVS domain. */
|
||||||
|
} pmu_ldo_name_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The name of body bias.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_body_bias_name
|
||||||
|
{
|
||||||
|
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
|
||||||
|
kPMU_FBB_CM7 = 0x0U, /*!< The FBB implemented in Cortex-M7 Platform. */
|
||||||
|
kPMU_RBB_SOC = 0x1U, /*!< The RBB implemented in SOC. */
|
||||||
|
kPMU_RBB_LPSR = 0x2U, /*!< The RBB implemented in LPSRMIX. */
|
||||||
|
#else
|
||||||
|
kPMU_RBB_SOC = 0x0U, /*!< The RBB implemented in SOC. */
|
||||||
|
kPMU_RBB_LPSR = 0x1U, /*!< The RBB implemented in LPSRMIX. */
|
||||||
|
#endif /* PMU_HAS_FBB */
|
||||||
|
} pmu_body_bias_name_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The control mode of LDOs/Bandgaps/Body Bias.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_control_mode
|
||||||
|
{
|
||||||
|
kPMU_StaticMode = 0U, /*!< Static/Software Control mode. */
|
||||||
|
kPMU_GPCMode = 1U, /*!< GPC/Hardware Control mode. */
|
||||||
|
} pmu_control_mode_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The operation mode for the LDOs.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_ldo_operate_mode
|
||||||
|
{
|
||||||
|
kPMU_LowPowerMode = 0x0U, /*!< LDOs operate in Low power mode. */
|
||||||
|
kPMU_HighPowerMode = 0x1U, /*!< LDOs operate in High power mode. */
|
||||||
|
} pmu_ldo_operate_mode_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of LPSR ANA LDO's charge pump current.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_lpsr_ana_ldo_charge_pump_current
|
||||||
|
{
|
||||||
|
kPMU_LpsrAnaChargePump300nA = 0U, /*!< The current of the charge pump is selected as 300nA. */
|
||||||
|
kPMU_LpsrAnaChargePump400nA = 1U, /*!< The current of the charge pump is selected as 400nA. */
|
||||||
|
kPMU_LpsrAnaChargePump500nA = 2U, /*!< The current of the charge pump is selected as 500nA. */
|
||||||
|
kPMU_LpsrAnaChargePump600nA = 3U, /*!< The current of the charge pump is selected as 600nA. */
|
||||||
|
} pmu_lpsr_ana_ldo_charge_pump_current_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of LPSR ANA LDO's output range.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_lpsr_ana_ldo_output_range
|
||||||
|
{
|
||||||
|
kPMU_LpsrAnaLdoOutputFrom1P77To1P83 = 0U, /*!< The output voltage varies from 1.77V to 1.83V. */
|
||||||
|
kPMU_LpsrAnaLdoOutputFrom1P72To1P77 = 1U, /*!< The output voltage varies from 1.72V to 1.77V. */
|
||||||
|
kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, /*!< The output voltage varies from 1.82V to 1.88V. */
|
||||||
|
} pmu_lpsr_ana_ldo_output_range_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of voltage step time for LPSR DIG LDO.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_lpsr_dig_voltage_step_time
|
||||||
|
{
|
||||||
|
kPMU_LpsrDigVoltageStepInc15us = 0x0U, /*!< LPSR DIG LDO voltage step time selected as 15us. */
|
||||||
|
kPMU_LpsrDigVoltageStepInc25us = 0x1U, /*!< LPSR DIG LDO voltage step time selected as 25us. */
|
||||||
|
kPMU_LpsrDigVoltageStepInc50us = 0x2U, /*!< LPSR DIG LDO voltage step time selected as 50us. */
|
||||||
|
kPMU_LpsrDigVoltageStepInc100us = 0x3U, /*!< LPSR DIG LDO voltage step time selected as 100us. */
|
||||||
|
} pmu_lpsr_dig_voltage_step_time_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The target output voltage of LPSR DIG LDO.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_lpsr_dig_target_output_voltage
|
||||||
|
{
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U, /*!< The target voltage selected as 0.631V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P65V = 0x1U, /*!< The target voltage selected as 0.65V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P67V = 0x2U, /*!< The target voltage selected as 0.67V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U, /*!< The target voltage selected as 0.689V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U, /*!< The target voltage selected as 0.709V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U, /*!< The target voltage selected as 0.728V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U, /*!< The target voltage selected as 0.748V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P767V = 0x7U, /*!< The target voltage selected as 0.767V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P786V = 0x8U, /*!< The target voltage selected as 0.786V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P806V = 0x9U, /*!< The target voltage selected as 0.806V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P825V = 0xAU, /*!< The target voltage selected as 0.825V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P845V = 0xBU, /*!< The target voltage selected as 0.845V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P864V = 0xCU, /*!< The target voltage selected as 0.864V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P883V = 0xDU, /*!< The target voltage selected as 0.883V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P903V = 0xEU, /*!< The target voltage selected as 0.903V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P922V = 0xFU, /*!< The target voltage selected as 0.922V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P942V = 0x10U, /*!< The target voltage selected as 0.942V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P961V = 0x11U, /*!< The target voltage selected as 0.961V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage0P981V = 0x12U, /*!< The target voltage selected as 0.981V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P0V = 0x13U, /*!< The target voltage selected as 1.0V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P019V = 0x14U, /*!< The target voltage selected as 1.019V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P039V = 0x15U, /*!< The target voltage selected as 1.039V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P058V = 0x16U, /*!< The target voltage selected as 1.058V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P078V = 0x17U, /*!< The target voltage selected as 1.078V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, /*!< The target voltage selected as 1.097V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, /*!< The target voltage selected as 1.117V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, /*!< The target voltage selected as 1.136V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, /*!< The target voltage selected as 1.155V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, /*!< The target voltage selected as 1.175V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, /*!< The target voltage selected as 1.194V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, /*!< The target voltage selected as 1.214V */
|
||||||
|
kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, /*!< The target voltage selected as 1.233V */
|
||||||
|
} pmu_lpsr_dig_target_output_voltage_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of the SNVS DIG LDO's charge pump current.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_snvs_dig_charge_pump_current
|
||||||
|
{
|
||||||
|
kPMU_SnvsDigChargePump12P5nA = 0U, /*!< The current of SNVS DIG LDO's charge pump is selected as 12.5nA. */
|
||||||
|
kPMU_SnvsDigChargePump6P25nA = 1U, /*!< The current of SNVS DIG LDO's charge pump is selected as 6.25nA. */
|
||||||
|
kPMU_SnvsDigChargePump18P75nA = 2U, /*!< The current of SNVS DIG LDO's charge pump is selected as 18.75nA. */
|
||||||
|
} pmu_snvs_dig_charge_pump_current_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of the SNVS DIG LDO's discharge resistor.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_snvs_dig_discharge_resistor_value
|
||||||
|
{
|
||||||
|
kPMU_SnvsDigDischargeResistor15K = 0U, /*!< The Discharge Resistor is selected as 15K ohm */
|
||||||
|
kPMU_SnvsDigDischargeResistor30K = 1U, /*!< The Discharge Resistor is selected as 30K ohm */
|
||||||
|
kPMU_SnvsDigDischargeResistor9K = 2U, /*!< The Discharge Resistor is selected as 9K ohm */
|
||||||
|
} pmu_snvs_dig_discharge_resistor_value_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of bandgap power down option.
|
||||||
|
*/
|
||||||
|
enum _pmu_static_bandgap_power_down_option
|
||||||
|
{
|
||||||
|
kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */
|
||||||
|
kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, /*!< Power down only the reference output
|
||||||
|
section of the bandgap */
|
||||||
|
kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without
|
||||||
|
affecting any additional functionality. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of output VBG voltage.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_bandgap_output_VBG_voltage_value
|
||||||
|
{
|
||||||
|
kPMU_BandgapOutputVBGVoltageNominal = 0x0U, /*!< Output nominal voltage. */
|
||||||
|
kPMU_BandgapOutputVBGVoltagePlus10mV = 0x1U, /*!< Output VBG voltage Plus 10mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltagePlus20mV = 0x2U, /*!< Output VBG voltage Plus 20mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltagePlus30mV = 0x3U, /*!< Output VBG voltage Plus 30mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltageMinus10mV = 0x4U, /*!< Output VBG voltage Minus 10mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltageMinus20mV = 0x5U, /*!< Output VBG voltage Minus 20mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltageMinus30mV = 0x6U, /*!< Output VBG voltage Minus 30mV. */
|
||||||
|
kPMU_BandgapOutputVBGVoltageMinus40mV = 0x7U, /*!< Output VBG voltage Minus 40mV. */
|
||||||
|
} pmu_bandgap_output_VBG_voltage_value_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumeration of output current.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_bandgap_output_current_value
|
||||||
|
{
|
||||||
|
kPMU_OutputCurrent11P5uA = 0x0U, /*!< Output 11.5uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent11P8uA = 0x1U, /*!< Output 11.8uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent12P1uA = 0x2U, /*!< Output 12.1uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent12P4uA = 0x4U, /*!< Output 12.4uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent12P7uA = 0x5U, /*!< Output 12.7uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent13P0uA = 0x6U, /*!< Output 13.0uA current from the bandgap. */
|
||||||
|
kPMU_OutputCurrent13P3uA = 0x7U, /*!< Output 13.3uA current from the bandgap. */
|
||||||
|
} pmu_bandgap_output_current_value_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of well bias power source.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_well_bias_power_source
|
||||||
|
{
|
||||||
|
kPMU_WellBiasPowerFromLpsrDigLdo = 0U, /*!< LPSR Dig LDO supplies the power stage and NWELL sampler. */
|
||||||
|
kPMU_WellBiasPowerFromDCDC, /*!< DCDC supplies the power stage and NWELL sampler. */
|
||||||
|
} pmu_well_bias_power_source_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of bias area size.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_bias_area_size
|
||||||
|
{
|
||||||
|
kPMU_180uA_6mm2At125C = 0U, /*!< Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C */
|
||||||
|
kPMU_150uA_5mm2At125C, /*!< Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C */
|
||||||
|
kPMU_120uA_4mm2At125C, /*!< Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C */
|
||||||
|
kPMU_90uA_3mm2At125C, /*!< Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C */
|
||||||
|
kPMU_60uA_2mm2At125C, /*!< Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C */
|
||||||
|
kPMU_45uA_1P5mm2At125C, /*!< Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C */
|
||||||
|
kPMU_30uA_1mm2At125C, /*!< Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C */
|
||||||
|
kPMU_15uA_0P5mm2At125C, /*!< Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C */
|
||||||
|
} pmu_bias_area_size_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of well bias typical frequency.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_well_bias_typical_freq
|
||||||
|
{
|
||||||
|
kPMU_OscFreqDiv128 = 0U, /*!< Typical frequency = osc_freq / 128. */
|
||||||
|
kPMU_OscFreqDiv64 = 1U, /*!< Typical frequency = osc_freq / 64. */
|
||||||
|
kPMU_OscFreqDiv32 = 2U, /*!< Typical frequency = osc_freq / 32. */
|
||||||
|
kPMU_OscFreqDiv16 = 3U, /*!< Typical frequency = osc_freq / 16. */
|
||||||
|
kPMU_OscFreqDiv8 = 4U, /*!< Typical frequency = osc_freq / 8. */
|
||||||
|
kPMU_OscFreqDiv2 = 6U, /*!< Typical frequency = osc_freq / 2. */
|
||||||
|
kPMU_OscFreq = 7U, /*!< Typical frequency = oscillator frequency. */
|
||||||
|
} pmu_well_bias_typical_freq_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of well bias adaptive clock source.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_adaptive_clock_source
|
||||||
|
{
|
||||||
|
kPMU_AdaptiveClkSourceOscClk = 0U, /*!< The adaptive clock source is oscillator clock. */
|
||||||
|
kPMU_AdaptiveClkSourceChargePumpClk, /*!< The adaptive clock source is charge pump clock. */
|
||||||
|
} pmu_adaptive_clock_source_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of frequency reduction due to cap increment.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_freq_reduction
|
||||||
|
{
|
||||||
|
kPMU_FreqReductionNone = 0U, /*!< No frequency reduction. */
|
||||||
|
kPMU_FreqReduction30PCT, /*!< 30% frequency reduction due to cap increment. */
|
||||||
|
kPMU_FreqReduction40PCT, /*!< 40% frequency reduction due to cap increment. */
|
||||||
|
kPMU_FreqReduction50PCT, /*!< 50% frequency reduction due to cap increment. */
|
||||||
|
} pmu_freq_reduction_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The enumerator of well bias 1P8 adjustment.
|
||||||
|
*/
|
||||||
|
typedef enum _pmu_well_bias_1P8_adjustment
|
||||||
|
{
|
||||||
|
kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, /*!< Cref = 0fF, Cspl = 0fF, DeltaC = 0fF. */
|
||||||
|
kPMU_Cref0fFCspl30fFDeltaCN30fF, /*!< Cref = 0fF, Cspl = 30fF, DeltaC = -30fF. */
|
||||||
|
kPMU_Cref0fFCspl43fFDeltaCN43fF, /*!< Cref = 0fF, Cspl = 43fF, DeltaC = -43fF. */
|
||||||
|
kPMU_Cref0fFCspl62fFDeltaCN62fF, /*!< Cref = 0fF, Cspl = 62fF, DeltaC = -62fF. */
|
||||||
|
kPMU_Cref0fFCspl105fFDeltaCN105fF, /*!< Cref = 0fF, Cspl = 105fF, DeltaC = -105fF. */
|
||||||
|
kPMU_Cref30fFCspl0fFDeltaC30fF, /*!< Cref = 30fF, Cspl = 0fF, DeltaC = 30fF. */
|
||||||
|
kPMU_Cref30fFCspl43fFDeltaCN12fF, /*!< Cref = 30fF, Cspl = 43fF, DeltaC = -12fF. */
|
||||||
|
kPMU_Cref30fFCspl105fFDeltaCN75fF, /*!< Cref = 30fF, Cspl = 105fF, DeltaC = -75fF. */
|
||||||
|
kPMU_Cref43fFCspl0fFDeltaC43fF, /*!< Cref = 43fF, Cspl = 0fF, DeltaC = 43fF. */
|
||||||
|
kPMU_Cref43fFCspl30fFDeltaC13fF, /*!< Cref = 43fF, Cspl = 30fF, DeltaC = 13fF. */
|
||||||
|
kPMU_Cref43fFCspl62fFDeltaCN19fF, /*!< Cref = 43fF, Cspl = 62fF, DeltaC = -19fF. */
|
||||||
|
kPMU_Cref62fFCspl0fFDeltaC62fF, /*!< Cref = 62fF, Cspl = 0fF, DeltaC = 62fF. */
|
||||||
|
kPMU_Cref62fFCspl43fFDeltaC19fF, /*!< Cref = 62fF, Cspl = 43fF, DeltaC = 19fF. */
|
||||||
|
kPMU_Cref105fFCspl0fFDeltaC105fF, /*!< Cref = 105fF, Cspl = 0fF, DeltaC = 105fF. */
|
||||||
|
kPMU_Cref105fFCspl30fFDeltaC75fF, /*!< Cref = 105fF, Cspl = 30fF, DeltaC = 75fF. */
|
||||||
|
} pmu_well_bias_1P8_adjustment_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief LPSR ANA LDO config.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_static_lpsr_ana_ldo_config
|
||||||
|
{
|
||||||
|
pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */
|
||||||
|
bool enable2mALoad; /*!< Enable/Disable 2mA load.
|
||||||
|
- \b true Enables 2mA loading to prevent overshoot;
|
||||||
|
- \b false Disables 2mA loading.*/
|
||||||
|
bool enable4mALoad; /*!< Enable/Disable 4mA load.
|
||||||
|
- \b true Enables 4mA loading to prevent dramatic voltage drop;
|
||||||
|
- \b false Disables 4mA load. */
|
||||||
|
bool enable20uALoad; /*!< Enable/Disable 20uA load.
|
||||||
|
- \b true Enables 20uA loading to prevent overshoot;
|
||||||
|
- \b false Disables 20uA load. */
|
||||||
|
bool enableStandbyMode; /*!< Enable/Disable Standby Mode.
|
||||||
|
- \b true Enables Standby mode, if the STBY assert, the LPSR ANA LDO enter LP mode
|
||||||
|
- \b false Disables Standby mode. */
|
||||||
|
} pmu_static_lpsr_ana_ldo_config_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief LPSR DIG LDO Config in Static/Software Mode.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_static_lpsr_dig_config
|
||||||
|
{
|
||||||
|
bool enableStableDetect; /*!< Enable/Disable Stable Detect.
|
||||||
|
- \b true Enables Stable Detect.
|
||||||
|
- \b false Disables Stable Detect. */
|
||||||
|
pmu_lpsr_dig_voltage_step_time_t voltageStepTime; /*!< Step time. */
|
||||||
|
pmu_lpsr_dig_target_output_voltage_t targetVoltage; /*!< The target output voltage. */
|
||||||
|
} pmu_static_lpsr_dig_config_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief SNVS DIG LDO config.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_snvs_dig_config
|
||||||
|
{
|
||||||
|
pmu_ldo_operate_mode_t mode; /*!< The operate mode the SNVS DIG LDO. */
|
||||||
|
pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; /*!< The current of SNVS DIG LDO's charge pump current. */
|
||||||
|
pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; /*!< The value of SNVS DIG LDO's
|
||||||
|
Discharge Resistor. */
|
||||||
|
uint8_t trimValue; /*!< The trim value. */
|
||||||
|
bool enablePullDown; /*!< Enable/Disable Pull down.
|
||||||
|
- \b true Enables the feature of using 1M ohm resistor to discharge the LDO output.
|
||||||
|
- \b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */
|
||||||
|
bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */
|
||||||
|
} pmu_snvs_dig_config_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Bandgap config in static mode.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_static_bandgap_config
|
||||||
|
{
|
||||||
|
uint8_t powerDownOption; /*!< The OR'ed value of @ref _pmu_static_bandgap_power_down_option. Please refer to @ref
|
||||||
|
_pmu_static_bandgap_power_down_option. */
|
||||||
|
bool enableLowPowerMode; /*!< Turn on/off the Low power mode.
|
||||||
|
- \b true Turns on the low power operation of the bandgap.
|
||||||
|
- \b false Turns off the low power operation of the bandgap. */
|
||||||
|
pmu_bandgap_output_VBG_voltage_value_t outputVoltage; /*!< The output VBG voltage of Bandgap. */
|
||||||
|
pmu_bandgap_output_current_value_t outputCurrent; /*!< The output current from the bandgap to
|
||||||
|
the temperature sensors. */
|
||||||
|
} pmu_static_bandgap_config_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The union of well bias basic options, such as clock source, power source and so on.
|
||||||
|
*/
|
||||||
|
typedef union _pmu_well_bias_option
|
||||||
|
{
|
||||||
|
uint16_t wellBiasData; /*!< well bias configuration data. */
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint16_t enablePWellOnly : 1U; /*!< Turn on both PWELL and NWELL, or only trun on PWELL.
|
||||||
|
- \b 1b0 PWELL and NEWLL are both turned on.
|
||||||
|
- \b 1b1 PWELL is turned on only. */
|
||||||
|
uint16_t reserved1 : 1U; /*!< Reserved. */
|
||||||
|
uint16_t biasAreaSize : 3U; /*!< Select size of bias area, please refer to @ref pmu_bias_area_size_t */
|
||||||
|
uint16_t disableAdaptiveFreq : 1U; /*!< Enable/Disable adaptive frequency.
|
||||||
|
- \b 1b0 Frequency change after each half cycle minimum frequency
|
||||||
|
determined by typical frequency.
|
||||||
|
- \b 1b1 Adaptive frequency disabled. Frequency determined by typical
|
||||||
|
frequency. */
|
||||||
|
uint16_t wellBiasFreq : 3U; /*!< Set well bias typical frequency, please refer to @ref
|
||||||
|
pmu_well_bias_typical_freq_t. */
|
||||||
|
uint16_t clkSource : 1U; /*!< Config the adaptive clock source, please @ref pmu_adaptive_clock_source_t. */
|
||||||
|
uint16_t freqReduction : 2U; /*!< Config the percent of frequency reduction due to cap increment,
|
||||||
|
please refer to @ref pmu_freq_reduction_t. */
|
||||||
|
uint16_t enablePowerDownOption : 1U; /*!< Enable/Disable pull down option.
|
||||||
|
- \b false Pull down option is disabled.
|
||||||
|
- \b true Pull down option is enabled. */
|
||||||
|
uint16_t reserved2 : 1U; /*!< Reserved. */
|
||||||
|
uint16_t powerSource : 1U; /*!< Set power source, please refer to @ref pmu_well_bias_power_source_t. */
|
||||||
|
uint16_t reserved3 : 1U; /*!< Reserved. */
|
||||||
|
} wellBiasStruct;
|
||||||
|
} pmu_well_bias_option_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The structure of well bias configuration.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_well_bias_config
|
||||||
|
{
|
||||||
|
pmu_well_bias_option_t wellBiasOption; /*!< Well bias basic function, please
|
||||||
|
refer to @ref pmu_well_bias_option_t. */
|
||||||
|
pmu_well_bias_1P8_adjustment_t adjustment; /*!< Well bias adjustment 1P8, please
|
||||||
|
refer to @ref pmu_well_bias_1P8_adjustment_t. */
|
||||||
|
} pmu_well_bias_config_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief The stucture of body bias config in GPC mode.
|
||||||
|
*/
|
||||||
|
typedef struct _pmu_gpc_body_bias_config
|
||||||
|
{
|
||||||
|
uint8_t PWELLRegulatorSize; /*!< The size of the PWELL Regulator. */
|
||||||
|
uint8_t NWELLRegulatorSize; /*!< The size of the NWELL Regulator. */
|
||||||
|
uint8_t oscillatorSize; /*!< The size of the oscillator bits. */
|
||||||
|
uint8_t regulatorStrength; /*!< The strength of the selected regulator. */
|
||||||
|
} pmu_gpc_body_bias_config_t;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name LDOs Control APIs
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Selects the control mode of the PLL LDO.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param mode The control mode of the PLL LDO. Please refer to @ref pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables PLL LDO via AI interface in Static/Software mode.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables PLL LDO via AI interface in Static/Software mode.
|
||||||
|
*/
|
||||||
|
void PMU_StaticDisablePllLdo(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Selects the control mode of the LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param mode The control mode of the LPSR ANA LDO. Please refer to @ref pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the Bypass mode of the LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @param enable Enable/Disable bypass mode.
|
||||||
|
* - \b true Enable LPSR ANA Bypass mode.
|
||||||
|
* - \b false Disable LPSR ANA Bypass mode.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Checks whether the LPSR ANA LDO is in bypass mode.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @return The result used to indicates whether the LPSR ANA LDO is in bypass mode.
|
||||||
|
* - \b true The LPSR ANA LDO is in bypass mode.
|
||||||
|
* - \b false The LPSR ANA LDO not in bypass mode.
|
||||||
|
*/
|
||||||
|
static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
|
||||||
|
{
|
||||||
|
return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Fill the LPSR ANA LDO configuration structure with default settings.
|
||||||
|
*
|
||||||
|
* The default values are:
|
||||||
|
* @code
|
||||||
|
* config->mode = kPMU_HighPowerMode;
|
||||||
|
config->enable2mALoad = true;
|
||||||
|
config->enable20uALoad = false;
|
||||||
|
config->enable4mALoad = true;
|
||||||
|
config->enableStandbyMode = false;
|
||||||
|
config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0;
|
||||||
|
config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable;
|
||||||
|
config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA;
|
||||||
|
config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83;
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initialize the LPSR ANA LDO in Static/Sofware Mode.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the output of LPSR ANA LDO.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Selects the control mode of the LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param mode The control mode of the LPSR DIG LDO. Please refer to @ref pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @param enable
|
||||||
|
* - \b true Turns on Bypass mode of the LPSR DIG LDO.
|
||||||
|
* - \b false Turns off Bypass mode of the LPSR DIG LDO.
|
||||||
|
*/
|
||||||
|
void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Checks whether the LPSR DIG LDO is in bypass mode.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @return The result used to indicates whether the LPSR DIG LDO is in bypass mode.
|
||||||
|
* - \b true The LPSR DIG LDO is in bypass mode.
|
||||||
|
* - \b false The LPSR DIG LDO not in bypass mode.
|
||||||
|
*/
|
||||||
|
static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
|
||||||
|
{
|
||||||
|
return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the default configuration of LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* The default values are:
|
||||||
|
* @code
|
||||||
|
* config->enableStableDetect = false;
|
||||||
|
* config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us;
|
||||||
|
* config->brownOutConfig = kPMU_LpsrDigBrownOutDisable;
|
||||||
|
* config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V;
|
||||||
|
* config->mode = kPMU_HighPowerMode;
|
||||||
|
* @endcode
|
||||||
|
* @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initialize the LPSR DIG LDO in static mode.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
* @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the LPSR DIG LDO.
|
||||||
|
*
|
||||||
|
* @param base ANADIG_LDO_SNVS peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the voltage step of LPSR DIG LDO in certain setpoint during GPC mode.
|
||||||
|
*
|
||||||
|
* @note The function provides the feature to set the voltage step to different setpoints.
|
||||||
|
*
|
||||||
|
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
* @param voltageValue The voltage step to be set. See enumeration @ref pmu_lpsr_dig_target_output_voltage_t.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the default config of the SNVS DIG LDO.
|
||||||
|
*
|
||||||
|
* The default values are:
|
||||||
|
* @code
|
||||||
|
* config->mode = kPMU_LowPowerMode;
|
||||||
|
* config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA;
|
||||||
|
* config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K;
|
||||||
|
* config->trimValue = 0U;
|
||||||
|
* config->enablePullDown = true;
|
||||||
|
* config->enableLdoStable = false;
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* @param config Pointer to @ref pmu_snvs_dig_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initialize the SNVS DIG LDO.
|
||||||
|
*
|
||||||
|
* @param base LDO SNVS DIG peripheral base address.
|
||||||
|
* @param mode Used to control LDO power mode, please refer to @ref pmu_ldo_operate_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable SNVS DIG LDO.
|
||||||
|
*/
|
||||||
|
static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base)
|
||||||
|
{
|
||||||
|
base->PMU_LDO_SNVS_DIG &= ~ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1
|
||||||
|
* means enable specific ldo in that setpoint.
|
||||||
|
* For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable
|
||||||
|
* PLL LDO in other setpoint.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the operating mode of the selected LDO in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
* @param mode The operating mode of the selected ldo. Please refer to enumeration @ref pmu_ldo_operate_mode_t for
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the selected LDOs' Tracking mode in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the selected LDOs' Bypass mode in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief When STBY assert, enable/disable the selected LDO enter it's Low power mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY
|
||||||
|
* assert, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Bandgap Control APIs
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Selects the control mode of the Bandgap Reference.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param mode The control mode of the Bandgap Reference. Please refer to @ref pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
*/
|
||||||
|
void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disables Bandgap self bias for best noise performance.
|
||||||
|
*
|
||||||
|
* This function should be invoked after powering up. This function will wait for the bandgap stable and disable the
|
||||||
|
* bandgap self bias. After powering up, it need to wait for the bandgap to get stable and then disable Bandgap Self
|
||||||
|
* bias for best noise performance.
|
||||||
|
*/
|
||||||
|
void PMU_DisableBandgapSelfBiasAfterPowerUp(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables Bandgap self bias before power down.
|
||||||
|
*
|
||||||
|
* This function will enable Bandgap self bias feature before powering down or there
|
||||||
|
* will be risk of Bandgap not starting properly.
|
||||||
|
*/
|
||||||
|
void PMU_EnableBandgapSelfBiasBeforePowerDown(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initialize Bandgap.
|
||||||
|
*
|
||||||
|
* @param config Pointer to the structure @ref pmu_static_bandgap_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in
|
||||||
|
* setpoint0 and setpoint1 and disable bandgap in other setpoints.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param setpointMap The map of setpoints that the bandgap will be enabled in those setpoints, this parameter
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
base->BANDGAP_ENABLE_SP = ~setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the Bandgap's Standby mode in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param setpointMap The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap)
|
||||||
|
{
|
||||||
|
base->BANDGAP_STBY_EN_SP = setpointMap;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Body Bias Control APIs
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Configures Well bias, such as power source, clock source and so on.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param config Pointer to the @ref pmu_well_bias_config_t structure.
|
||||||
|
*/
|
||||||
|
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the default configuration of well bias.
|
||||||
|
*
|
||||||
|
* @param config The pointer to the @ref pmu_well_bias_config_t structure.
|
||||||
|
*/
|
||||||
|
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Selects the control mode of the Body Bias.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t.
|
||||||
|
* @param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t.
|
||||||
|
*/
|
||||||
|
void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables/disables the selected body bias.
|
||||||
|
*
|
||||||
|
* @param base PMU peripheral base address.
|
||||||
|
* @param name The name of the body bias to be turned on/off, please refer to @ref pmu_body_bias_name_t.
|
||||||
|
* @param enable Used to turn on/off the specific body bias.
|
||||||
|
* - \b true Enable the selected body bias.
|
||||||
|
* - \b false Disable the selected body bias.
|
||||||
|
*/
|
||||||
|
void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
|
||||||
|
* should be the OR'ed Value of _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Controls the ON/OFF of the selected Body Bias' Wbias power switch in certain setpoints with GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
|
||||||
|
* @param setpointMap The map of setpoints that the specific body bias's wbias power switch will be turn on in those
|
||||||
|
* setpoints, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
|
||||||
|
*/
|
||||||
|
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the default config of body bias in GPC mode.
|
||||||
|
*
|
||||||
|
* @param config Pointer to structure @ref pmu_gpc_body_bias_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Sets the config of the selected Body Bias in GPC mode.
|
||||||
|
*
|
||||||
|
* @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details.
|
||||||
|
* @param config Pointer to structure @ref pmu_gpc_body_bias_config_t.
|
||||||
|
*/
|
||||||
|
void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/*!
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* _FSL_PMU_H_ */
|
||||||
|
|
@ -0,0 +1,138 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Processors: MIMXRT1176AVM8A_cm4
|
||||||
|
** MIMXRT1176CVM8A_cm4
|
||||||
|
** MIMXRT1176DVMAA_cm4
|
||||||
|
**
|
||||||
|
** Compilers: Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
** Keil ARM C/C++ Compiler
|
||||||
|
** MCUXpresso Compiler
|
||||||
|
**
|
||||||
|
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210615
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Provides a system configuration function and a global variable that
|
||||||
|
** contains the system frequency. It configures the device and initializes
|
||||||
|
** the oscillator (PLL) that is part of the microcontroller device.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update header files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file system_MIMXRT1176_cm4.h
|
||||||
|
* @brief support imxrt1176-sbc cm4 core system init
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: system_MIMXRT1176_cm4.h
|
||||||
|
Description: support imxrt1176-sbc cm4 system init
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @file MIMXRT1176_cm4
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021-06-15
|
||||||
|
* @brief Device specific configuration file for MIMXRT1176_cm4 (header file)
|
||||||
|
*
|
||||||
|
* Provides a system configuration function and a global variable that contains
|
||||||
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
|
* (PLL) that is part of the microcontroller device.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SYSTEM_MIMXRT1176_cm4_H_
|
||||||
|
#define _SYSTEM_MIMXRT1176_cm4_H_ /**< Symbol preventing repeated inclusion */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef DISABLE_WDOG
|
||||||
|
#define DISABLE_WDOG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Define clock source values */
|
||||||
|
|
||||||
|
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||||
|
|
||||||
|
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
|
||||||
|
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
|
||||||
|
|
||||||
|
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System clock frequency (core clock)
|
||||||
|
*
|
||||||
|
* The system clock frequency supplied to the SysTick timer and the processor
|
||||||
|
* core clock. This variable can be used by the user application to setup the
|
||||||
|
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||||
|
* query the frequency of the debug timer or configure the trace clock speed
|
||||||
|
* SystemCoreClock is initialized with a correct predefined value.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
*
|
||||||
|
* Typically this function configures the oscillator (PLL) that is part of the
|
||||||
|
* microcontroller device. For systems with variable clock speed it also updates
|
||||||
|
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||||
|
*/
|
||||||
|
void SystemInit (void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Updates the SystemCoreClock variable.
|
||||||
|
*
|
||||||
|
* It must be called whenever the core clock is changed during program
|
||||||
|
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||||
|
* the current core clock.
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate (void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SystemInit function hook.
|
||||||
|
*
|
||||||
|
* This weak function allows to call specific initialization code during the
|
||||||
|
* SystemInit() execution.This can be used when an application specific code needs
|
||||||
|
* to be called as close to the reset entry as possible (for example the Multicore
|
||||||
|
* Manager MCMGR_EarlyInit() function call).
|
||||||
|
* NOTE: No global r/w variables can be used in this hook function because the
|
||||||
|
* initialization of these variables happens after this function.
|
||||||
|
*/
|
||||||
|
void SystemInitHook (void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _SYSTEM_MIMXRT1176_cm4_H_ */
|
||||||
|
|
@ -0,0 +1,138 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Processors: MIMXRT1176AVM8A_cm7
|
||||||
|
** MIMXRT1176CVM8A_cm7
|
||||||
|
** MIMXRT1176DVMAA_cm7
|
||||||
|
**
|
||||||
|
** Compilers: Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
** Keil ARM C/C++ Compiler
|
||||||
|
** MCUXpresso Compiler
|
||||||
|
**
|
||||||
|
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||||
|
** Version: rev. 1.0, 2020-12-29
|
||||||
|
** Build: b210615
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Provides a system configuration function and a global variable that
|
||||||
|
** contains the system frequency. It configures the device and initializes
|
||||||
|
** the oscillator (PLL) that is part of the microcontroller device.
|
||||||
|
**
|
||||||
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||||
|
** Copyright 2016-2021 NXP
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
**
|
||||||
|
** http: www.nxp.com
|
||||||
|
** mail: support@nxp.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 0.1 (2018-03-05)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.0 (2020-12-29)
|
||||||
|
** Update header files to align with IMXRT1170RM Rev.0.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @file system_MIMXRT1176_cm7.h
|
||||||
|
* @brief support imxrt1176-sbc cm7 core system init
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2022-08-19
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: system_MIMXRT1176_cm7.h
|
||||||
|
Description: support imxrt1176-sbc cm7 system init
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @file MIMXRT1176_cm7
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021-06-15
|
||||||
|
* @brief Device specific configuration file for MIMXRT1176_cm7 (header file)
|
||||||
|
*
|
||||||
|
* Provides a system configuration function and a global variable that contains
|
||||||
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
|
* (PLL) that is part of the microcontroller device.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SYSTEM_MIMXRT1176_cm7_H_
|
||||||
|
#define _SYSTEM_MIMXRT1176_cm7_H_ /**< Symbol preventing repeated inclusion */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef DISABLE_WDOG
|
||||||
|
#define DISABLE_WDOG 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Define clock source values */
|
||||||
|
|
||||||
|
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||||
|
|
||||||
|
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
|
||||||
|
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
|
||||||
|
|
||||||
|
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System clock frequency (core clock)
|
||||||
|
*
|
||||||
|
* The system clock frequency supplied to the SysTick timer and the processor
|
||||||
|
* core clock. This variable can be used by the user application to setup the
|
||||||
|
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||||
|
* query the frequency of the debug timer or configure the trace clock speed
|
||||||
|
* SystemCoreClock is initialized with a correct predefined value.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
*
|
||||||
|
* Typically this function configures the oscillator (PLL) that is part of the
|
||||||
|
* microcontroller device. For systems with variable clock speed it also updates
|
||||||
|
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||||
|
*/
|
||||||
|
void SystemInit (void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Updates the SystemCoreClock variable.
|
||||||
|
*
|
||||||
|
* It must be called whenever the core clock is changed during program
|
||||||
|
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||||
|
* the current core clock.
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate (void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SystemInit function hook.
|
||||||
|
*
|
||||||
|
* This weak function allows to call specific initialization code during the
|
||||||
|
* SystemInit() execution.This can be used when an application specific code needs
|
||||||
|
* to be called as close to the reset entry as possible (for example the Multicore
|
||||||
|
* Manager MCMGR_EarlyInit() function call).
|
||||||
|
* NOTE: No global r/w variables can be used in this hook function because the
|
||||||
|
* initialization of these variables happens after this function.
|
||||||
|
*/
|
||||||
|
void SystemInitHook (void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _SYSTEM_MIMXRT1176_cm7_H_ */
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
config BSP_USING_LPUART1
|
||||||
|
bool "Enable LPUART1"
|
||||||
|
default y
|
||||||
|
if BSP_USING_LPUART1
|
||||||
|
config SERIAL_BUS_NAME_1
|
||||||
|
string "serial bus 1 name"
|
||||||
|
default "uart1"
|
||||||
|
config SERIAL_DRV_NAME_1
|
||||||
|
string "serial bus 1 driver name"
|
||||||
|
default "uart1_drv"
|
||||||
|
config SERIAL_1_DEVICE_NAME_0
|
||||||
|
string "serial bus 1 device name"
|
||||||
|
default "uart1_dev1"
|
||||||
|
endif
|
||||||
|
|
||||||
|
config BSP_USING_LPUART2
|
||||||
|
bool "Enable LPUART2"
|
||||||
|
default y
|
||||||
|
if BSP_USING_LPUART2
|
||||||
|
config SERIAL_BUS_NAME_2
|
||||||
|
string "serial bus 2 name"
|
||||||
|
default "uart2"
|
||||||
|
config SERIAL_DRV_NAME_2
|
||||||
|
string "serial bus 2 driver name"
|
||||||
|
default "uart2_drv"
|
||||||
|
config SERIAL_2_DEVICE_NAME_0
|
||||||
|
string "serial bus 2 device name"
|
||||||
|
default "uart2_dev2"
|
||||||
|
endif
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
SRC_FILES := connect_uart.c fsl_lpuart.c
|
||||||
|
|
||||||
|
include $(KERNEL_ROOT)/compiler.mk
|
||||||
|
|
@ -0,0 +1,410 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file connect_uart.c
|
||||||
|
* @brief support imxrt1176-sbc board uart function and register to bus framework
|
||||||
|
* @version 1.0
|
||||||
|
* @author AIIT XUOS Lab
|
||||||
|
* @date 2021-05-28
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
File name: connect_uart.c
|
||||||
|
Description: support imxrt1176-sbc board uart configure and uart bus register function
|
||||||
|
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
|
||||||
|
History:
|
||||||
|
1. Date: 2022-08-19
|
||||||
|
Author: AIIT XUOS Lab
|
||||||
|
Modification:
|
||||||
|
1. support imxrt1176-sbc board uart configure, write and read
|
||||||
|
2. support imxrt1176-sbc board uart bus device and driver register
|
||||||
|
*************************************************/
|
||||||
|
|
||||||
|
#include <board.h>
|
||||||
|
#include <connect_uart.h>
|
||||||
|
#include <fsl_lpuart.h>
|
||||||
|
|
||||||
|
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev);
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART1
|
||||||
|
struct SerialBus serial_bus_1;
|
||||||
|
struct SerialDriver serial_driver_1;
|
||||||
|
struct SerialHardwareDevice serial_device_1;
|
||||||
|
|
||||||
|
void LPUART1_IRQHandler(int irqn, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
// KPrintf("LPUART1_IRQHandler \n");
|
||||||
|
lock = DisableIRQ(UART1_IRQn);
|
||||||
|
UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1);
|
||||||
|
EnableIRQ(UART1_IRQn);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(UART1_IRQn, LPUART1_IRQHandler, NONE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART2
|
||||||
|
struct SerialBus serial_bus_2;
|
||||||
|
struct SerialDriver serial_driver_2;
|
||||||
|
struct SerialHardwareDevice serial_device_2;
|
||||||
|
|
||||||
|
void LPUART2_IRQHandler(int irqn, void *arg)
|
||||||
|
{
|
||||||
|
x_base lock = 0;
|
||||||
|
lock = DISABLE_INTERRUPT();
|
||||||
|
|
||||||
|
UartIsr(&serial_bus_2, &serial_driver_2, &serial_device_2);
|
||||||
|
|
||||||
|
ENABLE_INTERRUPT(lock);
|
||||||
|
}
|
||||||
|
DECLARE_HW_IRQ(UART2_IRQn, LPUART2_IRQHandler, NONE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||||
|
{
|
||||||
|
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||||
|
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||||
|
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||||
|
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||||
|
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||||
|
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||||
|
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||||
|
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||||
|
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
|
||||||
|
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||||
|
{
|
||||||
|
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||||
|
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||||
|
|
||||||
|
/* kLPUART_RxDataRegFullFlag can only cleared or set by hardware */
|
||||||
|
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
|
||||||
|
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxOverrunFlag) {
|
||||||
|
/* Clear overrun flag, otherwise the RX does not work. */
|
||||||
|
LPUART_ClearStatusFlags(uart_base, kLPUART_RxOverrunFlag);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Get debug console frequency. */
|
||||||
|
uint32_t GetUartSrcFreq(uint32_t irq_num)
|
||||||
|
{
|
||||||
|
uint32_t idx = irq_num % LPUART1_IRQn;
|
||||||
|
|
||||||
|
return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1 + idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(serial_drv);
|
||||||
|
|
||||||
|
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||||
|
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||||
|
|
||||||
|
if (configure_info->private_data) {
|
||||||
|
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
|
||||||
|
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
|
||||||
|
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
|
||||||
|
|
||||||
|
// config serial receive sem timeout
|
||||||
|
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
|
||||||
|
|
||||||
|
lpuart_config_t config;
|
||||||
|
LPUART_GetDefaultConfig(&config);
|
||||||
|
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
|
||||||
|
|
||||||
|
switch (serial_cfg->data_cfg.serial_data_bits)
|
||||||
|
{
|
||||||
|
case DATA_BITS_7:
|
||||||
|
config.dataBitsCount = kLPUART_SevenDataBits;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
config.dataBitsCount = kLPUART_EightDataBits;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (serial_cfg->data_cfg.serial_stop_bits)
|
||||||
|
{
|
||||||
|
case STOP_BITS_2:
|
||||||
|
config.stopBitCount = kLPUART_TwoStopBit;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
config.stopBitCount = kLPUART_OneStopBit;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (serial_cfg->data_cfg.serial_parity_mode)
|
||||||
|
{
|
||||||
|
case PARITY_ODD:
|
||||||
|
config.parityMode = kLPUART_ParityOdd;
|
||||||
|
break;
|
||||||
|
case PARITY_EVEN:
|
||||||
|
config.parityMode = kLPUART_ParityEven;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
config.parityMode = kLPUART_ParityDisabled;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
config.enableTx = true;
|
||||||
|
config.enableRx = true;
|
||||||
|
|
||||||
|
LPUART_Init(uart_base, &config, GetUartSrcFreq(serial_cfg->hw_cfg.serial_irq_interrupt));
|
||||||
|
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(serial_drv);
|
||||||
|
|
||||||
|
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||||
|
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||||
|
|
||||||
|
switch (serial_operation_cmd)
|
||||||
|
{
|
||||||
|
case OPER_CLR_INT:
|
||||||
|
DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OPER_SET_INT:
|
||||||
|
LPUART_EnableInterrupts(uart_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||||
|
NVIC_SetPriority(serial_cfg->hw_cfg.serial_irq_interrupt, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
|
||||||
|
EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
|
||||||
|
{
|
||||||
|
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||||
|
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||||
|
|
||||||
|
LPUART_WriteByte(uart_base, c);
|
||||||
|
while (!(LPUART_GetStatusFlags(uart_base) & kLPUART_TxDataRegEmptyFlag));
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
|
||||||
|
{
|
||||||
|
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||||
|
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||||
|
|
||||||
|
int c = -1;
|
||||||
|
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
|
||||||
|
c = LPUART_ReadByte(uart_base);
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||||
|
{
|
||||||
|
NULL_PARAM_CHECK(drv);
|
||||||
|
NULL_PARAM_CHECK(configure_info);
|
||||||
|
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
int serial_operation_cmd;
|
||||||
|
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||||
|
|
||||||
|
switch (configure_info->configure_cmd)
|
||||||
|
{
|
||||||
|
case OPE_INT:
|
||||||
|
ret = SerialInit(serial_drv, configure_info);
|
||||||
|
break;
|
||||||
|
case OPE_CFG:
|
||||||
|
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||||
|
ret = SerialConfigure(serial_drv, serial_operation_cmd);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct SerialDataCfg data_cfg_init =
|
||||||
|
{
|
||||||
|
.serial_baud_rate = BAUD_RATE_115200,
|
||||||
|
.serial_data_bits = DATA_BITS_8,
|
||||||
|
.serial_stop_bits = STOP_BITS_1,
|
||||||
|
.serial_parity_mode = PARITY_NONE,
|
||||||
|
.serial_bit_order = BIT_ORDER_LSB,
|
||||||
|
.serial_invert_mode = NRZ_NORMAL,
|
||||||
|
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||||
|
.serial_timeout = WAITING_FOREVER,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*manage the serial device operations*/
|
||||||
|
static const struct SerialDrvDone drv_done =
|
||||||
|
{
|
||||||
|
.init = SerialInit,
|
||||||
|
.configure = SerialConfigure,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*manage the serial device hal operations*/
|
||||||
|
static struct SerialHwDevDone hwdev_done =
|
||||||
|
{
|
||||||
|
.put_char = SerialPutChar,
|
||||||
|
.get_char = SerialGetChar,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||||
|
{
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
|
||||||
|
/*Init the serial bus */
|
||||||
|
ret = SerialBusInit(serial_bus, bus_name);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit SerialBusInit error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Init the serial driver*/
|
||||||
|
ret = SerialDriverInit(serial_driver, drv_name);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit SerialDriverInit error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Attach the serial driver to the serial bus*/
|
||||||
|
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Attach the serial device to the serial bus*/
|
||||||
|
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||||
|
{
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
|
||||||
|
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int Imxrt1176HwUartInit(void)
|
||||||
|
{
|
||||||
|
x_err_t ret = EOK;
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART1
|
||||||
|
static struct SerialCfgParam serial_cfg_1;
|
||||||
|
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||||
|
|
||||||
|
static struct SerialDevParam serial_dev_param_1;
|
||||||
|
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||||
|
|
||||||
|
serial_driver_1.drv_done = &drv_done;
|
||||||
|
serial_driver_1.configure = &SerialDrvConfigure;
|
||||||
|
serial_device_1.hwdev_done = &hwdev_done;
|
||||||
|
|
||||||
|
serial_cfg_1.data_cfg = data_cfg_init;
|
||||||
|
|
||||||
|
serial_cfg_1.hw_cfg.private_data = (void *)LPUART1;
|
||||||
|
serial_cfg_1.hw_cfg.serial_irq_interrupt = LPUART1_IRQn;
|
||||||
|
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||||
|
|
||||||
|
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||||
|
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||||
|
|
||||||
|
ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART2
|
||||||
|
static struct SerialCfgParam serial_cfg_2;
|
||||||
|
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||||
|
|
||||||
|
static struct SerialDevParam serial_dev_param_2;
|
||||||
|
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||||
|
|
||||||
|
serial_driver_2.drv_done = &drv_done;
|
||||||
|
serial_driver_2.configure = &SerialDrvConfigure;
|
||||||
|
serial_device_2.hwdev_done = &hwdev_done;
|
||||||
|
|
||||||
|
serial_cfg_2.data_cfg = data_cfg_init;
|
||||||
|
|
||||||
|
serial_cfg_2.hw_cfg.private_data = (void *)LPUART2;
|
||||||
|
serial_cfg_2.hw_cfg.serial_irq_interrupt = LPUART2_IRQn;
|
||||||
|
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||||
|
|
||||||
|
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||||
|
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||||
|
|
||||||
|
ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
|
||||||
|
if (EOK != ret) {
|
||||||
|
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
||||||
|
SRC_FILES := fsl_flexspi_nor_boot.c
|
||||||
|
|
||||||
|
include $(KERNEL_ROOT)/compiler.mk
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "evkmimxrt1170_flexspi_nor_config.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.conf"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.conf"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
const flexspi_nor_config_t hyperflash_config = { //MaaXBoard RT update
|
||||||
|
.memConfig =
|
||||||
|
{
|
||||||
|
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||||
|
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||||
|
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||||
|
.csHoldTime = 3u,
|
||||||
|
.csSetupTime = 3u,
|
||||||
|
.columnAddressWidth = 3u,
|
||||||
|
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||||
|
.controllerMiscOption =
|
||||||
|
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||||
|
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||||
|
.sflashPadType = kSerialFlash_8Pads,
|
||||||
|
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||||
|
.sflashA1Size = 32u * 1024u * 1024u,
|
||||||
|
.dataValidTime = {16u, 16u},
|
||||||
|
.lookupTable =
|
||||||
|
{
|
||||||
|
// Read LUTs
|
||||||
|
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
|
||||||
|
FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
|
||||||
|
FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.pageSize = 512u,
|
||||||
|
.sectorSize = 256u * 1024u,
|
||||||
|
.blockSize = 256u * 1024u,
|
||||||
|
.isUniformBlockSize = true,
|
||||||
|
};
|
||||||
|
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||||
|
|
@ -0,0 +1,268 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2018-2020 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
|
||||||
|
#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||||
|
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/* FLEXSPI memory config block related defintions */
|
||||||
|
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||||
|
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||||
|
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||||
|
|
||||||
|
/* FLEXSPI Feature related definitions */
|
||||||
|
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||||
|
|
||||||
|
/* Lookup table related defintions */
|
||||||
|
#define CMD_INDEX_READ 0
|
||||||
|
#define CMD_INDEX_READSTATUS 1
|
||||||
|
#define CMD_INDEX_WRITEENABLE 2
|
||||||
|
#define CMD_INDEX_WRITE 4
|
||||||
|
|
||||||
|
#define CMD_LUT_SEQ_IDX_READ 0
|
||||||
|
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||||
|
|
||||||
|
#define CMD_SDR 0x01
|
||||||
|
#define CMD_DDR 0x21
|
||||||
|
#define RADDR_SDR 0x02
|
||||||
|
#define RADDR_DDR 0x22
|
||||||
|
#define CADDR_SDR 0x03
|
||||||
|
#define CADDR_DDR 0x23
|
||||||
|
#define MODE1_SDR 0x04
|
||||||
|
#define MODE1_DDR 0x24
|
||||||
|
#define MODE2_SDR 0x05
|
||||||
|
#define MODE2_DDR 0x25
|
||||||
|
#define MODE4_SDR 0x06
|
||||||
|
#define MODE4_DDR 0x26
|
||||||
|
#define MODE8_SDR 0x07
|
||||||
|
#define MODE8_DDR 0x27
|
||||||
|
#define WRITE_SDR 0x08
|
||||||
|
#define WRITE_DDR 0x28
|
||||||
|
#define READ_SDR 0x09
|
||||||
|
#define READ_DDR 0x29
|
||||||
|
#define LEARN_SDR 0x0A
|
||||||
|
#define LEARN_DDR 0x2A
|
||||||
|
#define DATSZ_SDR 0x0B
|
||||||
|
#define DATSZ_DDR 0x2B
|
||||||
|
#define DUMMY_SDR 0x0C
|
||||||
|
#define DUMMY_DDR 0x2C
|
||||||
|
#define DUMMY_RWDS_SDR 0x0D
|
||||||
|
#define DUMMY_RWDS_DDR 0x2D
|
||||||
|
#define JMP_ON_CS 0x1F
|
||||||
|
#define STOP 0
|
||||||
|
|
||||||
|
#define FLEXSPI_1PAD 0
|
||||||
|
#define FLEXSPI_2PAD 1
|
||||||
|
#define FLEXSPI_4PAD 2
|
||||||
|
#define FLEXSPI_8PAD 3
|
||||||
|
|
||||||
|
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||||
|
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||||
|
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||||
|
|
||||||
|
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||||
|
typedef enum _FlexSpiSerialClockFreq
|
||||||
|
{
|
||||||
|
kFlexSpiSerialClk_30MHz = 1,
|
||||||
|
kFlexSpiSerialClk_50MHz = 2,
|
||||||
|
kFlexSpiSerialClk_60MHz = 3,
|
||||||
|
kFlexSpiSerialClk_80MHz = 4,
|
||||||
|
kFlexSpiSerialClk_100MHz = 5,
|
||||||
|
kFlexSpiSerialClk_120MHz = 6,
|
||||||
|
kFlexSpiSerialClk_133MHz = 7,
|
||||||
|
kFlexSpiSerialClk_166MHz = 8,
|
||||||
|
kFlexSpiSerialClk_200MHz = 9,
|
||||||
|
} flexspi_serial_clk_freq_t;
|
||||||
|
|
||||||
|
//!@brief FlexSPI clock configuration type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||||
|
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Read Sample Clock Source definition
|
||||||
|
typedef enum _FlashReadSampleClkSource
|
||||||
|
{
|
||||||
|
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||||
|
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||||
|
} flexspi_read_sample_clk_t;
|
||||||
|
|
||||||
|
//!@brief Misc feature bit definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||||
|
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||||
|
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||||
|
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||||
|
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||||
|
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||||
|
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Type Definition
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||||
|
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||||
|
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Pad Definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kSerialFlash_1Pad = 1,
|
||||||
|
kSerialFlash_2Pads = 2,
|
||||||
|
kSerialFlash_4Pads = 4,
|
||||||
|
kSerialFlash_8Pads = 8,
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI LUT Sequence structure
|
||||||
|
typedef struct _lut_sequence
|
||||||
|
{
|
||||||
|
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||||
|
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||||
|
uint16_t reserved;
|
||||||
|
} flexspi_lut_seq_t;
|
||||||
|
|
||||||
|
//!@brief Flash Configuration Command Type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||||
|
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||||
|
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||||
|
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||||
|
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||||
|
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Memory Configuration Block
|
||||||
|
typedef struct _FlexSPIConfig
|
||||||
|
{
|
||||||
|
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||||
|
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||||
|
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||||
|
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||||
|
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||||
|
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||||
|
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||||
|
//! Serial NAND, need to refer to datasheet
|
||||||
|
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||||
|
//! Generic configuration, etc.
|
||||||
|
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||||
|
//! DPI/QPI/OPI switch or reset command
|
||||||
|
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||||
|
//! sequence number, [31:16] Reserved
|
||||||
|
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||||
|
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||||
|
flexspi_lut_seq_t
|
||||||
|
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||||
|
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||||
|
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||||
|
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||||
|
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||||
|
//! details
|
||||||
|
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||||
|
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||||
|
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||||
|
//! Chapter for more details
|
||||||
|
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||||
|
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||||
|
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||||
|
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||||
|
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||||
|
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||||
|
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||||
|
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||||
|
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||||
|
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||||
|
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||||
|
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||||
|
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||||
|
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||||
|
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||||
|
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||||
|
//! busy flag is 0 when flash device is busy
|
||||||
|
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||||
|
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||||
|
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||||
|
} flexspi_mem_config_t;
|
||||||
|
|
||||||
|
/* */
|
||||||
|
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||||
|
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||||
|
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||||
|
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||||
|
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||||
|
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||||
|
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||||
|
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||||
|
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||||
|
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||||
|
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||||
|
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||||
|
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||||
|
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial NOR configuration block
|
||||||
|
*/
|
||||||
|
typedef struct _flexspi_nor_config
|
||||||
|
{
|
||||||
|
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||||
|
uint32_t pageSize; //!< Page size of Serial NOR
|
||||||
|
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||||
|
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||||
|
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||||
|
uint8_t reserved0[2]; //!< Reserved for future use
|
||||||
|
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||||
|
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||||
|
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||||
|
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||||
|
uint32_t blockSize; //!< Block size
|
||||||
|
uint32_t reserve2[11]; //!< Reserved for future use
|
||||||
|
} flexspi_nor_config_t;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2019-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl_flexspi_nor_boot.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.ivt"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.ivt"
|
||||||
|
#endif
|
||||||
|
/*************************************
|
||||||
|
* IVT Data
|
||||||
|
*************************************/
|
||||||
|
const ivt image_vector_table = {
|
||||||
|
IVT_HEADER, /* IVT Header */
|
||||||
|
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
|
||||||
|
IVT_RSVD, /* Reserved = 0 */
|
||||||
|
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
|
||||||
|
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
|
||||||
|
(uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */
|
||||||
|
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
|
||||||
|
IVT_RSVD /* Reserved = 0 */
|
||||||
|
};
|
||||||
|
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.boot_data"), used))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.boot_data"
|
||||||
|
#endif
|
||||||
|
/*************************************
|
||||||
|
* Boot Data
|
||||||
|
*************************************/
|
||||||
|
const BOOT_DATA_T g_boot_data = {
|
||||||
|
BOOT_IMAGE_BASE, /* boot start location */
|
||||||
|
BOOT_IMAGE_SIZE, /* size */
|
||||||
|
PLUGIN_FLAG, /* Plugin flag*/
|
||||||
|
0xFFFFFFFFU /* empty - extra data word */
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,147 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2019-2021 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __FLEXSPI_NOR_BOOT_H__
|
||||||
|
#define __FLEXSPI_NOR_BOOT_H__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "board.h"
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_DEVICE driver version 2.0.4. */
|
||||||
|
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*************************************
|
||||||
|
* IVT Data
|
||||||
|
*************************************/
|
||||||
|
typedef struct _ivt_
|
||||||
|
{
|
||||||
|
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
|
||||||
|
* (see @ref data)
|
||||||
|
*/
|
||||||
|
uint32_t hdr;
|
||||||
|
/** Absolute address of the first instruction to execute from the
|
||||||
|
* image
|
||||||
|
*/
|
||||||
|
uint32_t entry;
|
||||||
|
/** Reserved in this version of HAB: should be NULL. */
|
||||||
|
uint32_t reserved1;
|
||||||
|
/** Absolute address of the image DCD: may be NULL. */
|
||||||
|
uint32_t dcd;
|
||||||
|
/** Absolute address of the Boot Data: may be NULL, but not interpreted
|
||||||
|
* any further by HAB
|
||||||
|
*/
|
||||||
|
uint32_t boot_data;
|
||||||
|
/** Absolute address of the IVT.*/
|
||||||
|
uint32_t self;
|
||||||
|
/** Absolute address of the image CSF.*/
|
||||||
|
uint32_t csf;
|
||||||
|
/** Reserved in this version of HAB: should be zero. */
|
||||||
|
uint32_t reserved2;
|
||||||
|
} ivt;
|
||||||
|
|
||||||
|
#define IVT_MAJOR_VERSION 0x4
|
||||||
|
#define IVT_MAJOR_VERSION_SHIFT 0x4
|
||||||
|
#define IVT_MAJOR_VERSION_MASK 0xF
|
||||||
|
#define IVT_MINOR_VERSION 0x1
|
||||||
|
#define IVT_MINOR_VERSION_SHIFT 0x0
|
||||||
|
#define IVT_MINOR_VERSION_MASK 0xF
|
||||||
|
|
||||||
|
#define IVT_VERSION(major, minor) \
|
||||||
|
((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
|
||||||
|
(((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
|
||||||
|
|
||||||
|
/* IVT header */
|
||||||
|
#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
|
||||||
|
#define IVT_SIZE 0x2000
|
||||||
|
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
|
||||||
|
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
|
||||||
|
|
||||||
|
/* Set resume entry */
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||||
|
extern uint32_t Reset_Handler[];
|
||||||
|
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
|
||||||
|
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
|
||||||
|
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
|
||||||
|
#define BOOT_DATA_ADDRESS &g_boot_data
|
||||||
|
#define IVT_ADDRESS &image_vector_table
|
||||||
|
#define DCD_DATA_ADDRESS dcd_data
|
||||||
|
#elif defined(__MCUXPRESSO)
|
||||||
|
extern uint32_t ResetISR[];
|
||||||
|
extern uint32_t __boot_hdr_start__[];
|
||||||
|
extern uint32_t __boot_hdr_ivt_loadaddr__[];
|
||||||
|
extern uint32_t __boot_hdr_boot_data_loadaddr__[];
|
||||||
|
extern uint32_t __boot_hdr_dcd_loadaddr__[];
|
||||||
|
extern uint32_t _boot_loadaddr[];
|
||||||
|
extern uint32_t _boot_size[];
|
||||||
|
#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR)
|
||||||
|
#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr)
|
||||||
|
#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size)
|
||||||
|
#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__)
|
||||||
|
#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__)
|
||||||
|
#define DCD_DATA_ADDRESS ((uint32_t)__boot_hdr_dcd_loadaddr__)
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
extern uint32_t Reset_Handler[];
|
||||||
|
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
|
||||||
|
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
|
||||||
|
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
|
||||||
|
#define BOOT_DATA_ADDRESS &g_boot_data
|
||||||
|
#define IVT_ADDRESS &image_vector_table
|
||||||
|
#define DCD_DATA_ADDRESS dcd_data
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
extern uint32_t Reset_Handler[];
|
||||||
|
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
|
||||||
|
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
|
||||||
|
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
|
||||||
|
#define BOOT_DATA_ADDRESS &g_boot_data
|
||||||
|
#define IVT_ADDRESS &image_vector_table
|
||||||
|
#define DCD_DATA_ADDRESS dcd_data
|
||||||
|
#endif
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
|
||||||
|
#define DCD_ADDRESS DCD_DATA_ADDRESS
|
||||||
|
#else
|
||||||
|
#define DCD_ADDRESS 0
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#define CSF_ADDRESS 0
|
||||||
|
#define IVT_RSVD (uint32_t)(0x00000000)
|
||||||
|
|
||||||
|
/*************************************
|
||||||
|
* Boot Data
|
||||||
|
*************************************/
|
||||||
|
typedef struct _boot_data_
|
||||||
|
{
|
||||||
|
uint32_t start; /* boot start location */
|
||||||
|
uint32_t size; /* size */
|
||||||
|
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
|
||||||
|
uint32_t placeholder; /* placehoder to make even 0x10 size */
|
||||||
|
} BOOT_DATA_T;
|
||||||
|
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
#define FLASH_BASE FlexSPI1_AMBA_BASE
|
||||||
|
#elif __CORTEX_M == 4
|
||||||
|
#define FLASH_BASE FlexSPI1_ALIAS_BASE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BOARD_FLASH_SIZE)
|
||||||
|
#define FLASH_SIZE BOARD_FLASH_SIZE
|
||||||
|
#else
|
||||||
|
#error "Please define macro BOARD_FLASH_SIZE"
|
||||||
|
#endif
|
||||||
|
#define PLUGIN_FLAG (uint32_t)0
|
||||||
|
|
||||||
|
/* External Variables */
|
||||||
|
extern const BOOT_DATA_T g_boot_data;
|
||||||
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
|
||||||
|
extern const uint8_t dcd_data[];
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __FLEXSPI_NOR_BOOT_H__ */
|
||||||
|
|
@ -282,6 +282,27 @@ KERNELPATHS += \
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/imxrt1176-sbc)
|
||||||
|
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||||
|
-I$(KERNEL_ROOT)/arch/arm/cortex-m7 \
|
||||||
|
-I$(BSP_ROOT)/include \
|
||||||
|
-I$(BSP_ROOT)/third_party_driver \
|
||||||
|
-I$(BSP_ROOT)/third_party_driver/include \
|
||||||
|
-I$(BSP_ROOT)/third_party_driver/CMSIS/Include \
|
||||||
|
-I$(KERNEL_ROOT)/include \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
|
||||||
|
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
|
||||||
|
-I$(KERNEL_ROOT)/resources/include \
|
||||||
|
-I$(BSP_ROOT)/xip #
|
||||||
|
endif
|
||||||
|
|
||||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano)
|
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano)
|
||||||
KERNELPATHS += \
|
KERNELPATHS += \
|
||||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m3 \
|
-I$(KERNEL_ROOT)/arch/arm/cortex-m3 \
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue