forked from xuos/xiuos
340 lines
19 KiB
C
340 lines
19 KiB
C
/**
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* @file dcd.c
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* @brief support imxrt1176-sbc dcd
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022-08-19
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*/
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/*************************************************
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File name: dcd.c
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Description: support imxrt1176-sbc dcd
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Others: take SDK_2_11_1_MIMXRT1170-EVK for references
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History:
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1. Date: 2022-08-19
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Author: AIIT XUOS Lab
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Modification:
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*************************************************/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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#include "dcd.h"
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#include "fsl_common.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.dcd_data"), used))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.dcd_data"
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#endif
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: DCDx V2.0
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processor: MIMXRT1176xxxxx
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package_id: MIMXRT1176DVMAA
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mcu_data: ksdk2_0
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processor_version: 9.0.1
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board: MIMXRT1170-EVK
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output_format: c_array
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
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const uint8_t dcd_data[] = {
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/* HEADER */
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/* Tag */
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0xD2,
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/* Image Length */
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0x03, 0x98,
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/* Version */
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0x41,
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/* COMMANDS */
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/* group: 'Imported Commands' */
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/* #1.1-93, command header bytes for merged 'Write - value' command */
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0xCC, 0x02, 0xEC, 0x04,
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/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */
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0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02,
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/* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0, size: 4 */
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0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
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/* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0, size: 4 */
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0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
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/* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0, size: 4 */
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0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
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/* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
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/* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
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/* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
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/* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
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/* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
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/* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
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/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
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/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
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/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
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/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
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/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
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/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
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/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
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/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
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/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
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/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
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/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
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/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
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/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
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/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
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/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
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/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
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/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
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/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
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/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
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/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
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/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
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/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
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/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
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/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
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/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
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/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
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/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
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/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
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/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
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/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x0, size: 4 */
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0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
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/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4 */
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0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10,
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/* #1.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08,
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/* #1.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08,
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/* #1.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08,
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/* #1.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08,
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/* #1.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08,
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/* #1.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08,
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/* #1.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08,
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/* #1.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08,
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/* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08,
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/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08,
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/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08,
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/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08,
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/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08,
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/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08,
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/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
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/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08,
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/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08,
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/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08,
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/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08,
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/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08,
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/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08,
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/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08,
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/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08,
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/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08,
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/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08,
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/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08,
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/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08,
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/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08,
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/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08,
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/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08,
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/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08,
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/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08,
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/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08,
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/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08,
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/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08,
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/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08,
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/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08,
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/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08,
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/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08,
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/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x8, size: 4 */
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0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08,
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/* #1.82, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
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0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04,
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/* #1.83, command: write_value, address: SEMC_BMCR0, value: 0x00030524, size: 4 */
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0x40, 0x0D, 0x40, 0x08, 0x00, 0x03, 0x05, 0x24,
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/* #1.84, command: write_value, address: SEMC_BMCR1, value: 0x06030524, size: 4 */
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0x40, 0x0D, 0x40, 0x0C, 0x06, 0x03, 0x05, 0x24,
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/* #1.85, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
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0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1B,
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/* #1.86, command: write_value, address: SEMC_SDRAMCR0, value: 0x00000F31, size: 4 */
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0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x31,
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/* #1.87, command: write_value, address: SEMC_SDRAMCR1, value: 0x00772A22, size: 4 */
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0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22,
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/* #1.88, command: write_value, address: SEMC_SDRAMCR2, value: 0x00010A0D, size: 4 */
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0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D,
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/* #1.89, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */
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0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08,
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/* #1.90, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
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0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00,
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/* #1.91, command: write_value, address: SEMC_IPCR1, value: 0x00000002, size: 4 */
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0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02,
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/* #1.92, command: write_value, address: SEMC_IPCR2, value: 0x00000000, size: 4 */
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0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00,
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/* #1.93, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
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0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
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/* group: 'nop' */
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/* #1, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #2, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #3, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #4, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #5, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* group: 'set intr/ipcmd' */
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/* #1.1-2, command header bytes for merged 'Write - value' command */
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0xCC, 0x00, 0x14, 0x04,
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/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
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0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
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/* #1.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
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0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
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/* group: 'nop2' */
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/* #1, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #2, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #3, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #4, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #5, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* group: 'set intr/ipcmd 2' */
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/* #1.1-2, command header bytes for merged 'Write - value' command */
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0xCC, 0x00, 0x14, 0x04,
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/* #1.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
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0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
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/* #1.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
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0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
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/* group: 'nop3' */
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/* #1, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #2, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #3, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #4, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #5, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* group: 'set intr/iptxdat/ipcmd' */
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/* #1.1-3, command header bytes for merged 'Write - value' command */
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0xCC, 0x00, 0x1C, 0x04,
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/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
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0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
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/* #1.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
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0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33,
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/* #1.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
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0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
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/* group: 'nop4' */
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/* #1, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #2, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #3, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #4, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* #5, command: nop */
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0xC0, 0x00, 0x04, 0x00,
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/* group: 'set intr/s' */
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/* #1.1-2, command header bytes for merged 'Write - value' command */
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0xCC, 0x00, 0x14, 0x04,
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/* #1.1, command: write_value, address: SEMC_INTR, value: 0x3, size: 4 */
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0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
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/* #1.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */
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0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09
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};
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/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
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#else
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const uint8_t dcd_data[] = {0x00};
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#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
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#endif /* XIP_BOOT_HEADER_ENABLE */
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