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Merge pull request 'merge code' (#19) from ok1052 into prepare_for_master 

ok
This commit is contained in:
wgzAIIT 2022-03-28 16:16:08 +08:00
parent 1814a2d577 ad9b7492ae
commit 88802c0964
9 changed files with 118 additions and 125 deletions
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4
Ubiquitous/Nuttx/aiit_board/xidatong/Kconfig
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@ -7,7 +7,7 @@ if ARCH_BOARD_XIDATONG
choice
prompt "Boot Flash"
default XIDATONG_HYPER_FLASH
default XIDATONG_QSPI_FLASH
config XIDATONG_HYPER_FLASH
bool "HYPER Flash"
@ -19,7 +19,7 @@ endchoice # Boot Flash
config XIDATONG_SDRAM
bool "Enable SDRAM"
default n
default y
select IMXRT_SEMC_INIT_DONE
---help---
Activate DCD configuration of SDRAM

1
Ubiquitous/Nuttx/aiit_board/xidatong/configs/knsh/defconfig
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@ -37,6 +37,7 @@ CONFIG_NUTTX_USERSPACE=0x60200000
CONFIG_PASS1_BUILDIR="boards/arm/imxrt/xidatong/kernel"
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=8

1
Ubiquitous/Nuttx/aiit_board/xidatong/configs/libcxxtest/defconfig
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@ -36,6 +36,7 @@ CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=536870912
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_CPULOAD=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y

1
Ubiquitous/Nuttx/aiit_board/xidatong/configs/netnsh/defconfig
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@ -56,6 +56,7 @@ CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y

1
Ubiquitous/Nuttx/aiit_board/xidatong/configs/nsh/defconfig
View File

@ -35,6 +35,7 @@ CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=14

73
Ubiquitous/Nuttx/aiit_board/xidatong/configs/usdhc/defconfig Normal file
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@ -0,0 +1,73 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="xidatong"
CONFIG_ARCH_BOARD_XIDATONG=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y
CONFIG_ARCH_INTERRUPTSTACK=10240
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_URANDOM=y
CONFIG_DEV_ZERO=y
CONFIG_FAT_LCNAMES=y
CONFIG_CLOCK_MONOTONIC=y
CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_EXAMPLES_HELLO=y
CONFIG_IMXRT1020_EVK_QSPI_FLASH=y
CONFIG_IMXRT_GPIO1_0_15_IRQ=y
CONFIG_IMXRT_GPIO_IRQ=y
CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_USDHC1=y
CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y
CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_NCHAINS=8
CONFIG_LIBC_STRERROR=y
CONFIG_LPUART1_RXBUFSIZE=1024
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=1024
CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MM_IOB=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_CMDOPT_DD_STATS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_CHILD_STATUS=y
CONFIG_SCHED_HAVE_PARENT=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDIO_BLOCKSETUP=y
CONFIG_SERIAL_TERMIOS=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_CLE_CMD_HISTORY=y
CONFIG_SYSTEM_COLOR_CLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_USER_ENTRYPOINT="nsh_main"

22
Ubiquitous/Nuttx/aiit_board/xidatong/include/board.h
View File

@ -207,20 +207,16 @@
* sure shapes are square with minimal ringing.
*/
#define GPIO_USDHC1_DATA0 GPIO_USDHC1_DATA0_1 /* GPIO_SD_B0_02 */
#define GPIO_USDHC1_DATA1 GPIO_USDHC1_DATA1_1 /* GPIO_SD_B0_03 */
#define GPIO_USDHC1_DATA2 GPIO_USDHC1_DATA2_1 /* GPIO_SD_B0_04 */
#define GPIO_USDHC1_DATA3 GPIO_USDHC1_DATA3_1 /* GPIO_SD_B0_05 */
#define GPIO_USDHC1_CLK GPIO_USDHC1_CLK_1 /* GPIO_SD_B0_01 */
#define GPIO_USDHC1_CMD GPIO_USDHC1_CMD_1 /* GPIO_SD_B0_00 */
#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0 | IOMUX_USDHC1_DATAX_DEFAULT)
#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1 | IOMUX_USDHC1_DATAX_DEFAULT)
#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2 | IOMUX_USDHC1_DATAX_DEFAULT)
#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3 | IOMUX_USDHC1_DATAX_DEFAULT)
#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK | IOMUX_USDHC1_CLK_DEFAULT)
#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD | IOMUX_USDHC1_CMD_DEFAULT)
#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT)
#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_02 */
#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_03 */
#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_04 */
#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_05 */
#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_SD_B0_01 */
#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) /* GPIO_SD_B0_00 */
//#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT)
#define PIN_USDHC1_CD_GPIO (IOMUX_VSD_DEFAULT | GPIO_PORT2 | GPIO_PIN28) /* GPIO_B1_12 */
/* 386 KHz for initial inquiry stuff */

138
Ubiquitous/Nuttx/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.c
View File

@ -90,121 +90,41 @@ const struct flexspi_nor_config_s g_flash_config =
{
.mem_config =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
.cs_hold_time = 3u,
.cs_setup_time = 3u,
.column_address_width = 0u,
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
.sflash_pad_type = SERIAL_FLASH_4PADS,
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_60MHz,
.sflash_a1size = 8u * 1024u * 1024u,
.data_valid_time =
{
16u, 16u
},
.lookup_table =
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY,
.cs_hold_time = 3u,
.cs_setup_time = 3u,
.device_mode_cfg_enable = true,
.device_mode_type = 1,
.device_mode_seq.seq_num = 1,
.device_mode_seq.seq_id = 4,
.device_mode_arg = 0x000200,
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
.sflash_pad_type = SERIAL_FLASH_4PADS,
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_60MHz,
.sflash_a1size = 16u * 1024u * 1024u,
.data_valid_time = {16u, 16u},
/* Enable DDR mode, Word addassable,
* Safe configuration, Differential clock
*/
.lookup_table =
{
/* LUTs */
/* Read LUTs */
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
[2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
/* 0 Fast read Quad IO DTR Mode Operation in SPI Mode (normal read) */
FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0xed, RADDR_DDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_DDR,
FLEXSPI_4PAD, 0x0c, READ_DDR, FLEXSPI_4PAD, 0x08),
FLEXSPI_LUT_SEQ(STOP,
FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP,
FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 1 Read Status */
FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x1),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 2 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 3 */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 4 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 5 Erase Sector */
FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0xd7, RADDR_SDR, FLEXSPI_1PAD, 0x18),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 6 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 7 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 8 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 9 Page Program */
FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x8, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 10 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 11 Chip Erase */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xc7, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
//Write Enable
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
//Write status
[4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
},
},
.page_size = 256u,
.sector_size = 4u * 1024u,
.blocksize = 32u * 1024u,
.is_uniform_blocksize = false,
};
#else
# error Boot Flash type not chosen!

2
Ubiquitous/Nuttx/aiit_board/xidatong/src/imxrt_sdram_ini_dcd.c
View File

@ -1256,7 +1256,7 @@ const uint8_t g_dcd_data[] =
0x00,
0x4c,
0x50,
0x21,
0x07,
0x0a,
0x09,
};