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feat add xishutong-arm32 board for XiUOS from Liu_Weichao 

it is OK
This commit is contained in:
IACU 2023-11-20 10:40:06 +08:00
parent 50d8ff5488 94d3d37a19
commit 52454eec8d
244 changed files with 126359 additions and 1862 deletions
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162
APP_Framework/Applications/app_test/test_4g_ec200a.c Normal file
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@ -0,0 +1,162 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file test_4g_ec200a.c
* @brief Implement the connection 4G function, using QUECTEL EC200A device
* @version 1.1
* @author AIIT XUOS Lab
* @date 2023.10.15
*/
#include <stdio.h>
#include <string.h>
#include <transform.h>
#ifdef ADD_XIZI_FEATURES
char *trans_data = "{\"saleid\": \"52330000MJ87322565\", \"gateid\": \"10100001011\", \"type\": \"report\", \"time\": \"2023-06-15 17:22:00\", \"sequence\": \"268\", \"source\": \"da\", \"meter\": [{\"id\": \"T100106\", \"status\": \"1\", \"name\": \"T100106\", \"values\": {}}]}\r\n";
// const char chk_buad[] = {"AT+IPR?\r\n"};
const char set_mode[] = {"AT+QMTCFG=\"recv/mode\",0,0,1\r\n"};
// const char set_cfg[] = {"AT+QMTCFG=\"aliauth\",0,\"k0celEMx5DK\",\"test_device\",\"411aa14c0dc671f7ee869adced442d13\"\r\n"};
const char set_server[] = {"AT+QMTOPEN=0,\"xyheqmx.e3.luyouxia.net\",13333\r\n"};
// const char set_server[] = {"AT+QMTOPEN=0,\"iot-060a7p7c.mqtt.iothub.aliyuncs.com\",1883\r\n"};
const char set_conn[] = {"AT+QMTCONN=0,\"quectel\",\"test\",\"test123456\"\r\n"};
// const char set_conn[] = {"AT+QMTCONN=0,\"sysoul\"\r\n"};
// const char set_get[] = {"AT+QMTSUB=0,1,\"/get\",0\r\n"};
// const char set_reply[] = {"AT+QMTPUBEX=0,0,0,0,\"/reply\",1000\r\n"};
char recv_buf[100] = {0};
int buf_len = 0;
void Test4G(void)
{
int quectel_fd = PrivOpen(ADAPTER_QUECTEL_DRIVER, O_RDWR);
if (quectel_fd < 0) {
printf("open quectel fd error:%d\n", quectel_fd);
return;
}
printf("quectel fopen success\n");
struct SerialDataCfg quectel_cfg;
memset(&quectel_cfg, 0, sizeof(struct SerialDataCfg));
quectel_cfg.serial_baud_rate = BAUD_RATE_115200;
quectel_cfg.serial_data_bits = DATA_BITS_8;
quectel_cfg.serial_stop_bits = STOP_BITS_1;
quectel_cfg.serial_parity_mode = PARITY_NONE;
quectel_cfg.serial_bit_order = BIT_ORDER_LSB;
quectel_cfg.serial_invert_mode = NRZ_NORMAL;
// quectel_cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
quectel_cfg.serial_buffer_size = 1024;
quectel_cfg.serial_timeout = 1000;
quectel_cfg.is_ext_uart = 0;
// quectel_cfg.ext_uart_no = ADAPTER_QUECTEL_DRIVER_EXT_PORT;
// quectel_cfg.port_configure = PORT_CFG_INIT;
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = &quectel_cfg;
if (0 != PrivIoctl(quectel_fd, OPE_INT, &ioctl_cfg)) {
printf("ioctl quectel fd error %d\n", quectel_fd);
PrivClose(quectel_fd);
return;
}
printf("4G module set\n");
// memset(recv_buf, 0, sizeof(recv_buf));
// printf("chk_buad: %s\n", chk_buad);
// printf("chk_buad_len: %d\n", strlen(chk_buad));
// PrivWrite(quectel_fd, chk_buad, strlen(chk_buad));
// PrivTaskDelay(30);
// buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
// printf("buf_len: %d\n", buf_len);
// printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
// PrivTaskDelay(1000);
memset(recv_buf, 0, sizeof(recv_buf));
printf("set_mode: %s\n", set_mode);
printf("set_mode_len: %d\n", strlen(set_mode));
PrivWrite(quectel_fd, set_mode, strlen(set_mode));
PrivTaskDelay(30);
buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
printf("buf_len: %d\n", buf_len);
printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
PrivTaskDelay(1000);
// memset(recv_buf, 0, sizeof(recv_buf));
// printf("set_cfg: %s\n", set_cfg);
// printf("set_cfg_len: %d\n", strlen(set_cfg));
// PrivWrite(quectel_fd, set_cfg, strlen(set_cfg));
// PrivTaskDelay(30);
// buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
// printf("buf_len: %d\n", buf_len);
// printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
// PrivTaskDelay(1000);
memset(recv_buf, 0, sizeof(recv_buf));
printf("set_server: %s\n", set_server);
printf("set_server_len: %d\n", strlen(set_server));
PrivWrite(quectel_fd, set_server, strlen(set_server));
PrivTaskDelay(30);
buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
printf("buf_len: %d\n", buf_len);
printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
PrivTaskDelay(1000);
memset(recv_buf, 0, sizeof(recv_buf));
printf("set_conn: %s\n", set_conn);
printf("set_conn_len: %d\n", strlen(set_conn));
PrivWrite(quectel_fd, set_conn, strlen(set_conn));
PrivTaskDelay(30);
buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
printf("buf_len: %d\n", buf_len);
printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
PrivTaskDelay(1000);
while (1) {
printf("start send\n");
char set_reply[50] = {"AT+QMTPUBEX=0,0,0,0,\"/reply\","};
char data_len_str[20];
sprintf(data_len_str, "%d", strlen(trans_data));
printf("data_len_str: %s\n", data_len_str);
strcat(set_reply, data_len_str);
strcat(set_reply, "\r\n");
memset(recv_buf, 0, sizeof(recv_buf));
printf("set_reply: %s\n", set_reply);
printf("set_reply_len: %d\n", strlen(set_reply));
PrivWrite(quectel_fd, set_reply, strlen(set_reply));
PrivTaskDelay(30);
buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
printf("buf_len: %d\n", buf_len);
printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
PrivTaskDelay(500);
memset(recv_buf, 0, sizeof(recv_buf));
printf("send_data: %s\n", trans_data);
printf("send_data_len: %d\n", strlen(trans_data));
PrivWrite(quectel_fd, trans_data, strlen(trans_data));
PrivTaskDelay(30);
buf_len = PrivRead(quectel_fd, recv_buf, sizeof(recv_buf));
printf("buf_len: %d\n", buf_len);
printf("[%s] Info: Recv from uart: %s\n", __func__, recv_buf);
PrivTaskDelay(5000);
}
PrivClose(quectel_fd);
return;
}
PRIV_SHELL_CMD_FUNCTION(Test4G, a quectel test sample, PRIV_SHELL_CMD_MAIN_ATTR);
#endif

7
APP_Framework/Applications/ota/Kconfig Executable file → Normal file
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@ -1,7 +0,0 @@
menu "ota app "
menuconfig APPLICATION_OTA
bool "Using app bin ota"
default n
endmenu

19
APP_Framework/Applications/ota/README.md
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@ -1,19 +0,0 @@
# OTA README
xiuos当前的ota功能允许应用bin文件可以通过4G实现远程的bin文件更新（限制：1、bin文件存放在设备SD卡并且应用从SD卡启动；2、暂且支持4G实现；3、暂时只支持aiit终端;4、只支持xiuos内核）。
## 文件说明
| 名称 | 说明 |
| -- | -- |
| ota.c| xiuos设备OTA代码 |
| ota_server.c | pc服务端的实例代码供参考 |
## 使用说明
xiuos的应用bin文件更新依赖上层的adapter框架，因此需要在menuconfig同时配置以下选项：
1、ota开关APPLICATION_OTA打开；
2、adapter的4G功能开关；
3、拆分的应用启动SEPARATE_COMPILE开关从SD卡启动的配置开关APP_STARTUP_FROM_SDCARD。

1217
APP_Framework/Applications/ota/ota.c
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File diff suppressed because it is too large Load Diff

0
Ubiquitous/XiZi_IIoT/tool/bootloader/ota/ota.h → APP_Framework/Applications/ota/ota.h
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385
APP_Framework/Applications/ota/ota_server.c
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@ -1,385 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file: ota_server.c
* @brief: a application ota task of system running in Linux
* @version: 1.0
* @author: AIIT XUOS Lab
* @date: 2021/11/3
*
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <sys/socket.h>
#include <pthread.h>
#include <time.h>
#include <sys/types.h>
#include <errno.h>
#include <sys/time.h>
#include <assert.h>
#include <netdb.h>
#include <sys/stat.h>
#include <fcntl.h>
typedef int BOOL;
#define true 1
#define false 0
int serverfd;//服务器socket
int clientfd[100000];//客户端的socketfd,100个元素，clientfd[0]~clientfd[99]
int size = 99999;//用来控制进入聊天室的人数为50以内
int PORT = 9898;//端口号
typedef struct sockaddr meng;
struct ota_header_t
{
int16_t frame_flag; ///< frame start flag 2 Bytes
uint8_t dev_type; ///< device type
uint8_t burn_mode; ///< data burn way
uint32_t total_len; ///< send data total length caculated from each frame_len
uint32_t dev_hid; ///< device hardware version
uint32_t dev_sid; ///< device software version
char resv[8]; ///< reserve
};
struct ota_frame_t
{
uint32_t frame_id; ///< Current frame id
uint32_t frame_len; ///< Current frame data length
char frame_data[64]; ///< Current frame data,max length 224
uint32_t crc; ///< Current frame data crc
};
struct ota_data
{
struct ota_header_t header;
struct ota_frame_t frame;
char end[4];
};
pthread_t ota_ktask;
/**
* @description: CRC16 check
* @param data data buffer
* @param length data length
* @return check code
*/
uint32_t OtaCrc16(uint8_t * data, uint32_t length)
{
int j;
unsigned int reg_crc=0xFFFF;
printf("crc data length[%d] Bytes,",length);
while (length--) {
reg_crc ^= *data++;
for (j=0;j<8;j++) {
if(reg_crc & 0x01)
reg_crc=reg_crc >>1 ^ 0xA001;
else
reg_crc=reg_crc >>1;
}
}
printf(" crc = [0x%x]\n",reg_crc);
return reg_crc;
}
void init(void)
{
serverfd = socket(PF_INET,SOCK_STREAM,0);
if (serverfd == -1)
{
perror("创建socket失败");
exit(-1);
}
//为套接字设置ip协议 设置端口号 并自动获取本机ip转化为网络ip
struct sockaddr_in addr;//存储套接字的信息
addr.sin_family = AF_INET;//地址族
addr.sin_port = htons(PORT);//设置server端端口号，你可以随便设置,当sin_port = 0时，系统随机选择一个未被使用的端口号
addr.sin_addr.s_addr = htons(INADDR_ANY);//当sin_addr = INADDR_ANY时，表示从本机的任一网卡接收数据
//绑定套接字
// int on = 1;
struct timeval timeout;
timeout.tv_sec = 5;
timeout.tv_usec = 0;
if(setsockopt(serverfd, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(struct timeval)) < 0)
{
perror("端口设置失败");
exit(-1);
}
if (bind(serverfd,(meng*)&addr,sizeof(addr)) == -1)
{
perror("绑定失败");
exit(-1);
}
if (listen(serverfd,100) == -1)
{//监听最大连接数
perror("设置监听失败");
exit(-1);
}
}
int OtaFileSend(int fd)
{
unsigned char buf[32] = { 0 };
struct ota_data data;
FILE *file_fd;
char ch;
int length = 0;
int try_times = 10;
int recv_end_times = 3;
int ret = 0;
int frame_cnt = 0;
int file_length = 0;
char * file_buf = NULL;
file_fd = fopen("/home/aep04/wwg/XiUOS_aiit-arm32-board_app.bin", "r");
if (NULL == file_fd){
printf("open file failed.\n");
return -1;
}
fseek(file_fd, 0, SEEK_SET);
printf("start send file.\n");
while(!feof(file_fd))
{
memset(&data, 0, sizeof(data));
data.header.frame_flag = 0x5A5A;
length = fread( data.frame.frame_data, 1, 64, file_fd );
if(length > 0)
{
printf("read %d Bytes\n",length);
data.frame.frame_id = frame_cnt;
data.frame.frame_len = length;
data.frame.crc = OtaCrc16(data.frame.frame_data, length);
file_length += length;
}
send_again:
usleep(50000);
printf("ota send current[%d] frame.\n",frame_cnt);
length = send(fd, &data, sizeof(data), MSG_NOSIGNAL);
if(length < 0){
printf("send [%d] frame faile.go to send again\n",frame_cnt);
goto send_again;
}
recv_again:
memset(buf, 0, 32);
length = recv(fd, buf, sizeof(buf), 0);
if(length < 0 ){
printf("[%d] frame waiting for ok timeout,receive again.\n",frame_cnt);
goto recv_again;
}
printf("receive buf[%s] length = %d\n",buf, length);
if(0 == strncmp(buf, "ok", length))
{
try_times = 10;
printf("[%d]frame data send done.\n",frame_cnt);
frame_cnt++;
continue;
}
else
{
if(try_times > 0)
{
try_times--;
goto send_again;
}
else
{
printf("send frame[%d] 10 times failed.\n",frame_cnt);
ret = -1;
break;
}
}
}
/* finally,crc check total bin file.*/
if (ret == 0)
{
sleep(1);
printf("total send file length[%d] Bytes [%d] frames.\n",file_length,frame_cnt);
printf("now crc check total bin file.\n");
file_buf = malloc(file_length);
memset(file_buf, 0, file_length);
memset(&data, 0, sizeof(data));
data.header.frame_flag = 0x5A5A;
file_fd = fopen("/home/aep04/wwg/XiUOS_aiit-arm32-board_app.bin", "r");
if (NULL == file_fd){
printf("open file failed.\n");
return -1;
}
fseek(file_fd, 0, SEEK_SET);
length = fread(file_buf,1, file_length, file_fd);
printf("read file length = %d\n",length);
if(length > 0) {
data.frame.frame_id = frame_cnt;
data.header.total_len = file_length;
data.frame.frame_len = strlen("aiit_ota_end");
data.frame.crc = OtaCrc16(file_buf, length);
memcpy(data.frame.frame_data,"aiit_ota_end",strlen("aiit_ota_end"));
}
send_end_signal:
printf("send aiit_ota_end signal.\n");
length = send(fd, &data, sizeof(data), MSG_NOSIGNAL);
if(length < 0){
printf("send end signal faile,send end signal again\n");
goto send_end_signal;
}
recv_end_signal:
memset(buf, 0, 32);
length = recv(fd, buf, sizeof(buf), 0);
if(length < 0 )
{
recv_end_times--;
printf("end signal waiting for ok timeout,receive again.\n");
if(recv_end_times > 0)
{
goto recv_end_signal;
}
else
{
ret = -1;
}
}
if(0 != strncmp(buf, "ok", length))
{
printf("error end !!!\n");
ret = -1;
}
free(file_buf);
}
fclose(file_fd);
return ret;
}
void* server_thread(void* p)
{
int fd = *(int*)p;
unsigned char buf[32] = { 0 };
struct ota_data data;
int ret = 0;
int length = 0;
printf("pthread = %d\n",fd);
sleep(8);
while(1)
{
memset(&data, 0x0 , sizeof(struct ota_data));
data.header.frame_flag = 0x5A5A;
memcpy(data.frame.frame_data,"aiit_ota_start",strlen("aiit_ota_start"));
data.frame.frame_len = strlen("aiit_ota_start");
printf("send start signal.\n");
ret = send(fd, &data, sizeof(data), MSG_NOSIGNAL);
if (ret > 0){
printf("send %s[%d] Bytes\n",data.frame.frame_data,ret);
}
// sleep(1);
memset(buf, 0, 32);
length = recv(fd, buf, sizeof(buf), 0);
if (length <= 0)
{
continue;
}
else
{
printf("recv buf %s length %d\n",buf,length);
if(0 == strncmp(buf, "ready", length))
{
ret = OtaFileSend(fd);
if (ret == 0) {
printf("ota file send successful.\n");
break;
} else { /* ota failed then restart the ota process */
continue;
}
}
}
}
printf("exit fd = %d\n",fd);
close(fd);
pthread_exit(0);
}
void server(void)
{
printf("ota Server startup\n");
while(1)
{
struct sockaddr_in fromaddr;
socklen_t len = sizeof(fromaddr);
int fd = accept(serverfd,(meng*)&fromaddr,&len);
//调用accept进入堵塞状态，等待客户端的连接
if (fd == -1)
{
// printf("The client connection is wrong...\n");
continue;
}
int i = 0;
for (i = 0;i < size;i++)
{
if (clientfd[i] == 0)
{
//记录客户端的socket
clientfd[i] = fd;
//有客户端连接之后，启动线程给此客户服务
pthread_t tid;
pthread_create(&tid,0,server_thread,&fd);
break;
}
if (size == i)
{
//发送给客户端说聊天室满了
char* str = "Devices full";
printf("%s", str);
send(fd,str,strlen(str),0);
close(fd);
}
}
}
}
int main(void)
{
init();
server();
}

0
Ubiquitous/XiZi_IIoT/tool/bootloader/ota/server_tcp.c → APP_Framework/Applications/ota/server_tcp.c
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2
Ubiquitous/XiZi_IIoT/Makefile
View File

@ -6,7 +6,7 @@ MAKEFLAGS += --no-print-directory
riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64 edu-riscv64 ch32v307vct6 riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64 edu-riscv64 ch32v307vct6
arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32 xiwangtong-arm32 edu-arm32 arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32 xiwangtong-arm32 edu-arm32 xishutong-arm32
emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator cortex-m7-emulator emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator cortex-m7-emulator
support := $(riscv_support) $(arm_support) $(emulator_support) support := $(riscv_support) $(arm_support) $(emulator_support)

5
Ubiquitous/XiZi_IIoT/arch/arm/Makefile
View File

@ -30,6 +30,11 @@ SRC_DIR := shared
SRC_DIR += cortex-m4 SRC_DIR += cortex-m4
endif endif
ifeq ($(CONFIG_BOARD_XISHUTONG_ARM32),y)
SRC_DIR := shared
SRC_DIR += cortex-m4
endif
ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y) ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y)
SRC_DIR := shared SRC_DIR := shared
SRC_DIR += cortex-m7 SRC_DIR += cortex-m7

4
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m4/Makefile
View File

@ -18,4 +18,8 @@ ifeq ($(CONFIG_BOARD_EDU_ARM32_EVB),y)
SRC_DIR += hc32f4a0 SRC_DIR += hc32f4a0
endif endif
ifeq ($(CONFIG_BOARD_XISHUTONG_ARM32),y)
SRC_DIR += hc32f4a0
endif
include $(KERNEL_ROOT)/compiler.mk include $(KERNEL_ROOT)/compiler.mk

10
Ubiquitous/XiZi_IIoT/board/edu-arm32/third_party_driver/sdio/connect_sdio.c
View File

@ -229,11 +229,13 @@ static void SdCardAttach(void)
KPrintf("\r\nCard inserted.\r\n"); KPrintf("\r\nCard inserted.\r\n");
int err_code = LL_OK;
/* Reset and init SDIOC */ /* Reset and init SDIOC */
if (LL_OK != SDIOC_SWReset(sd_handle->SDIOCx, SDIOC_SW_RST_ALL)) { if (LL_OK != (err_code = SDIOC_SWReset(sd_handle->SDIOCx, SDIOC_SW_RST_ALL))) {
KPrintf("Reset SDIOC failed!\r\n"); KPrintf("Reset SDIOC failed! error code: %d\r\n", err_code);
} else if (LL_OK != SD_Init(sd_handle)) { } else if (LL_OK != (err_code = SD_Init(sd_handle))) {
KPrintf("SD card initialize failed!\r\n"); KPrintf("SD card initialize failed!, error code: %d\r\n", err_code);
} else { } else {
KPrintf("SD card init done!\r\n"); KPrintf("SD card init done!\r\n");
} }

0
Ubiquitous/XiZi_IIoT/tool/bootloader/flash/Kconfig → Ubiquitous/XiZi_IIoT/board/xidatong-arm32/third_party_driver/ota/Kconfig
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0
Ubiquitous/XiZi_IIoT/tool/bootloader/flash/flash_ops.c → Ubiquitous/XiZi_IIoT/board/xidatong-arm32/third_party_driver/ota/Makefile
View File

0
Ubiquitous/XiZi_IIoT/tool/bootloader/ota/Kconfig → Ubiquitous/XiZi_IIoT/board/xidatong-arm32/third_party_driver/ota/boot_for_ota.c
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0
Ubiquitous/XiZi_IIoT/board/xidatong-arm32/third_party_driver/ota/flash_for_ota.c Normal file
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261
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/.defconfig Normal file
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@ -0,0 +1,261 @@
#
# Automatically generated file; DO NOT EDIT.
# XiZi_IIoT Project Configuration
#
CONFIG_BOARD_EDU_ARM32_EVB=y
CONFIG_ARCH_ARM=y
#
# hc32f4a0 feature
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART3=y
CONFIG_SERIAL_BUS_NAME_3="usart3"
CONFIG_SERIAL_DRV_NAME_3="usart3_drv"
CONFIG_SERIAL_3_DEVICE_NAME_0="usart3_dev3"
CONFIG_BSP_USING_UART6=y
CONFIG_SERIAL_BUS_NAME_6="usart6"
CONFIG_SERIAL_DRV_NAME_6="usart6_drv"
CONFIG_SERIAL_6_DEVICE_NAME_0="usart6_dev6"
#
# config default board resources
#
#
# config board app name
#
CONFIG_BOARD_APP_NAME="/XiUOS_edu_arm32_app.bin"
#
# Hardware feature
#
CONFIG_RESOURCES_SERIAL=y
CONFIG_SERIAL_USING_DMA=y
CONFIG_SERIAL_RB_BUFSZ=128
#
# Kernel feature
#
#
# separate compile(choose none for compile once)
#
# CONFIG_SEPARATE_COMPILE is not set
# CONFIG_COMPILER_APP is not set
# CONFIG_APP_STARTUP_FROM_SDCARD is not set
CONFIG_APP_STARTUP_FROM_FLASH=y
# CONFIG_COMPILER_KERNEL is not set
#
# Memory Management
#
# CONFIG_KERNEL_MEMBLOCK is not set
CONFIG_MEM_ALIGN_SIZE=8
# CONFIG_MEM_EXTERN_SRAM is not set
CONFIG_MM_PAGE_SIZE=4096
#
# Using small memory allocator
#
CONFIG_KERNEL_SMALL_MEM_ALLOC=y
CONFIG_SMALL_NUMBER_32B=64
CONFIG_SMALL_NUMBER_64B=32
#
# Task feature
#
CONFIG_USER_APPLICATION=y
# CONFIG_TASK_ISOLATION is not set
#
# Inter-Task communication
#
CONFIG_KERNEL_SEMAPHORE=y
CONFIG_KERNEL_MUTEX=y
CONFIG_KERNEL_EVENT=y
CONFIG_KERNEL_MESSAGEQUEUE=y
CONFIG_KERNEL_SOFTTIMER=y
CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
# CONFIG_SCHED_POLICY_RR is not set
# CONFIG_SCHED_POLICY_FIFO is not set
# CONFIG_KTASK_PRIORITY_8 is not set
CONFIG_KTASK_PRIORITY_32=y
# CONFIG_KTASK_PRIORITY_256 is not set
CONFIG_KTASK_PRIORITY_MAX=32
CONFIG_TICK_PER_SECOND=1000
CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
CONFIG_IDLE_KTASK_STACKSIZE=1024
CONFIG_ZOMBIE_KTASK_STACKSIZE=2048
#
# Kernel Console
#
CONFIG_KERNEL_CONSOLE=y
CONFIG_KERNEL_BANNER=y
CONFIG_KERNEL_CONSOLEBUF_SIZE=128
#
# Kernel Hook
#
# CONFIG_KERNEL_HOOK is not set
#
# Command shell
#
CONFIG_TOOL_SHELL=y
CONFIG_SHELL_ENTER_CR=y
CONFIG_SHELL_ENTER_LF=y
CONFIG_SHELL_ENTER_CR_AND_LF=y
# CONFIG_SHELL_ENTER_CRLF is not set
#
# Set shell user control
#
CONFIG_SHELL_DEFAULT_USER="letter"
CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
CONFIG_SHELL_LOCK_TIMEOUT=10000
#
# Set shell config param
#
CONFIG_SHELL_TASK_STACK_SIZE=4096
CONFIG_SHELL_TASK_PRIORITY=20
CONFIG_SHELL_MAX_NUMBER=5
CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
CONFIG_SHELL_HISTORY_MAX_NUMBER=5
CONFIG_SHELL_PRINT_BUFFER=128
CONFIG_SHELL_HELP_SHOW_PERMISSION=y
# CONFIG_SHELL_HELP_LIST_USER is not set
CONFIG_SHELL_HELP_LIST_VAR=y
# CONFIG_SHELL_HELP_LIST_KEY is not set
#
# Kernel data structure Manage
#
CONFIG_KERNEL_QUEUEMANAGE=y
CONFIG_KERNEL_WORKQUEUE=y
CONFIG_WORKQUEUE_KTASK_STACKSIZE=2048
CONFIG_WORKQUEUE_KTASK_PRIORITY=23
CONFIG_QUEUE_MAX=16
CONFIG_KERNEL_WAITQUEUE=y
CONFIG_KERNEL_DATAQUEUE=y
# CONFIG_KERNEL_CIRCULAR_AREA is not set
# CONFIG_KERNEL_AVL_TREE is not set
#
# Kernel components init
#
CONFIG_KERNEL_COMPONENTS_INIT=y
CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048
CONFIG_KERNEL_USER_MAIN=y
CONFIG_NAME_NUM_MAX=32
# CONFIG_KERNEL_DEBUG is not set
# CONFIG_ARCH_SMP is not set
#
# hash table config
#
CONFIG_ID_HTABLE_SIZE=16
CONFIG_ID_NUM_MAX=128
# CONFIG_KERNEL_TEST is not set
#
# Lib
#
CONFIG_LIB=y
CONFIG_LIB_POSIX=y
CONFIG_LIB_NEWLIB=y
# CONFIG_LIB_MUSLLIB is not set
#
# C++ features
#
# CONFIG_LIB_CPLUSPLUS is not set
#
# File system
#
CONFIG_FS_VFS=y
CONFIG_VFS_USING_WORKDIR=y
CONFIG_FS_VFS_DEVFS=y
CONFIG_FS_VFS_FATFS=y
# CONFIG_FS_CH376 is not set
# CONFIG_FS_LWEXT4 is not set
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FEATURES=y
# CONFIG_ADD_NUTTX_FEATURES is not set
# CONFIG_ADD_RTTHREAD_FEATURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
CONFIG_MAIN_KTASK_PRIORITY=16
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
# CONFIG_APPLICATION_SENSOR is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
# CONFIG_APP_USING_WEBNET is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
#
# LVGL configuration
#
# CONFIG_LV_CONF_MINIMAL is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

43
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/Kconfig Normal file
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mainmenu "XiZi_IIoT Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_XISHUTONG_ARM32
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "xishutong-arm32 feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_xishutong_arm32_app.bin"
endmenu
endmenu
config MOUNT_SDCARD
bool
default n
config MOUNT_USB
bool
default n
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

5
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/Makefile Normal file
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SRC_FILES := board.c
SRC_DIR := third_party_driver
include $(KERNEL_ROOT)/compiler.mk

172
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/README.md Normal file
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# 从零开始构建矽璓工业物联操作系统：使用ARM架构的xishutong-arm32开发板
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。
## 开发环境搭建
### 推荐使用：
**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
第一步:打开sources.list文件
```c
sudo vim /etc/apt/sources.list
```
第二步:将以下内容复制到sources.list文件
```c
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
```
第三步:更新源和系统软件
```c
sudo apt-get update
sudo apt-get upgrade
```
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
### 依赖包安装：
```
$ sudo apt install build-essential pkg-config git
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
```
**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
```c
mkdir test && cd test
git clone https://gitlink.org.cn/xuos/xiuos.git
```
1、打开XiUOS源码文件包可以看到以下目录：
| 名称 | 说明 |
| -- | -- |
| APP_Framework | 应用代码 |
| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
2、打开XiZi内核源码文件包可以看到以下目录：
| 名称 | 说明 |
| -- | -- |
| arch | 架构代码 |
| board | 板级支持包 |
| fs | 文件系统 |
| kernel | 内核源码 |
| lib | 第三方库源码 |
| resources | 驱动文件 |
| tool | 系统工具 |
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境
### 裁减配置工具的下载
裁减配置工具：
**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
```c
mkdir kfrontends && cd kfrontends
git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
```
下载源码后按以下步骤执行软件安装：
```c
cd kconfig-frontends
./xs_build.sh
```
### 编译工具链：
ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
```shell
$ sudo apt install gcc-arm-none-eabi
```
# 在xishutong-arm32上创建第一个应用 --helloworld
## 1. 简介
| 硬件 | 描述 |
| -- | -- |
|芯片型号| HC32F4A0SITB|
|CPU|arm cortex-m4|
|主频| 240MHz |
|片内SRAM| 512KB |
|片上FLASH| 2MB |
| 外设 | -- |
| | ADC、PGA、DAC、CMP、PWM、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I2C、WDT、Timer等 |
XiUOS板级驱动当前支持使用UART。
## 2. 编译说明
### 编辑环境：`Ubuntu18.04`
### 编译工具链：`arm-none-eabi-gcc`
使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
修改`APP_Framework/Applications`文件夹下`main.c`
在输出函数中写入 `Hello, world!!! \n`完成代码编辑。
编译步骤：
1.在VScode命令终端中执行以下命令，生成配置文件
```c
cd ./Ubiquitous/XiZi
make BOARD=xishutong-arm32 distclean
make BOARD=xishutong-arm32 menuconfig
```
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
![menuconfig1](img/menuconfig1.png)
退出时选择`yes`保存上面所配置的内容，如下图所示：
![menuconfig2](img/menuconfig2.png)
3.继续执行以下命令，进行编译
```c
make BOARD=xishutong-arm32
```
4.如果编译正确无误，会产生XiZi-xishutong-arm32.elf、XiZi-xishutong-arm32.bin文件。其中XiZi-xishutong-arm32.bin需要烧写到设备中进行运行。
## 3. 烧写及执行
### 3.1 烧写
将BOARD=xishutong-arm32开发板通过TYPE-C接口转接到PC，然后使用华大官方HDSC ISP工具进行烧写bin文件。
1、烧写工具：HDSC ISP，可参考[https://www.hdsc.com.cn/Category83-1496](https://www.hdsc.com.cn/Category83-1496)
2、烧录bin文件前，需要将开发板boot引脚拉高，上电后再按下reset按键，方可进入BOOT MODE。
3、打开HDSC ISP工具后，选择芯片类型、通信波特率、bin文件路径和对应串口，如step1中所示。之后勾选擦除、空白检测、编程选项，点击执行，如step2中所示。若烧写无误，则如step3提示验证成功，代表烧录文件完成。
![HDSC_ISP](img/HDSC_ISP.png)
### 3.2 运行结果
如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端TYPE-C串口引脚为UART3)。
![terminal](img/terminal.png)

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/board.c Normal file
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support xishutong-arm32-board init configure and start-up
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-09-08
*/
/*************************************************
File name: board.c
Description: support xishutong-arm32-board init configure and driver/task/... init
Others:
History:
1. Date: 2022-09-08
Author: AIIT XUOS Lab
Modification:
1. support xishutong-arm32-board InitBoardHardware
*************************************************/
#include <board.h>
#include <connect_usart.h>
#include <hc32_ll.h>
#include <xizi.h>
#ifdef BSP_USING_GPIO
#include <connect_gpio.h>
#endif
#ifdef BSP_USING_ADC
#include <connect_adc.h>
#endif
#ifdef BSP_USING_DAC
#include <connect_dac.h>
#endif
#ifdef BSP_USING_SDIO
#include <connect_sdio.h>
#endif
#ifdef BSP_USING_SPI
#include <connect_spi.h>
#endif
#ifdef BSP_USING_I2C
#include <connect_i2c.h>
#endif
#ifdef BSP_USING_USB
#include <connect_usb.h>
#endif
#ifdef BSP_USING_RTC
#include <connect_rtc.h>
#endif
#ifdef BSP_USING_WDT
#include <connect_wdt.h>
#endif
#ifdef BSP_USING_TIMER
#include <connect_hwtimer.h>
#endif
#ifdef BSP_USING_CAN
#include <connect_can.h>
#endif
#ifdef BSP_USING_LWIP
#include <connect_ethernet.h>
#endif
extern void entry(void);
extern int HwUsartInit();
/* Peripheral register WE/WP selection */
#define LL_PERIPH_SEL (LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_EFM | LL_PERIPH_SRAM)
void SystemClockConfig(void)
{
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcPLLHInit;
CLK_SetClockDiv(CLK_BUS_CLK_ALL,
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | CLK_HCLK_DIV1));
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit);
(void)CLK_PLLStructInit(&stcPLLHInit);
stcPLLHInit.u8PLLState = CLK_PLL_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
#ifdef BSP_USING_USB
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
#else
/* VCO = (8/1)*100 = 800MHz*/
stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
#endif
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
(void)CLK_PLLInit(&stcPLLHInit);
#ifdef BSP_USING_USB
/* Highspeed SRAM set to 0 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
#else
/* Highspeed SRAM set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE2, SRAM_WAIT_CYCLE2);
#endif
/* 0-wait @ 40MHz */
EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
/* 4 cycles for 200 ~ 250MHz */
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
}
void PeripheralClockConfig(void)
{
#if defined(BSP_USING_CAN1)
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
#endif
#if defined(BSP_USING_CAN2)
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
#endif
#if defined(BSP_USING_ADC)
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
#endif
}
void SysTickConfiguration(void)
{
stc_clock_freq_t stcClkFreq;
uint32_t cnts;
CLK_GetClockFreq(&stcClkFreq);
cnts = (uint32_t)stcClkFreq.u32HclkFreq / TICK_PER_SECOND;
SysTick_Config(cnts);
}
void SysTick_Handler(void)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
TickAndTaskTimesliceUpdate();
ENABLE_INTERRUPT(lock);
}
struct InitSequenceDesc _board_init[] = {
#ifdef BSP_USING_GPIO
{ "hw_pin", HwGpioInit },
#endif
#ifdef BSP_USING_SDIO
{ "sdio", HwSdioInit },
#endif
#ifdef BSP_USING_SPI
{ "spi", HwSpiInit },
#endif
#ifdef BSP_USING_I2C
{ "i2c", HwI2cInit },
#endif
#ifdef BSP_USING_ADC
{ "hw adc init", HwAdcInit },
#endif
#ifdef BSP_USING_DAC
{ "hw dac init", HwDacInit },
#endif
#ifdef BSP_USING_USB
{ "usb", HwUsbHostInit },
#endif
#ifdef BSP_USING_RTC
{ "rtc", HwRtcInit },
#endif
#ifdef BSP_USING_WDT
{ "wdt", HwWdtInit },
#endif
#ifdef BSP_USING_TIMER
{ "tmr", HwTimerInit },
#endif
#ifdef BSP_USING_CAN
{ "can", HwCanInit },
#endif
#ifdef BSP_USING_LWIP
{ "wiz", HwWiznetInit },
#endif
{ " NONE ", NONE },
};
void InitBoardHardware()
{
int i = 0;
int ret = 0;
/* MCU Peripheral registers write unprotected */
LL_PERIPH_WE(LL_PERIPH_SEL);
SystemClockConfig();
PeripheralClockConfig();
SysTickConfiguration();
#ifdef BSP_USING_UART
HwUsartInit();
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
for (i = 0; _board_init[i].fn != NONE; i++) {
ret = _board_init[i].fn();
KPrintf("initialize %s %s\n", _board_init[i].fn_name, ret == 0 ? "success" : "failed");
}
KPrintf("board init done.\n");
KPrintf("start kernel...\n");
}

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define xishutong-arm32-board init configure and start-up function
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-09-08
*/
/*************************************************
File name: board.h
Description: define xishutong-arm32-board board init function and struct
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. define xishutong-arm32-board InitBoardHardware
2. define xishutong-arm32-board data and bss struct
*************************************************/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
extern int __heap_start;
extern unsigned int g_service_table_start;
extern unsigned int g_service_table_end;
#define MEMORY_START_ADDRESS (&__heap_start)
#define HC32F4_SRAM_SIZE 512
#define MEMORY_END_ADDRESS (0x1FFE0000 + HC32F4_SRAM_SIZE * 1024)
void InitBoardHardware(void);
#endif

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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O2 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
# export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-xishutong-arm32.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O2 -Werror
# export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
export APPLFLAGS :=
export DEFINES := -DHAVE_CCONFIG_H -DHC32F4A0 -DUSE_DDL_DRIVER -DHAVE_SIGINFO
ifeq ($(CONFIG_RESOURCES_LWIP), y)
export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
endif
export ARCH = arm

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/**
*******************************************************************************
* @file system_hc32f4a0.h
* @brief This file contains all the functions prototypes of the HC32 System.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __SYSTEM_HC32F4A0_H__
#define __SYSTEM_HC32F4A0_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stdint.h>
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F4A0_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Macros
* @{
*/
/**
* @addtogroup HC32F4A0_System_Clock_Source
* @{
*/
#if !defined (MRC_VALUE)
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
#endif
#if !defined (RTCLRC_VALUE)
#define RTCLRC_VALUE (32768UL) /*!< Internal RTC low speed RC freq. */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
#endif
#if !defined (HCLK_VALUE)
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Exported_Variable
* @{
*/
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @}
*/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Functions
* @{
*/
extern void SystemInit(void); /*!< Initialize the system */
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
#if defined (ROM_EXT_QSPI)
void SystemInit_QspiMem(void);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HC32F4A0_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*/
/*****************************************************************************/
/* File HC32F4A0xI.ld */
/* Abstract Linker script for HC32F4A0 Device with */
/* 2MByte FLASH, 516KByte RAM */
/* Version V1.0 */
/* Date 2022-04-28 */
/*****************************************************************************/
/**
* @file link.lds
* @brief hc32f4a0 Linker script
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-09-08
*/
/*************************************************
File name: link.lds
Description: hc32f4a0 Linker script
Others: take HC32F4A0xI.ld for references
History:
1. Date: 2022-09-08
Author: AIIT XUOS Lab
Modification:
1. add shell cmd table and g_service_table
*************************************************/
/* Custom defines, according to section 7.7 of the user manual.
Take OTP sector 16 for example. */
__OTP_DATA_START = 0x03000000;
__OTP_DATA_SIZE = 2048;
__OTP_LOCK_START = 0x03001840;
__OTP_LOCK_SIZE = 4;
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.interrupts :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
/* section information for shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP (*(shellCommand))
_shell_command_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))
PROVIDE(g_service_table_end = ABSOLUTE(.));
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_data_sec :
{
KEEP(*(.otp_data_sec))
} >OTP_DATA
.otp_lock_sec :
{
KEEP(*(.otp_lock_sec))
} >OTP_LOCK
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(.data)
*(.data*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
.ramb_data : AT (__etext_ramb)
{
. = ALIGN(4);
__data_start_ramb__ = .;
*(.ramb_data)
*(.ramb_data*)
. = ALIGN(4);
__data_end_ramb__ = .;
} >RAMB
__bss_start = .;
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
__bss_end = .;
.ramb_bss :
{
. = ALIGN(4);
__bss_start_ramb__ = .;
*(.ramb_bss)
*(.ramb_bss*)
. = ALIGN(4);
__bss_end_ramb__ = .;
} >RAMB
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
__heap_start = .;
} >RAM
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
}

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/CMSIS/include/cmsis_compiler.h Normal file
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.1
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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menuconfig BSP_USING_UART
bool "Using UART device"
default y
select RESOURCES_SERIAL
if BSP_USING_UART
source "$BSP_DIR/third_party_driver/usart/Kconfig"
endif
menuconfig BSP_USING_GPIO
bool "Using GPIO device "
default y
select RESOURCES_PIN
if BSP_USING_GPIO
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
endif
menuconfig BSP_USING_LWIP
bool "Using LwIP by ethernet device"
default n
select RESOURCES_LWIP
if BSP_USING_LWIP
source "$BSP_DIR/third_party_driver/ethernet/Kconfig"
endif
menuconfig BSP_USING_SDIO
bool "Using SD CARD device"
default n
select RESOURCES_SDIO
if BSP_USING_SDIO
source "$BSP_DIR/third_party_driver/sdio/Kconfig"
endif

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SRC_DIR += common
ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += usart
endif
ifeq ($(CONFIG_BSP_USING_GPIO),y)
SRC_DIR += gpio
endif
ifeq ($(CONFIG_BSP_USING_LWIP),y)
SRC_DIR += ethernet ethernet_wiz
endif
ifeq ($(CONFIG_BSP_USING_SDIO),y)
SRC_DIR += sdio
endif
include $(KERNEL_ROOT)/compiler.mk

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SRC_FILES := system_hc32f4a0.c hardware_irq.c
SRC_DIR := hc32_ll_driver
include $(KERNEL_ROOT)/compiler.mk

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/**
* @file hardware_irq.c
* @brief support xishutong-arm32-board irq configure
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-09-13
*/
/*************************************************
File name: hardware_irq.c
Description: support xishutong-arm32-board irq configure
Others:
History:
1. Date: 2022-09-13
Author: AIIT XUOS Lab
Modification:
1. support xishutong-arm32-board irq
*************************************************/
/*******************************************************************************
* Include files
******************************************************************************/
#include <hardware_irq.h>
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
x_err_t hc32_install_irq_handler(struct Hc32IrqConfig *irq_config,
void (*irq_hdr)(void),
x_bool irq_enable)
{
x_err_t result = -ERROR;
stc_irq_signin_config_t stcIrqSignConfig;
NULL_PARAM_CHECK(irq_config);
NULL_PARAM_CHECK(irq_hdr);
stcIrqSignConfig.enIRQn = irq_config->irq_num;
stcIrqSignConfig.enIntSrc = irq_config->int_src;
stcIrqSignConfig.pfnCallback = irq_hdr;
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) {
NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn);
NVIC_SetPriority(stcIrqSignConfig.enIRQn, irq_config->irq_prio);
if (irq_enable) {
NVIC_EnableIRQ(stcIrqSignConfig.enIRQn);
} else {
NVIC_DisableIRQ(stcIrqSignConfig.enIRQn);
}
result = EOK;
}
return result;
}
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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SRC_DIR := src
include $(KERNEL_ROOT)/compiler.mk

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/**
*******************************************************************************
* @file hc32_ll.h
* @brief This file contains HC32 Series Device Driver Library file call
* management.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_H__
#define __HC32_LL_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_Global
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup LL_Global_Macros LL Global Macros
* @{
*/
/**
* @defgroup Peripheral_Register_WP_Local_Macros Peripheral Register Write Protection Local Macros
* @{
*/
#define LL_PERIPH_EFM (1UL << 0U)
#define LL_PERIPH_FCG (1UL << 1U)
#define LL_PERIPH_GPIO (1UL << 2U)
#define LL_PERIPH_INTC (1UL << 3U)
#define LL_PERIPH_LVD (1UL << 4U)
#define LL_PERIPH_MPU (1UL << 5U)
#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U)
#define LL_PERIPH_SRAM (1UL << 7U)
#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \
LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU)
/**
* @}
*/
/* Defined use Device Driver Library */
#if !defined (USE_DDL_DRIVER)
/**
* @brief Comment the line below if you will not use the Device Driver Library.
* In this case, the application code will be based on direct access to
* peripherals registers.
*/
/* #define USE_DDL_DRIVER */
#endif /* USE_DDL_DRIVER */
/**
* @defgroup HC32_Series_DDL_Version HC32 Series Device Driver Library Version
* @{
*/
#define HC32_DDL_VER_MAIN 0x01U /*!< [31:24] main version */
#define HC32_DDL_VER_SUB1 0x00U /*!< [23:16] sub1 version */
#define HC32_DDL_VER_SUB2 0x00U /*!< [15:8] sub2 version */
#define HC32_DDL_VER_PATCH 0x00U /*!< [7:0] patch version */
#define HC32_DDL_VER ((HC32_DDL_VER_MAIN << 24) | (HC32_DDL_VER_SUB1 << 16) | \
(HC32_DDL_VER_SUB2 << 8 ) | (HC32_DDL_VER_PATCH))
/**
* @}
*/
/**
* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version
* @{
*/
#define HC32_DDL_REV_MAIN 0x02U /*!< [31:24] main version */
#define HC32_DDL_REV_SUB1 0x00U /*!< [23:16] sub1 version */
#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */
#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */
#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \
(HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH))
/**
* @}
*/
/**
* @}
*/
/* Use Device Driver Library */
#if defined (USE_DDL_DRIVER)
/**
* @brief Include peripheral module's header file
*/
#if (LL_ADC_ENABLE == DDL_ON)
#include "hc32_ll_adc.h"
#endif /* LL_ADC_ENABLE */
#if (LL_AES_ENABLE == DDL_ON)
#include "hc32_ll_aes.h"
#endif /* LL_AES_ENABLE */
#if (LL_AOS_ENABLE == DDL_ON)
#include "hc32_ll_aos.h"
#endif /* LL_AOS_ENABLE */
#if (LL_CAN_ENABLE == DDL_ON)
#include "hc32_ll_can.h"
#endif /* LL_CAN_ENABLE */
#if (LL_CLK_ENABLE == DDL_ON)
#include "hc32_ll_clk.h"
#endif /* LL_CLK_ENABLE */
#if (LL_CMP_ENABLE == DDL_ON)
#include "hc32_ll_cmp.h"
#endif /* LL_CMP_ENABLE */
#if (LL_CRC_ENABLE == DDL_ON)
#include "hc32_ll_crc.h"
#endif /* LL_CRC_ENABLE */
#if (LL_CTC_ENABLE == DDL_ON)
#include "hc32_ll_ctc.h"
#endif /* LL_CTC_ENABLE */
#if (LL_DAC_ENABLE == DDL_ON)
#include "hc32_ll_dac.h"
#endif /* LL_DAC_ENABLE */
#if (LL_DCU_ENABLE == DDL_ON)
#include "hc32_ll_dcu.h"
#endif /* LL_DCU_ENABLE */
#if (LL_DMA_ENABLE == DDL_ON)
#include "hc32_ll_dma.h"
#endif /* LL_DMA_ENABLE */
#if (LL_DMC_ENABLE == DDL_ON)
#include "hc32_ll_dmc.h"
#endif /* LL_DMC_ENABLE */
#if (LL_DVP_ENABLE == DDL_ON)
#include "hc32_ll_dvp.h"
#endif /* LL_DVP_ENABLE */
#if (LL_EFM_ENABLE == DDL_ON)
#include "hc32_ll_efm.h"
#endif /* LL_EFM_ENABLE */
#if (LL_EMB_ENABLE == DDL_ON)
#include "hc32_ll_emb.h"
#endif /* LL_EMB_ENABLE */
#if (LL_ETH_ENABLE == DDL_ON)
#include "hc32_ll_eth.h"
#endif /* LL_ETH_ENABLE */
#if (LL_EVENT_PORT_ENABLE == DDL_ON)
#include "hc32_ll_event_port.h"
#endif /* LL_EVENT_PORT_ENABLE */
#if (LL_FCG_ENABLE == DDL_ON)
#include "hc32_ll_fcg.h"
#endif /* LL_FCG_ENABLE */
#if (LL_FCM_ENABLE == DDL_ON)
#include "hc32_ll_fcm.h"
#endif /* LL_FCM_ENABLE */
#if (LL_FMAC_ENABLE == DDL_ON)
#include "hc32_ll_fmac.h"
#endif /* LL_FMAC_ENABLE */
#if (LL_GPIO_ENABLE == DDL_ON)
#include "hc32_ll_gpio.h"
#endif /* LL_GPIO_ENABLE */
#if (LL_HASH_ENABLE == DDL_ON)
#include "hc32_ll_hash.h"
#endif /* LL_HASH_ENABLE */
#if (LL_HRPWM_ENABLE == DDL_ON)
#include "hc32_ll_hrpwm.h"
#endif /* LL_HRPWM_ENABLE */
#if (LL_I2C_ENABLE == DDL_ON)
#include "hc32_ll_i2c.h"
#endif /* LL_I2C_ENABLE */
#if (LL_I2S_ENABLE == DDL_ON)
#include "hc32_ll_i2s.h"
#endif /* LL_I2S_ENABLE */
#if (LL_ICG_ENABLE == DDL_ON)
#include "hc32_ll_icg.h"
#endif /* LL_ICG_ENABLE */
#if (LL_INTERRUPTS_ENABLE == DDL_ON)
#include "hc32_ll_interrupts.h"
#endif /* LL_INTERRUPTS_ENABLE */
#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON)
#include "hc32f4a0_ll_interrupts_share.h"
#endif /* LL_INTERRUPTS_ENABLE */
#if (LL_KEYSCAN_ENABLE == DDL_ON)
#include "hc32_ll_keyscan.h"
#endif /* LL_KEYSCAN_ENABLE */
#if (LL_MAU_ENABLE == DDL_ON)
#include "hc32_ll_mau.h"
#endif /* LL_MAU_ENABLE */
#if (LL_MPU_ENABLE == DDL_ON)
#include "hc32_ll_mpu.h"
#endif /* LL_MPU_ENABLE */
#if (LL_NFC_ENABLE == DDL_ON)
#include "hc32_ll_nfc.h"
#endif /* LL_NFC_ENABLE */
#if (LL_OTS_ENABLE == DDL_ON)
#include "hc32_ll_ots.h"
#endif /* LL_OTS_ENABLE */
#if (LL_PWC_ENABLE == DDL_ON)
#include "hc32_ll_pwc.h"
#endif /* LL_PWC_ENABLE */
#if (LL_QSPI_ENABLE == DDL_ON)
#include "hc32_ll_qspi.h"
#endif /* LL_QSPI_ENABLE */
#if (LL_RMU_ENABLE == DDL_ON)
#include "hc32_ll_rmu.h"
#endif /* LL_RMU_ENABLE */
#if (LL_RTC_ENABLE == DDL_ON)
#include "hc32_ll_rtc.h"
#endif /* LL_RTC_ENABLE */
#if (LL_SDIOC_ENABLE == DDL_ON)
#include "hc32_ll_sdioc.h"
#endif /* LL_SDIOC_ENABLE */
#if (LL_SMC_ENABLE == DDL_ON)
#include "hc32_ll_smc.h"
#endif /* LL_SMC_ENABLE */
#if (LL_SPI_ENABLE == DDL_ON)
#include "hc32_ll_spi.h"
#endif /* LL_SPI_ENABLE */
#if (LL_SRAM_ENABLE == DDL_ON)
#include "hc32_ll_sram.h"
#endif /* LL_SRAM_ENABLE */
#if (LL_SWDT_ENABLE == DDL_ON)
#include "hc32_ll_swdt.h"
#endif /* LL_SWDT_ENABLE */
#if (LL_TMR0_ENABLE == DDL_ON)
#include "hc32_ll_tmr0.h"
#endif /* LL_TMR0_ENABLE */
#if (LL_TMR2_ENABLE == DDL_ON)
#include "hc32_ll_tmr2.h"
#endif /* LL_TMR2_ENABLE */
#if (LL_TMR4_ENABLE == DDL_ON)
#include "hc32_ll_tmr4.h"
#endif /* LL_TMR4_ENABLE */
#if (LL_TMR6_ENABLE == DDL_ON)
#include "hc32_ll_tmr6.h"
#endif /* LL_TMR6_ENABLE */
#if (LL_TMRA_ENABLE == DDL_ON)
#include "hc32_ll_tmra.h"
#endif /* LL_TMRA_ENABLE */
#if (LL_TRNG_ENABLE == DDL_ON)
#include "hc32_ll_trng.h"
#endif /* LL_TRNG_ENABLE */
#if (LL_USART_ENABLE == DDL_ON)
#include "hc32_ll_usart.h"
#endif /* LL_USART_ENABLE */
#if (LL_UTILITY_ENABLE == DDL_ON)
#include "hc32_ll_utility.h"
#endif /* LL_UTILITY_ENABLE */
#if (LL_USB_ENABLE == DDL_ON)
#include "hc32_ll_usb.h"
#endif /* LL_USB_ENABLE */
#if (LL_WDT_ENABLE == DDL_ON)
#include "hc32_ll_wdt.h"
#endif /* LL_WDT_ENABLE */
#endif /* USE_DDL_DRIVER */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup LL_Global_Functions
* @{
*/
void LL_PERIPH_WE(uint32_t u32Peripheral);
void LL_PERIPH_WP(uint32_t u32Peripheral);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_DDL_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32_ll_adc.h Normal file
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@ -0,0 +1,518 @@
/**
*******************************************************************************
* @file hc32_ll_adc.h
* @brief This file contains all the functions prototypes of the ADC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_ADC_H__
#define __HC32_LL_ADC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_ADC
* @{
*/
#if (LL_ADC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup ADC_Global_Types ADC Global Types
* @{
*/
/**
* @brief Structure definition of analog watchdog(AWD) configuration.
*/
typedef struct {
uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode.
This parameter can be a value of @ref ADC_AWD_Mode */
uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */
uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */
} stc_adc_awd_config_t;
/**
* @brief Structure definition of ADC initialization.
*/
typedef struct {
uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode.
This parameter can be a value of @ref ADC_Scan_Mode */
uint16_t u16Resolution; /*!< Specifies the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint16_t u16DataAlign; /*!< Specifies ADC data alignment.
This parameter can be a value of @ref ADC_Data_Align */
} stc_adc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup ADC_Global_Macros ADC Global Macros
* @{
*/
/**
* @defgroup ADC_Sequence ADC Sequence
* @{
*/
#define ADC_SEQ_A (0U) /*!< ADC sequence A. */
#define ADC_SEQ_B (1U) /*!< ADC sequence B. */
/**
* @}
*/
/**
* @defgroup ADC_Channel ADC Channel
* @{
*/
#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, ADC2 and ADC3. */
#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, ADC2 and ADC3. */
#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, ADC2 and ADC3. */
#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, ADC2 and ADC3. */
#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1 and ADC2, PF6 for ADC3. */
#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1 and ADC2, PF7 for ADC3. */
#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1 and ADC2, PF8 for ADC3. */
#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1 and ADC2, PF9 for ADC3. */
#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1 and ADC2, PF10 for ADC3. */
#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1 and ADC2, PF3 for ADC3. */
#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, ADC2 and ADC3. */
#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, ADC2 and ADC3. */
#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, ADC2 and ADC3. */
#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, ADC2 and ADC3. */
#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1 and ADC2, PF4 for ADC3. */
#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1 and ADC2, PF5 for ADC3. */
#define ADC_CH16 (16U) /*!< Default input pin: PH2 for ADC3, NOT support ADC1 and ADC2. */
#define ADC_CH17 (17U) /*!< Default input pin: PH3 for ADC3, NOT support ADC1 and ADC2. */
#define ADC_CH18 (18U) /*!< Default input pin: PH4 for ADC3, NOT support ADC1 and ADC2. */
#define ADC_CH19 (19U) /*!< Default input pin: PH5 for ADC3, NOT support ADC1 and ADC2. */
#define ADC_EXT_CH (ADC_CH15) /*!< ADC1, ADC2 and ADC3: analog input source can be external analog pin,
or internal reference voltage, or VBAT/2. */
/**
* @}
*/
/**
* @defgroup ADC_Scan_Mode ADC Scan Convert Mode
* @{
*/
#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */
#define ADC_MD_SEQA_CONT (ADC_CR0_MS_0) /*!< Sequence A continuous. Sequence B is disabled. */
#define ADC_MD_SEQA_SEQB_SINGLESHOT (ADC_CR0_MS_1) /*!< Sequence A and B both single shot. */
#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (ADC_CR0_MS) /*!< Sequence A continuous and sequence B single shot. */
/**
* @}
*/
/**
* @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */
#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */
#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */
/**
* @}
*/
/**
* @defgroup ADC_Data_Align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */
#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */
/**
* @}
*/
/**
* @defgroup ADC_Average_Count ADC Average Count
* @{
*/
#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */
#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */
#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */
#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */
#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */
#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */
#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */
#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */
/**
* @}
*/
/**
* @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode
* @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel.
* @{
*/
#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */
#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */
/**
* @}
*/
/**
* @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection
* @{
*/
#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */
#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence.
This event is specified by register ADCx_ITRGSELR0(x=(null), 1, 2, 3). */
#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence.
This event is specified by register ADCx_ITRGSELR1(x=(null), 1, 2, 3). */
#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence.
The two events are specified by register ADCx_ITRGSELR0 and register ADCx_ITRGSELR1. */
/**
* @}
*/
/**
* @defgroup ADC_Int_Type ADC Interrupt Type
* @{
*/
#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */
#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */
#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB)
/**
* @}
*/
/**
* @defgroup ADC_Ext_Ch_Analog_Src ADC Extended Channel Analog Source
* @{
*/
#define ADC_EXTCH_EXTERN_ANALOG_PIN (0x0U) /*!< The analog source of extended channel is external analog input pin. */
#define ADC_EXTCH_INTERN_ANALOG_SRC (ADC_EXCHSELR_EXCHSEL) /*!< The analog source of extended channel is internal analog signal. */
/**
* @}
*/
/**
* @defgroup ADC_Status_Flag ADC Status Flag
* @{
*/
#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */
#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */
#define ADC_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */
#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB | ADC_FLAG_NESTED)
/**
* @}
*/
/**
* @defgroup ADC_Sync_Unit ADC Synchronous Unit
* @{
*/
#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */
#define ADC_SYNC_ADC1_ADC2_ADC3 (ADC_SYNCCR_SYNCMD_0) /*!< ADC1, ADC2 and ADC3 work synchronously. */
/**
* @}
*/
/**
* @defgroup ADC_Sync_Mode ADC Synchronous Mode
* @{
*/
#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode.
When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
All ADCs scan once. */
#define ADC_SYNC_SINGLE_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode.
When the trigger condition occurs, all ADCs start at the same time.
All ADCs scan once. */
#define ADC_SYNC_CYCLIC_DELAY_TRIG (ADC_SYNCCR_SYNCMD_2) /*!< Cyclic delayed trigger mode.
When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
All ADCs scan cyclicly(keep scaning till you stop them). */
#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_2 | \
ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode.
When the trigger condition occurs, all ADCs start at the same time.
All ADCs scan cyclicly(keep scaning till you stop them). */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit
* @{
*/
#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */
#define ADC_AWD1 (1U) /*!< ADC analog watchdog 1. */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type
* @{
*/
#define ADC_AWD_INT_AWD0 (ADC_AWDCR_AWD0IEN) /*!< Interrupt of AWD0. */
#define ADC_AWD_INT_AWD1 (ADC_AWDCR_AWD1IEN) /*!< Interrupt of AWD1. */
#define ADC_AWD_INT_ALL (ADC_AWD_INT_AWD0 | ADC_AWD_INT_AWD1)
/**
* @}
*/
/**
* @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */
#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Comb_Mode ADC AWD(Analog Watchdog) Combination Mode
* @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and
* the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel
* of AWD1 is converted after the channel conversion of AWD0 ends.
* @{
*/
#define ADC_AWD_COMB_INVD (0U) /*!< Combination mode is invalid. */
#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */
#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */
#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag
* @{
*/
#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */
#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */
#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */
#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | ADC_AWD_FLAG_AWD1 | ADC_AWD_FLAG_COMB)
/**
* @}
*/
/**
* @defgroup ADC_PGA_Unit ADC PGA Unit
* @{
*/
#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input pin is ADC123_IN0. */
#define ADC_PGA2 (1U) /*!< PGA2, belongs to ADC1. Input pin is ADC123_IN1. */
#define ADC_PGA3 (2U) /*!< PGA3, belongs to ADC1. Input pin is ADC123_IN2. */
#define ADC_PGA4 (3U) /*!< PGA4, belongs to ADC2. Input pin is ADC12_IN6. */
/**
* @}
*/
/**
* @defgroup ADC_PGA_Gain ADC PGA Gain Factor
* @{
*/
#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */
#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */
#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */
#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */
#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */
#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */
#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */
#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */
#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */
#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */
#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */
#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */
#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */
#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */
#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */
/**
* @}
*/
/**
* @defgroup ADC_PGA_VSS ADC PGA VSS
* @{
*/
#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */
#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */
/**
* @}
*/
/**
* @defgroup ADC_Remap_Pin ADC Remap Pin
* @{
*/
#define ADC12_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC1 and ADC2 */
#define ADC12_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC1 and ADC2 */
#define ADC12_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC1 and ADC2 */
#define ADC12_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC1 and ADC2 */
#define ADC12_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1 and ADC2 */
#define ADC12_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1 and ADC2 */
#define ADC12_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1 and ADC2 */
#define ADC12_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1 and ADC2 */
#define ADC12_PIN_PB0 (8U) /*!< ADC12_IN8(PB0): default channel is ADC_CH8 of ADC1 and ADC2 */
#define ADC12_PIN_PB1 (9U) /*!< ADC12_IN9(PB1): default channel is ADC_CH9 of ADC1 and ADC2 */
#define ADC12_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC1 and ADC2 */
#define ADC12_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC1 and ADC2 */
#define ADC12_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC1 and ADC2 */
#define ADC12_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC1 and ADC2 */
#define ADC12_PIN_PC4 (14U) /*!< ADC12_IN14(PC4): default channel is ADC_CH14 of ADC1 and ADC2 */
#define ADC12_PIN_PC5 (15U) /*!< ADC12_IN15(PC5): default channel is ADC_CH15 of ADC1 and ADC2 */
#define ADC3_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC3 */
#define ADC3_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC3 */
#define ADC3_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC3 */
#define ADC3_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC3 */
#define ADC3_PIN_PF6 (4U) /*!< ADC3_IN4(PF6): default channel is ADC_CH4 of ADC3 */
#define ADC3_PIN_PF7 (5U) /*!< ADC3_IN5(PF7): default channel is ADC_CH5 of ADC3 */
#define ADC3_PIN_PF8 (6U) /*!< ADC3_IN6(PF8): default channel is ADC_CH6 of ADC3 */
#define ADC3_PIN_PF9 (7U) /*!< ADC3_IN7(PF9): default channel is ADC_CH7 of ADC3 */
#define ADC3_PIN_PF10 (8U) /*!< ADC3_IN8(PF10): default channel is ADC_CH8 of ADC3 */
#define ADC3_PIN_PF3 (9U) /*!< ADC3_IN9(PF3): default channel is ADC_CH9 of ADC3 */
#define ADC3_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC3 */
#define ADC3_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC3 */
#define ADC3_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC3 */
#define ADC3_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC3 */
#define ADC3_PIN_PF4 (14U) /*!< ADC3_IN14(PF4): default channel is ADC_CH14 of ADC3 */
#define ADC3_PIN_PF5 (15U) /*!< ADC3_IN15(PF5): default channel is ADC_CH15 of ADC3 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup ADC_Global_Functions
* @{
*/
/*******************************************************************************
Basic features
******************************************************************************/
int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit);
void ADC_DeInit(CM_ADC_TypeDef *ADCx);
int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit);
void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState);
void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime);
/* Conversion data average calculation function. */
void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount);
void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState);
/* Extended channel. */
void ADC_SetExtChSrc(CM_ADC_TypeDef *ADCx, uint8_t u8ExtChSrc);
void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel);
void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState);
void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState);
void ADC_Start(CM_ADC_TypeDef *ADCx);
void ADC_Stop(CM_ADC_TypeDef *ADCx);
uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
/*******************************************************************************
Advanced features
******************************************************************************/
/* Channel remap. */
void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin);
uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx);
/* Sync mode. */
void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay);
void ADC_SyncModeCmd(en_functional_state_t enNewState);
/* Analog watchdog */
int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd);
/* Combination mode. */
void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode);
void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode);
uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit);
void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold);
void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch);
void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState);
void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState);
en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
/* Sample hold */
void ADC_SH_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8SampleTime);
void ADC_SH_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState);
/* PGA */
void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss);
void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState);
void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState);
void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode);
/**
* @}
*/
#endif /* LL_ADC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_ADC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_aes.h
* @brief This file contains all the functions prototypes of the AES driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_AES_H__
#define __HC32_LL_AES_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_AES
* @{
*/
#if (LL_AES_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AES_Global_Macros AES Global Macros
* @{
*/
/**
* @defgroup AES_Key_Size AES Key Size
* @{
*/
#define AES_KEY_SIZE_16BYTE (16U)
#define AES_KEY_SIZE_24BYTE (24U)
#define AES_KEY_SIZE_32BYTE (32U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup AES_Global_Functions
* @{
*/
int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize,
const uint8_t *pu8Key, uint8_t u8KeySize,
uint8_t *pu8Ciphertext);
int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize,
const uint8_t *pu8Key, uint8_t u8KeySize,
uint8_t *pu8Plaintext);
/**
* @}
*/
#endif /* LL_AES_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_AES_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_aos.h
* @brief This file contains all the functions prototypes of the AOS driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_AOS_H__
#define __HC32_LL_AOS_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_AOS
* @{
*/
#if (LL_AOS_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AOS_Global_Macros AOS Global Macros
* @{
*/
/**
* @defgroup AOS_Trigger_Select AOS Trigger Select
* @{
*/
#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1)
#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2)
#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3)
#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4)
#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0)
#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1)
#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2)
#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3)
#define AOS_DMA1_4 (uint32_t)(&CM_AOS->DMA1_TRGSEL4)
#define AOS_DMA1_5 (uint32_t)(&CM_AOS->DMA1_TRGSEL5)
#define AOS_DMA1_6 (uint32_t)(&CM_AOS->DMA1_TRGSEL6)
#define AOS_DMA1_7 (uint32_t)(&CM_AOS->DMA1_TRGSEL7)
#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0)
#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1)
#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2)
#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3)
#define AOS_DMA2_4 (uint32_t)(&CM_AOS->DMA2_TRGSEL4)
#define AOS_DMA2_5 (uint32_t)(&CM_AOS->DMA2_TRGSEL5)
#define AOS_DMA2_6 (uint32_t)(&CM_AOS->DMA2_TRGSEL6)
#define AOS_DMA2_7 (uint32_t)(&CM_AOS->DMA2_TRGSEL7)
#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_TRGSELRC)
#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_HTSSR0)
#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_HTSSR1)
#define AOS_TMR6_2 (uint32_t)(&CM_AOS->TMR6_HTSSR2)
#define AOS_TMR6_3 (uint32_t)(&CM_AOS->TMR6_HTSSR3)
#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNTTRGSR12)
#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNTTRGSR34)
#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_HTSSR)
#define AOS_TMR2 (uint32_t)(&CM_AOS->TMR2_HTSSR)
#define AOS_HASH_A (uint32_t)(&CM_AOS->HASH_ITRGSELA)
#define AOS_HASH_B (uint32_t)(&CM_AOS->HASH_ITRGSELB)
#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_HTSSR0)
#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_HTSSR1)
#define AOS_TMRA_2 (uint32_t)(&CM_AOS->TMRA_HTSSR2)
#define AOS_TMRA_3 (uint32_t)(&CM_AOS->TMRA_HTSSR3)
#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRG)
#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_ITRGSELR0)
#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_ITRGSELR1)
#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_ITRGSELR0)
#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_ITRGSELR1)
#define AOS_ADC3_0 (uint32_t)(&CM_AOS->ADC3_ITRGSELR0)
#define AOS_ADC3_1 (uint32_t)(&CM_AOS->ADC3_ITRGSELR1)
#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRG1)
#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRG2)
/**
* @}
*/
/**
* @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID
* @{
*/
#define AOS_COMM_TRIG1 (1UL << 30U)
#define AOS_COMM_TRIG2 (1UL << 31U)
#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2)
/**
* @}
*/
/**
* @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask
* @{
*/
#define AOS_TRIG_SEL_MASK (0x1FFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup AOS_Global_Functions
* @{
*/
/**
* @brief AOS software trigger.
* @param None
* @retval None
*/
__STATIC_INLINE void AOS_SW_Trigger(void)
{
WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET);
}
void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState);
void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent);
/**
* @}
*/
#endif /* LL_AOS_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_AOS_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_can.h
* @brief This file contains all the functions prototypes of the CAN driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_CAN_H__
#define __HC32_LL_CAN_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_CAN
* @{
*/
#if (LL_CAN_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CAN_Global_Types CAN Global Types
* @{
*/
/**
* @brief CAN bit time configuration structure.
* @note 1. TQ = u32Prescaler / CANClock.
* @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
* @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
* @note 4. See user manual of the target MCU and ISO11898-1 for more details.
*/
typedef struct {
uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */
uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
u32TimeSeg1 Contains synchronization segment,
propagation time segment and phase buffer segment 1. */
uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
Phase buffer segment 2. */
uint32_t u32SJW; /*!< Synchronization Jump Width.
Specifies the maximum number of time quanta the CAN hardware
is allowed to lengthen or shorten a bit to perform resynchronization. */
} stc_can_bit_time_config_t;
/**
* @brief CAN acceptance filter configuration structure.
*/
typedef struct {
uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */
uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */
uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */
} stc_can_filter_config_t;
/* CAN-FD structure */
/**
* @brief CAN-FD configuration structure.
*/
typedef struct {
stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of flexible data-rate bit. */
uint8_t u8Mode; /*!< CAN-FD mode, Bosch CAN-FD or ISO 11898-1:2015 CAN-FD.
This parameter can be a value of @ref CAN_FD_Mode */
uint8_t u8TDC; /*!< Enable or disable Transmitter Delay Compensation.
This parameter can be a value of @ref CAN_FD_TDC_En */
uint8_t u8SSPOffset; /*!< Specifies Secondary Sample Point offset.
The transmitter delay plus u8SSPOffset defines the time of the secondary sample point for TDC.
u8SSPOffset is given as a number of TQ. Range is [0, 127] */
} stc_canfd_config_t;
/**
* @brief TTCAN configuration structure.
*/
typedef struct {
uint32_t u32RefMsgID; /*!< Reference message identifier. */
uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit.
'1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while
'0' to set it as a standard ID. */
uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT.
This parameter can be a value of @ref TTCAN_NTU_Prescaler */
uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode.
This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */
uint16_t u16TriggerType; /*!< Trigger type of TTCAN.
This parameter can be a value of @ref TTCAN_Trigger_Type */
uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */
uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */
uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */
} stc_can_ttc_config_t;
/**
* @brief CAN initialization structure.
*/
typedef struct {
stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */
stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that
contains the configuration informations for the acceptance filters. */
uint16_t u16FilterSelect; /*!< Selects acceptance filters.
This parameter can be values of @ref CAN_Acceptance_Filter */
uint8_t u8WorkMode; /*!< Specifies the work mode of CAN.
This parameter can be a value of @ref CAN_Work_Mode */
uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB.
This parameter can be a value of @ref PTB_SingleShot_Tx_En */
uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB.
This parameter can be a value of @ref STB_SingleShot_Tx_En */
uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB.
This parameter can be a value of @ref CAN_STB_Prio_Mode_En
NOTE: A frame in the PTB has always the highest priority regardless of the ID. */
uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8].
Each CAN unit has 8 receive buffers. When the number of received frames reaches
the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred
if it was enabled. */
uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15].
Error warning limit = (u8ErrorWarnLimit + 1) * 8. */
uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error).
This parameter can be a value of @ref CAN_Rx_All_En */
uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received.
This parameter can be a value of @ref CAN_Rx_Ovf_Mode */
uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge.
This parameter can be a value of @ref CAN_Self_ACK_En */
/* CAN-FD configuration */
stc_canfd_config_t *pstcCanFd; /*!< Pointer to a CAN-FD configuration structure. @ref stc_canfd_config_t
Set it to NULL if not needed CAN-FD. */
stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t
Set it to NULL if not needed TTCAN. */
} stc_can_init_t;
/**
* @brief CAN error information structure.
*/
typedef struct {
uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */
uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */
uint8_t u8RxErrorCount; /*!< Receive error count. */
uint8_t u8TxErrorCount; /*!< Transmit error count. */
} stc_can_error_info_t;
/**
* @brief CAN TX frame data structure.
*/
typedef struct {
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
union {
uint32_t u32Ctrl;
struct {
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
It should be zero while the frame is remote frame.
This parameter can be a value of @ref CAN_Data_Length_Code */
uint32_t BRS: 1; /*!< Bit rate switch. */
uint32_t FDF: 1; /*!< CAN FD frame. */
uint32_t RTR: 1; /*!< Remote transmission request bit.
It is used to distinguish between data frames and remote frames. */
uint32_t IDE: 1; /*!< Identifier extension flag.
It is used to distinguish between standard format and extended format.
This parameter can be a 1 or 0. */
uint32_t RSVD: 24; /*!< Reserved bits. */
};
};
uint8_t au8Data[64U]; /*!< TX data payload. */
} stc_can_tx_frame_t;
/**
* @brief CAN RX frame data structure.
*/
typedef struct {
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
union {
uint32_t u32Ctrl;
struct {
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
It should be zero while the frame is remote frame.
This parameter can be a value of @ref CAN_Data_Length_Code */
uint32_t BRS: 1; /*!< Bit rate switch. */
uint32_t FDF: 1; /*!< CAN FD frame. */
uint32_t RTR: 1; /*!< Remote transmission request bit.
It is used to distinguish between data frames and remote frames. */
uint32_t IDE: 1; /*!< Identifier extension flag.
It is used to distinguish between standard format and extended format.
This parameter can be 1 or 0. */
uint32_t RSVD: 4; /*!< Reserved bits. */
uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */
uint32_t ERRT: 3; /*!< Error type. */
uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */
};
};
uint8_t au8Data[64U]; /*!< RX data payload. */
} stc_can_rx_frame_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CAN_Global_Macros CAN Global Macros
* @{
*/
/**
* @defgroup CAN_Work_Mode CAN Work Mode
* @{
*/
#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */
#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */
#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */
#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */
#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing.
It is forbidden to respond to received frames and error frames,
but data can be transmitted. */
/**
* @}
*/
/**
* @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type
* @{
*/
#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */
#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */
/**
* @}
*/
/**
* @defgroup CAN_Data_Length_Code CAN Data Length Code
* @{
*/
#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */
#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */
#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */
#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */
#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */
#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */
#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */
#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */
#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */
/* More DLC for CAN-FD. */
#define CAN_DLC12 (0x9U) /*!< CAN FD: the size of data field is 12 bytes. */
#define CAN_DLC16 (0xAU) /*!< CAN FD: the size of data field is 16 bytes. */
#define CAN_DLC20 (0xBU) /*!< CAN FD: the size of data field is 20 bytes. */
#define CAN_DLC24 (0xCU) /*!< CAN FD: the size of data field is 24 bytes. */
#define CAN_DLC32 (0xDU) /*!< CAN FD: the size of data field is 32 bytes. */
#define CAN_DLC48 (0xEU) /*!< CAN FD: the size of data field is 48 bytes. */
#define CAN_DLC64 (0xFU) /*!< CAN FD: the size of data field is 64 bytes. */
/**
* @}
*/
/**
* @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control
* @{
*/
#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */
#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */
/**
* @}
*/
/**
* @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control
* @{
*/
#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */
#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */
/**
* @}
*/
/**
* @defgroup CAN_Tx_Request CAN Transmission Request
* @{
*/
#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */
#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */
#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */
/**
* @}
*/
/**
* @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control
* @note A frame in the PTB has always the highest priority regardless of the ID.
* @{
*/
#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */
#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */
/**
* @}
*/
/**
* @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status
* @{
*/
#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty.
TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1):
PTB and STB are both empty. */
#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full;
TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */
#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full;
TTEN == 1 && TTTBM == 1: reserved value. */
#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full;
TTEN == 1 && TTTBM == 1: PTB and STB are both full. */
/**
* @}
*/
/**
* @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status
* @{
*/
#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */
#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */
#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */
#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */
/**
* @}
*/
/**
* @defgroup CAN_Rx_All_En CAN Receive All Frames
* @{
*/
#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */
#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */
/**
* @}
*/
/**
* @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode
* @{
*/
#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */
#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */
/**
* @}
*/
/**
* @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control
* @{
*/
#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */
#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */
/**
* @}
*/
/**
* @defgroup CAN_Interrupt_Type CAN Interrupt Type
* @{
*/
#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
the BUSOFF bit has been changed in either direction. */
#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */
#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */
#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */
#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */
#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */
#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error inetrrupt. */
#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */
#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */
#define CAN_INT_ALL (CAN_INT_ERR_INT | \
CAN_INT_STB_TX | \
CAN_INT_PTB_TX | \
CAN_INT_RX_BUF_WARN | \
CAN_INT_RX_BUF_FULL | \
CAN_INT_RX_OVERRUN | \
CAN_INT_RX | \
CAN_INT_BUS_ERR | \
CAN_INT_ARBITR_LOST | \
CAN_INT_ERR_PASSIVE)
/**
* @}
*/
/**
* @defgroup CAN_Status_Flag CAN Status Flag
* @{
*/
#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */
#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */
#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */
#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */
#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full.
TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled.
TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/
#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */
#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
the BUSOFF bit has been changed in either direction. */
#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */
#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */
#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */
#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */
#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */
#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */
#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */
#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */
#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */
#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */
#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \
CAN_FLAG_TX_GOING | \
CAN_FLAG_RX_GOING | \
CAN_FLAG_RX_BUF_OVF | \
CAN_FLAG_TX_BUF_FULL | \
CAN_FLAG_TX_ABORTED | \
CAN_FLAG_ERR_INT | \
CAN_FLAG_STB_TX | \
CAN_FLAG_PTB_TX | \
CAN_FLAG_RX_BUF_WARN | \
CAN_FLAG_RX_BUF_FULL | \
CAN_FLAG_RX_OVERRUN | \
CAN_FLAG_RX | \
CAN_FLAG_BUS_ERR | \
CAN_FLAG_ARBITR_LOST | \
CAN_FLAG_ERR_PASSIVE | \
CAN_FLAG_ERR_PASSIVE_NODE | \
CAN_FLAG_TEC_REC_WARN)
#define CAN_FLAG_CLR_ALL (CAN_FLAG_RX_BUF_OVF | \
CAN_FLAG_TX_ABORTED | \
CAN_FLAG_ERR_INT | \
CAN_FLAG_STB_TX | \
CAN_FLAG_PTB_TX | \
CAN_FLAG_RX_BUF_WARN | \
CAN_FLAG_RX_BUF_FULL | \
CAN_FLAG_RX_OVERRUN | \
CAN_FLAG_RX | \
CAN_FLAG_BUS_ERR | \
CAN_FLAG_ARBITR_LOST | \
CAN_FLAG_ERR_PASSIVE)
/**
* @}
*/
/**
* @defgroup CAN_ID_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */
#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */
#define CAN_ID_EXT (CAN_ACF_AIDEE | \
CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */
/**
* @}
*/
/**
* @defgroup CAN_Err_Type CAN Error Type
* @{
*/
#define CAN_ERR_NONE (0U) /*!< No error. */
#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */
#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */
#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */
#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */
#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */
#define CAN_ERR_OTHER (0x6U) /*!< Error is other error.
Dominant bits after own error flag, received active Error Flag too long,
dominant bit during Passive-Error-Flag after ACK error. */
/**
* @}
*/
/**
* @defgroup CAN_Acceptance_Filter CAN Acceptance Filter
* @{
*/
#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */
#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */
#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */
#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */
#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */
#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */
#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */
#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */
#define CAN_FILTER9 (CAN_ACFEN_AE_9) /*!< Acceptance filter 9 select bit. */
#define CAN_FILTER10 (CAN_ACFEN_AE_10) /*!< Acceptance filter 10 select bit. */
#define CAN_FILTER11 (CAN_ACFEN_AE_11) /*!< Acceptance filter 11 select bit. */
#define CAN_FILTER12 (CAN_ACFEN_AE_12) /*!< Acceptance filter 12 select bit. */
#define CAN_FILTER13 (CAN_ACFEN_AE_13) /*!< Acceptance filter 13 select bit. */
#define CAN_FILTER14 (CAN_ACFEN_AE_14) /*!< Acceptance filter 14 select bit. */
#define CAN_FILTER15 (CAN_ACFEN_AE_15) /*!< Acceptance filter 15 select bit. */
#define CAN_FILTER16 (CAN_ACFEN_AE_16) /*!< Acceptance filter 16 select bit. */
#define CAN_FILTER_ALL (0xFFFFU)
/**
* @}
*/
/**
* @defgroup CAN_FD_Mode CAN-FD Mode
* @{
*/
#define CAN_FD_MD_BOSCH (0x0U) /*!< Bosch CAN FD (non-ISO) mode. */
#define CAN_FD_MD_ISO (CAN_TCTRL_FD_ISO) /*!< ISO CAN FD mode (ISO 11898-1:2015). */
/**
* @}
*/
/**
* @defgroup CAN_FD_TDC_En CAN-FD TDC Function Control
* @{
*/
#define CAN_FD_TDC_DISABLE (0x0U) /*!< Disable transmitter delay compensation. */
#define CAN_FD_TDC_ENABLE (CAN_TDC_TDCEN) /*!< Enable transmitter delay compensation. */
/**
* @}
*/
/**
* @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode
* @{
*/
#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */
#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and
TRG_CFG.TTPTR(for data transmission). */
/**
* @}
*/
/**
* @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection
* @{
*/
#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */
#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */
#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */
#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */
/**
* @}
*/
/**
* @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State
* @{
*/
#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty".
TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0.
If a transmission from this slot is active, then TBE stays set as long as either the
transmission completes or after a transmission error or arbitration loss the transmission
is not active any more. If both TBF and TBE are set, then TBE wins. */
#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled".
TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1.
If both TBF and TBE are set, then TBE wins. */
/**
* @}
*/
/**
* @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type
* @{
*/
#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */
#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */
#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \
CAN_TTC_INT_WATCH_TRIG)
/**
* @}
*/
/**
* @defgroup TTCAN_Status_Flag TTCAN Status Flag
* @{
*/
#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */
#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */
#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */
#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \
CAN_TTC_FLAG_TRIG_ERR | \
CAN_TTC_FLAG_WATCH_TRIG)
/**
* @}
*/
/**
* @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler
* @{
*/
#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */
#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */
#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */
#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */
/**
* @}
*/
/**
* @defgroup TTCAN_Trigger_Type TTCAN Trigger Type
* @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled.
* @{
*/
#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */
#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */
#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */
#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \
CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */
#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CAN_Global_Functions
* @{
*/
/* Classical CAN */
int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit);
int32_t CAN_StructInit(stc_can_init_t *pstcCanInit);
void CAN_DeInit(CM_CAN_TypeDef *CANx);
void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState);
int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx);
void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest);
void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType);
int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx);
en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag);
void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag);
uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx);
int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr);
uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx);
uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx);
void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState);
void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit);
void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit);
int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd);
/* TTCAN */
int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc);
int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc);
void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState);
void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState);
en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag);
void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag);
uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx);
void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType);
void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow);
void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime);
void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime);
int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx);
int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc);
/**
* @}
*/
#endif /* LL_CAN_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_CAN_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,779 @@
/**
*******************************************************************************
* @file hc32_ll_clk.h
* @brief This file contains all the functions prototypes of the CLK driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_CLK_H__
#define __HC32_LL_CLK_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_CLK
* @{
*/
#if (LL_CLK_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CLK_Global_Types CLK Global Types
* @{
*/
/**
* @brief CLK XTAL configuration structure definition
*/
typedef struct {
uint8_t u8State; /*!< The new state of the XTAL.
This parameter can be a value of @ref CLK_XTAL_Config */
uint8_t u8Drv; /*!< The XTAL drive ability.
This parameter can be a value of @ref CLK_XTAL_Config */
uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk.
This parameter can be a value of @ref CLK_XTAL_Config */
uint8_t u8StableTime; /*!< The XTAL stable time selection.
This parameter can be a value of @ref CLK_XTAL_Config */
} stc_clock_xtal_init_t;
/**
* @brief CLK XTAL fault detect configuration structure definition
*/
typedef struct {
uint8_t u8State; /*!< Specifies the new state of XTALSTD.
This parameter can be a value of @ref CLK_XTALSTD_Config */
uint8_t u8Mode; /*!< Specifies the XTALSTD mode.
This parameter can be a value of @ref CLK_XTALSTD_Config */
uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off.
This parameter can be a value of @ref CLK_XTALSTD_Config */
uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off.
This parameter can be a value of @ref CLK_XTALSTD_Config */
} stc_clock_xtalstd_init_t;
/**
* @brief CLK XTAL32 configuration structure definition
*/
typedef struct {
uint8_t u8State; /*!< Xtal32 new state,
@ref CLK_XTAL32_Config for details */
uint8_t u8Drv; /*!< Xtal32 drive capacity setting,
@ref CLK_XTAL32_Config for details */
uint8_t u8Filter; /*!< Xtal32 noise filter setting,
@ref CLK_XTAL32_Config for details */
} stc_clock_xtal32_init_t;
/**
* @brief CLK clock frequency configuration structure definition
*/
typedef struct {
union {
uint32_t SCFGR; /*!< clock frequency config register */
struct {
uint32_t PCLK0S : 3; /*!< PCLK0 */
uint32_t resvd0 : 1; /*!< reserved */
uint32_t PCLK1S : 3; /*!< PCLK1 */
uint32_t resvd1 : 1; /*!< reserved */
uint32_t PCLK2S : 3; /*!< PCLK2 */
uint32_t resvd2 : 1; /*!< reserved */
uint32_t PCLK3S : 3; /*!< PCLK3 */
uint32_t resvd3 : 1; /*!< reserved */
uint32_t PCLK4S : 3; /*!< PCLK4 */
uint32_t resvd4 : 1; /*!< reserved */
uint32_t EXCKS : 3; /*!< EXCLK */
uint32_t resvd5 : 1; /*!< reserved */
uint32_t HCLKS : 3; /*!< HCLK */
uint32_t resvd6 : 5; /*!< reserved */
} SCFGR_f;
};
} stc_clock_scale_t;
/**
* @brief CLK PLL configuration structure definition
* @note PLL for MPLL while HC32F460,HC32F451,HC32F452
* PLL for PLLH while HC32F4A0
*/
typedef struct {
uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */
union {
uint32_t PLLCFGR; /*!< PLL config register */
struct {
uint32_t PLLM : 2; /*!< PLL M divide */
uint32_t resvd0 : 5; /*!< reserved */
uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */
uint32_t PLLN : 8; /*! PLLH N multi- */
uint32_t resvd1 : 4; /*! reserved */
uint32_t PLLR : 4; /*!< PLL R divide */
uint32_t PLLQ : 4; /*!< PLL Q divide */
uint32_t PLLP : 4; /*!< PLL P divide */
} PLLCFGR_f;
};
} stc_clock_pll_init_t;
/**
* @brief CLK PLLx configuration structure definition
* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
* PLLx for PLLA while HC32F4A0
*/
typedef struct {
uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */
union {
uint32_t PLLCFGR; /*!< PLLx config register */
struct {
uint32_t PLLM : 5; /*!< PLLx M divide */
uint32_t resvd0 : 3; /*!< reserved */
uint32_t PLLN : 9; /*!< PLLx N multi- */
uint32_t resvd1 : 3; /*!< reserved */
uint32_t PLLR : 4; /*!< PLLx R divide */
uint32_t PLLQ : 4; /*!< PLLx Q divide */
uint32_t PLLP : 4; /*!< PLLx P divide */
} PLLCFGR_f;
};
} stc_clock_pllx_init_t;
/**
* @brief CLK bus frequency structure definition
*/
typedef struct {
uint32_t u32SysclkFreq; /*!< System clock frequency. */
uint32_t u32HclkFreq; /*!< Hclk frequency. */
uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */
uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */
uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */
uint32_t u32ExclkFreq; /*!< Exclk frequency. */
uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */
uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */
} stc_clock_freq_t;
/**
* @brief CLK PLL clock frequency structure definition
*/
typedef struct {
uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */
uint32_t u32PllVco; /*!< PLL vco clock frequency. */
uint32_t u32PllP; /*!< PLLp clock frequency. */
uint32_t u32PllQ; /*!< PLLq clock frequency. */
uint32_t u32PllR; /*!< PLLr clock frequency. */
uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */
uint32_t u32PllxVco; /*!< pllx vco clock frequency. */
uint32_t u32PllxP; /*!< pllxp clock frequency. */
uint32_t u32PllxQ; /*!< pllxq clock frequency. */
uint32_t u32PllxR; /*!< pllxr clock frequency. */
} stc_pll_clock_freq_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CLK_Global_Macros CLK Global Macros
* @{
*/
/**
* @defgroup CLK_PLLx_State CLK PLLx State
* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
* PLLx for PLLA while HC32F4A0
* @{
*/
#define CLK_PLLX_OFF (0x01U)
#define CLK_PLLX_ON (0x00U)
/**
* @}
*/
/**
* @defgroup CLK_PLL_Config PLL Config
* @{
*/
/**
* @brief PLL function config.
*/
#define CLK_PLL_OFF (0x01U)
#define CLK_PLL_ON (0x00U)
/**
* @brief PLL/A source clock selection.
*/
#define CLK_PLL_SRC_XTAL (0x00UL)
#define CLK_PLL_SRC_HRC (0x01UL)
/**
* @}
*/
/**
* @defgroup CLK_XTAL_Config XTAL Config
* @{
*/
/**
* @brief XTAL function config.
*/
#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP)
#define CLK_XTAL_ON (0x00U)
/**
* @brief XTAL driver ability
* @note HC32F451/HC32F452 | | |
* @note HC32F4A0/HC32F460 | | |
* @note HC32F472 | HC32M423/HC32M424 | HC32M120/HC32F120/HC32F160 |
* High: [20~25] | [20~24] | [20] |
* Mid: [16~20) | [16~20) | [10~20) |
* Low: (8~16) | (8~16) | (4~10) |
* ULow: [4~8] | [4~8] | [4] |
*/
#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS)
#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS)
#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS)
#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS)
/**
* @brief XTAL mode selection osc or exclk
*/
#define CLK_XTAL_MD_OSC (0x00U)
#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS)
/**
* @brief XTAL stable time selection.
* @note a cycle of stable counter = a cycle of LRC divide by 8
*/
#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */
#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */
#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */
#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */
#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */
#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */
#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */
#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */
#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */
/**
* @}
*/
/**
* @defgroup CLK_XTALSTD_Config XTALSTD Config
* @{
*/
/**
* @brief XTAL error detection on or off
*/
#define CLK_XTALSTD_OFF (0x00U)
#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE)
/**
* @brief XTALSTD mode selection
*/
#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS)
#define CLK_XTALSTD_MD_INT (0x00U)
/**
* @brief XTALSTD reset on or off
*/
#define CLK_XTALSTD_RST_OFF (0x00U)
#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE)
/**
* @brief XTALSTD interrupt on or off
*/
#define CLK_XTALSTD_INT_OFF (0x00U)
#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE)
/**
* @}
*/
/**
* @defgroup CLK_XTAL32_Config XTAL32 Config
* @{
*/
/**
* @brief XTAL32 function config.
*/
#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP)
#define CLK_XTAL32_ON (0x00U)
/**
* @brief XTAL32 driver ability.
*/
#define CLK_XTAL32_DRV_MID (0x00U)
#define CLK_XTAL32_DRV_HIGH (0x01U)
/**
* @brief XTAL32 filtering selection.
*/
#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */
#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */
#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */
/**
* @}
*/
/**
* @defgroup CLK_HRC_Config HRC Config
* @{
*/
#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP)
#define CLK_HRC_ON (0x00U)
/**
* @}
*/
/**
* @defgroup CLK_HrcFreq_Sel Hrc Freqency Selection
* @{
*/
/**
* @}
*/
/**
* @defgroup CLK_STB_Flag CLK Stable Flags
* @{
*/
#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF)
#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF)
#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_PLLHSTBF)
#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_PLLASTBF)
#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \
CMU_OSCSTBSR_PLLASTBF | CMU_OSCSTBSR_PLLHSTBF)
/**
* @}
*/
/**
* @defgroup CLK_System_Clock_Source System Clock Source
* @{
*/
#define CLK_SYSCLK_SRC_HRC (0x00U)
#define CLK_SYSCLK_SRC_MRC (0x01U)
#define CLK_SYSCLK_SRC_LRC (0x02U)
#define CLK_SYSCLK_SRC_XTAL (0x03U)
#define CLK_SYSCLK_SRC_XTAL32 (0x04U)
#define CLK_SYSCLK_SRC_PLL (0x05U)
/**
* @}
*/
/**
* @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection
* @{
*/
#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S)
#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S)
#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S)
#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S)
#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S)
#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS)
#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS)
#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \
CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK)
/**
* @}
*/
/**
* @defgroup CLK_Clock_Divider Clock Divider
* @{
*/
/**
* @defgroup CLK_System_Clock_Divider System Clock Divider
* @{
*/
#define CLK_SYSCLK_DIV1 (0x00U)
#define CLK_SYSCLK_DIV2 (0x01U)
#define CLK_SYSCLK_DIV4 (0x02U)
#define CLK_SYSCLK_DIV8 (0x03U)
#define CLK_SYSCLK_DIV16 (0x04U)
#define CLK_SYSCLK_DIV32 (0x05U)
#define CLK_SYSCLK_DIV64 (0x06U)
/**
* @}
*/
/**
* @defgroup CLK_HCLK_Divider CLK HCLK Divider
* @{
*/
#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS)
#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS)
/**
* @}
*/
/**
* @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider
* @{
*/
#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS)
#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS)
/**
* @}
*/
/**
* @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider
* @{
*/
#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS)
#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS)
/**
* @}
*/
/**
* @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider
* @{
*/
#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS)
#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS)
/**
* @}
*/
/**
* @defgroup CLK_EXCLK_Divider CLK EXCLK Divider
* @{
*/
#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS)
#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS)
/**
* @}
*/
/**
* @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider
* @{
*/
#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS)
#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS)
/**
* @}
*/
/**
* @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider
* @{
*/
#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS)
#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS)
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup CLK_USBCLK_Sel CLK USB Clock Selection
* @{
*/
#define CLK_USBCLK_SYSCLK_DIV2 (0x01U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV3 (0x02U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV4 (0x03U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV5 (0x04U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV6 (0x05U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV7 (0x06U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_SYSCLK_DIV8 (0x07U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_PLLQ (0x08U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_PLLR (0x09U << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_PLLXP (0x0AU << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_PLLXQ (0x0BU << CMU_USBCKCFGR_USBCKS_POS)
#define CLK_USBCLK_PLLXR (0x0CU << CMU_USBCKCFGR_USBCKS_POS)
/**
* @}
*/
/**
* @defgroup CLK_CANCLK_Sel CLK CAN Clock Selection
* @{
*/
#define CLK_CANCLK_SYSCLK_DIV2 (0x01U)
#define CLK_CANCLK_SYSCLK_DIV3 (0x02U)
#define CLK_CANCLK_SYSCLK_DIV4 (0x03U)
#define CLK_CANCLK_SYSCLK_DIV5 (0x04U)
#define CLK_CANCLK_SYSCLK_DIV6 (0x05U)
#define CLK_CANCLK_SYSCLK_DIV7 (0x06U)
#define CLK_CANCLK_SYSCLK_DIV8 (0x07U)
#define CLK_CANCLK_PLLQ (0x08U)
#define CLK_CANCLK_PLLR (0x09U)
#define CLK_CANCLK_PLLXP (0x0AU)
#define CLK_CANCLK_PLLXQ (0x0BU)
#define CLK_CANCLK_PLLXR (0x0CU)
#define CLK_CANCLK_XTAL (0x0DU)
/**
* @}
*/
/**
* @defgroup CLK_CAN_Sel CLK CAN Channel Selection
* @{
*/
#define CLK_CAN1 (0x01U)
#define CLK_CAN2 (0x02U)
/**
* @}
*/
/**
* @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection
* @note ADC,I2S,DAC,TRANG
* @{
*/
#define CLK_PERIPHCLK_PCLK (0x0000U) /* PCLK2 is used for ADC clock, \
PCLK1 is used for I2S clock, \
PCLK4 is used for DAC/TRANG clock */
#define CLK_PERIPHCLK_PLLQ (0x0008U)
#define CLK_PERIPHCLK_PLLR (0x0009U)
#define CLK_PERIPHCLK_PLLXP (0x000AU)
#define CLK_PERIPHCLK_PLLXQ (0x000BU)
#define CLK_PERIPHCLK_PLLXR (0x000CU)
/**
* @}
*/
/**
* @defgroup CLK_I2S_Sel CLK I2S Channel Selection
* @{
*/
#define CLK_I2S1 (0x00U)
#define CLK_I2S2 (0x01U)
#define CLK_I2S3 (0x02U)
#define CLK_I2S4 (0x03U)
/**
* @}
*/
/**
* @defgroup CLK_TPIU_Divider TPIU clock divider
* @{
*/
#define CLK_TPIUCLK_DIV1 (0x00U)
#define CLK_TPIUCLK_DIV2 (0x01U)
#define CLK_TPIUCLK_DIV4 (0x02U)
/**
* @}
*/
/**
* @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select
* @{
*/
#define CLK_MCO1 (0x00U)
#define CLK_MCO2 (0x01U)
/**
* @}
*/
/**
* @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source
* @{
*/
#define CLK_MCO_SRC_HRC (0x00U)
#define CLK_MCO_SRC_MRC (0x01U)
#define CLK_MCO_SRC_LRC (0x02U)
#define CLK_MCO_SRC_XTAL (0x03U)
#define CLK_MCO_SRC_XTAL32 (0x04U)
#define CLK_MCO_SRC_PLLP (0x06U)
#define CLK_MCO_SRC_PLLXP (0x07U)
#define CLK_MCO_SRC_PLLQ (0x08U)
#define CLK_MCO_SRC_PLLXQ (0x09U)
#define CLK_MCO_SRC_PLLXR (0x0AU)
#define CLK_MCO_SRC_HCLK (0x0BU)
/**
* @}
*/
/**
* @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler
* @{
*/
#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS)
#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CLK_Global_Functions
* @{
*/
int32_t CLK_HrcCmd(en_functional_state_t enNewState);
int32_t CLK_MrcCmd(en_functional_state_t enNewState);
int32_t CLK_LrcCmd(en_functional_state_t enNewState);
void CLK_HrcTrim(int8_t i8TrimVal);
void CLK_MrcTrim(int8_t i8TrimVal);
void CLK_LrcTrim(int8_t i8TrimVal);
void CLK_RtcLrcTrim(int8_t i8TrimVal);
int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit);
int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit);
int32_t CLK_XtalCmd(en_functional_state_t enNewState);
int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit);
int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit);
void CLK_ClearXtalStdStatus(void);
en_flag_status_t CLK_GetXtalStdStatus(void);
int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init);
int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init);
int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
void CLK_Xtal32InputCmd(en_functional_state_t enNewState);
void CLK_SetPLLSrc(uint32_t u32PllSrc);
int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit);
int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit);
int32_t CLK_PLLCmd(en_functional_state_t enNewState);
int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq);
int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit);
int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit);
int32_t CLK_PLLxCmd(en_functional_state_t enNewState);
void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div);
void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState);
en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag);
void CLK_SetSysClockSrc(uint8_t u8Src);
void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div);
int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq);
uint32_t CLK_GetBusClockFreq(uint32_t u32Clock);
void CLK_SetPeriClockSrc(uint16_t u16Src);
void CLK_SetUSBClockSrc(uint8_t u8Src);
void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src);
void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src);
void CLK_TpiuClockCmd(en_functional_state_t enNewState);
void CLK_SetTpiuClockDiv(uint8_t u8Div);
/**
* @}
*/
#endif /* LL_CLK_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_CLK_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_cmp.h
* @brief Head file for CMP module.
*
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_CMP_H__
#define __HC32_LL_CMP_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_CMP
* @{
*/
#if (LL_CMP_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CMP_Global_Types CMP Global Types
* @{
*/
/**
* @brief CMP normal mode configuration structure
*/
typedef struct {
uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */
uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */
uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */
uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
} stc_cmp_init_t;
/**
* @brief CMP window mode configuration structure
*/
typedef struct {
uint8_t u8WinVolLow; /*!< CMP reference low voltage for window mode @ref CMP_Window_Low_Select */
uint8_t u8WinVolHigh; /*!< CMP reference high voltage for window mode @ref CMP_Window_High_Select */
uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */
uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
} stc_cmp_window_init_t;
/**
* @brief CMP blank window function configuration structure
*/
typedef struct {
uint16_t u16Src; /*!< blank window source select,
can be any combination of @ref CMP_BlankWindow_Src */
uint8_t u8ValidLevel; /*!< Blank window valid level @ref CMP_BlankWindow_Valid_Level */
uint8_t u8OutLevel; /*!< CMP output level when blank window valid @ref CMP_BlankWindow_output_Level */
} stc_cmp_blankwindow_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CMP_Global_Macros CMP Global Macros
* @{
*/
#define VISR_OFFSET (8U)
/**
* @defgroup CMP_Window_Mode_Unit CMP Window Mode Unit
* @{
*/
#define CMP_WIN_CMP12 (0x01U)
#define CMP_WIN_CMP34 (0x02U)
/**
* @}
*/
/**
* @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input
* @{
*/
#define CMP_POSITIVE_NONE (0x0U)
/* Select positive input for CMP1 */
#define CMP1_POSITIVE_PGA1_BP (CMP_PMSR_CVSL_0) /*!< Select PGA1_BP */
#define CMP1_POSITIVE_PGA1 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select PGA1 */
#define CMP1_POSITIVE_PGA2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select PGA2 */
#define CMP1_POSITIVE_CMP1_INP2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_2 << VISR_OFFSET)) /*!< Select CMP1_INP2 */
#define CMP1_POSITIVE_CMP1_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P3SL_0 << VISR_OFFSET)) /*!< Select CMP1_INP3 */
#define CMP1_POSITIVE_CMP2_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P3SL_1 << VISR_OFFSET)) /*!< Select CMP2_INP3 */
#define CMP1_POSITIVE_CMP1_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP1_INP4 */
/* Select positive input for CMP2 */
#define CMP2_POSITIVE_PGA2_BP (CMP_PMSR_CVSL_0) /*!< Select PGA2_BP */
#define CMP2_POSITIVE_PGA2 (CMP_PMSR_CVSL_1) /*!< Select PGA2 */
#define CMP2_POSITIVE_CMP2_INP3 (CMP_PMSR_CVSL_2) /*!< Select CMP2_INP3 */
#define CMP2_POSITIVE_CMP2_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP2_INP4 */
/* Select positive input for CMP3 */
#define CMP3_POSITIVE_PGA3_BP (CMP_PMSR_CVSL_0) /*!< Select PGA3_BP */
#define CMP3_POSITIVE_PGA3 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select PGA3 */
#define CMP3_POSITIVE_PGA4 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select PGA4_BP */
#define CMP3_POSITIVE_CMP3_INP2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_2 << VISR_OFFSET)) /*!< Select CMP3_INP2 */
#define CMP3_POSITIVE_CMP3_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select CMP3_INP3 */
#define CMP3_POSITIVE_CMP4_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select CMP4_INP3 */
#define CMP3_POSITIVE_CMP3_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP3_INP4 */
/* Select positive input for CMP4 */
#define CMP4_POSITIVE_PGA4_BP (CMP_PMSR_CVSL_0) /*!< Select PGA4_BP */
#define CMP4_POSITIVE_PGA4 (CMP_PMSR_CVSL_1) /*!< Select PGA4 */
#define CMP4_POSITIVE_CMP4_INP3 (CMP_PMSR_CVSL_2) /*!< Select CMP4_INP3 */
#define CMP4_POSITIVE_CMP4_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP4_INP4 */
/**
* @}
*/
/**
* @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input
* @{
*/
#define CMP_NEGATIVE_NONE (0x0U)
/* Select negative input for CMP1 */
#define CMP1_NEGATIVE_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */
#define CMP1_NEGATIVE_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */
#define CMP1_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP1_NEGATIVE_CMP1_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP1_INM4 */
/* Select negative input for CMP2 */
#define CMP2_NEGATIVE_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */
#define CMP2_NEGATIVE_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */
#define CMP2_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP2_NEGATIVE_CMP2_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP2_INM4 */
/* Select negative input for CMP3 */
#define CMP3_NEGATIVE_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */
#define CMP3_NEGATIVE_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */
#define CMP3_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP3_NEGATIVE_CMP3_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP3_INM4 */
/* Select negative input for CMP4 */
#define CMP4_NEGATIVE_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */
#define CMP4_NEGATIVE_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */
#define CMP4_NEGATIVE_CMP4_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP4_INM3 */
#define CMP4_NEGATIVE_CMP4_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP4_INM4 */
/**
* @}
*/
/**
* @defgroup CMP_Window_Low_Select CMP Window Mode Window Low Voltage
* @{
*/
#define CMP_WIN_LOW_NONE (0x0U)
/* Select input for window mode CMP_WIN_CMP12 */
#define CMP12_WIN_LOW_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */
#define CMP12_WIN_LOW_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */
#define CMP12_WIN_LOW_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP12_WIN_LOW_CMP1_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP1_INM4 */
/* Select input for window mode CMP_WIN_CMP34 */
#define CMP34_WIN_LOW_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */
#define CMP34_WIN_LOW_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */
#define CMP34_WIN_LOW_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP34_WIN_LOW_CMP3_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP3_INM4 */
/**
* @}
*/
/**
* @defgroup CMP_Window_High_Select CMP Window Mode Window High Voltage
* @{
*/
#define CMP_WIN_HIGH_NONE (0x0U)
/* Select input for window mode CMP_WIN_CMP12 */
#define CMP12_WIN_HIGH_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */
#define CMP12_WIN_HIGH_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */
#define CMP12_WIN_HIGH_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */
#define CMP12_WIN_HIGH_CMP2_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP2_INM4 */
/* Select input for window mode CMP_WIN_CMP34 */
#define CMP34_WIN_HIGH_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */
#define CMP34_WIN_HIGH_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */
#define CMP34_WIN_HIGH_CMP4_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP4_INM3 */
#define CMP34_WIN_HIGH_CMP4_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP4_INM4 */
/**
* @}
*/
/**
* @defgroup CMP_Out_Polarity_Select CMP Output Polarity
* @{
*/
#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */
#define CMP_OUT_INVT_ON (CMP_OCR_COPS) /*!< CMP output level reverse */
/**
* @}
*/
/**
* @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge
* @{
*/
#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */
#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */
#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */
#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */
/**
* @}
*/
/**
* @defgroup CMP_Out_Filter CMP Output Filter Configuration
* @{
*/
#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */
#define CMP_OUT_FILTER_CLK (1U << CMP_FIR_FCKS_POS)
#define CMP_OUT_FILTER_CLK_DIV8 (2U << CMP_FIR_FCKS_POS)
#define CMP_OUT_FILTER_CLK_DIV32 (3U << CMP_FIR_FCKS_POS)
/**
* @}
*/
/**
* @defgroup CMP_BlankWindow_Src CMP Output blank window Function Control Signal
* @{
*/
/* CMP1 blank window signal */
#define CMP1_BLANKWIN_TMRA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_1_PWM1 for CMP1 */
#define CMP1_BLANKWIN_TMRA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_1_PWM2 for CMP1 */
#define CMP1_BLANKWIN_TMRA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_1_PWM3 for CMP1 */
#define CMP1_BLANKWIN_TMRA_2_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_2_PWM1 for CMP1 */
#define CMP1_BLANKWIN_TMRA_2_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_2_PWM2 for CMP1 */
#define CMP1_BLANKWIN_TMRA_2_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_2_PWM3 for CMP1 */
#define CMP1_BLANKWIN_TMR6_1_PWMA (CMP_TWSR_CTWS6) /*!< Select TMR6_1_PWMA for CMP1 */
#define CMP1_BLANKWIN_TMR6_2_PWMA (CMP_TWSR_CTWS7) /*!< Select TMR6_2_PWMA for CMP1 */
#define CMP1_BLANKWIN_TMR6_3_PWMA (CMP_TWSR_CTWS8) /*!< Select TMR6_3_PWMA for CMP1 */
#define CMP1_BLANKWIN_TMR6_4_PWMA (CMP_TWSR_CTWS9) /*!< Select TMR6_4_PWMA for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_1_OUH for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_1_OUL for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_1_OVH for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_1_OVL for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_1_OWH for CMP1 */
#define CMP1_BLANKWIN_TMR4_1_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_1_OWL for CMP1 */
/* CMP2 blank window signal */
#define CMP2_BLANKWIN_TMRA_3_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_3_PWM1 for CMP2 */
#define CMP2_BLANKWIN_TMRA_3_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_3_PWM2 for CMP2 */
#define CMP2_BLANKWIN_TMRA_3_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_3_PWM3 for CMP2 */
#define CMP2_BLANKWIN_TMRA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_4_PWM1 for CMP2 */
#define CMP2_BLANKWIN_TMRA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_4_PWM2 for CMP2 */
#define CMP2_BLANKWIN_TMRA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_4_PWM3 for CMP2 */
#define CMP2_BLANKWIN_TMR6_5_PWMA (CMP_TWSR_CTWS6) /*!< Select TMR6_5_PWMA for CMP2 */
#define CMP2_BLANKWIN_TMR6_6_PWMA (CMP_TWSR_CTWS7) /*!< Select TMR6_6_PWMA for CMP2 */
#define CMP2_BLANKWIN_TMR6_7_PWMA (CMP_TWSR_CTWS8) /*!< Select TMR6_7_PWMA for CMP2 */
#define CMP2_BLANKWIN_TMR6_8_PWMA (CMP_TWSR_CTWS9) /*!< Select TMR6_8_PWMA for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_2_OUH for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_2_OUL for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_2_OVH for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_2_OVL for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_2_OWH for CMP2 */
#define CMP2_BLANKWIN_TMR4_2_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_2_OWL for CMP2 */
/* CMP3 blank window signal */
#define CMP3_BLANKWIN_TMRA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_1_PWM1 for CMP3 */
#define CMP3_BLANKWIN_TMRA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_1_PWM2 for CMP3 */
#define CMP3_BLANKWIN_TMRA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_1_PWM3 for CMP3 */
#define CMP3_BLANKWIN_TMRA_3_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_3_PWM1 for CMP3 */
#define CMP3_BLANKWIN_TMRA_3_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_3_PWM2 for CMP3 */
#define CMP3_BLANKWIN_TMRA_3_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_3_PWM3 for CMP3 */
#define CMP3_BLANKWIN_TMR6_1_PWMB (CMP_TWSR_CTWS6) /*!< Select TMR6_1_PWMB for CMP3 */
#define CMP3_BLANKWIN_TMR6_2_PWMB (CMP_TWSR_CTWS7) /*!< Select TMR6_2_PWMB for CMP3 */
#define CMP3_BLANKWIN_TMR6_3_PWMB (CMP_TWSR_CTWS8) /*!< Select TMR6_3_PWMB for CMP3 */
#define CMP3_BLANKWIN_TMR6_4_PWMB (CMP_TWSR_CTWS9) /*!< Select TMR6_4_PWMB for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_3_OUH for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_3_OUL for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_3_OVH for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_3_OVL for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_3_OWH for CMP3 */
#define CMP3_BLANKWIN_TMR4_3_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_3_OWL for CMP3 */
/* CMP4 blank window signal */
#define CMP4_BLANKWIN_TMRA_2_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_2_PWM1 for CMP4 */
#define CMP4_BLANKWIN_TMRA_2_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_2_PWM2 for CMP4 */
#define CMP4_BLANKWIN_TMRA_2_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_2_PWM3 for CMP3 */
#define CMP4_BLANKWIN_TMRA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_4_PWM1 for CMP4 */
#define CMP4_BLANKWIN_TMRA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_4_PWM2 for CMP4 */
#define CMP4_BLANKWIN_TMRA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_4_PWM3 for CMP4 */
#define CMP4_BLANKWIN_TMR6_5_PWMB (CMP_TWSR_CTWS6) /*!< Select TMR6_5_PWMB for CMP4 */
#define CMP4_BLANKWIN_TMR6_6_PWMB (CMP_TWSR_CTWS7) /*!< Select TMR6_6_PWMB for CMP4 */
#define CMP4_BLANKWIN_TMR6_7_PWMB (CMP_TWSR_CTWS8) /*!< Select TMR6_7_PWMB for CMP4 */
#define CMP4_BLANKWIN_TMR6_8_PWMB (CMP_TWSR_CTWS9) /*!< Select TMR6_8_PWMB for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_4_OUH for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_4_OUL for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_4_OVH for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_4_OVL for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_4_OWH for CMP4 */
#define CMP4_BLANKWIN_TMR4_3_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_4_OWL for CMP4 */
/**
* @}
*/
/**
* @defgroup CMP_BlankWindow_Valid_Level CMP Blank Window Valid Level
* @{
*/
#define CMP_BLANKWIN_VALID_LVL_LOW (0U) /*!< Blank window valid level is low */
#define CMP_BLANKWIN_VALID_LVL_HIGH (1U) /*!< Blank window valid level is high */
/**
* @}
*/
/**
* @defgroup CMP_BlankWindow_output_Level CMP Output Level When Blank Windows Valid
* @{
*/
#define CMP_BLANKWIN_OUTPUT_LVL_LOW (0U) /*!< Output low when blank windows valid */
#define CMP_BLANKWIN_OUTPUT_LVL_HIGH (CMP_OCR_TWOL) /*!< Output high when blank windows valid */
/**
* @}
*/
/**
* @defgroup CMP_8BitDAC_Adc_Ref_Switch CMP 8 bit DAC ADC Reference Voltage Switch
* @{
*/
/**
* @}
*/
/**
* @defgroup CMP_8Bit_Dac_Ch CMP 8 bit DAC Channel
* @{
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CMP_Global_Functions
* @{
*/
int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit);
int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit);
void CMP_DeInit(CM_CMP_TypeDef *CMPx);
void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx);
void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter);
void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity);
void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput);
void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput);
int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit);
int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit);
void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc);
int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowInit);
void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_CMP_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_CMP_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_crc.h
* @brief This file contains all the functions prototypes of the CRC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_CRC_H__
#define __HC32_LL_CRC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_CRC
* @{
*/
#if (LL_CRC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CRC_Global_Types CRC Global Types
* @{
*/
/**
* @brief CRC initialization structure definition
*/
typedef struct {
uint32_t u32Protocol; /*!< Specifies CRC Protocol.
This parameter can be a value of @ref CRC_Protocol_Control_Bit */
uint32_t u32InitValue; /*!< Specifies initial CRC value and value upper 16 bit is ignored when using CRC16.
This parameter can be a value of @ref CRC_Initial_Value */
} stc_crc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CRC_Global_Macros CRC Global Macros
* @{
*/
/**
* @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit
* @note: - CRC16 polynomial is X^16 + X^12 + X^5 + 1
* - CRC32 polynomial is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + \
* X^10 + X^8 + X^7 + X^5 + X^4 + X^2 + X + 1
* @{
*/
#define CRC_CRC16 (0x0UL)
#define CRC_CRC32 (CRC_CR_CR)
/**
* @}
*/
/**
* @defgroup CRC_Initial_Value CRC Initial Value
* @{
*/
#define CRC16_INIT_VALUE (0xFFFFUL)
#define CRC32_INIT_VALUE (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CRC_Global_Functions
* @{
*/
int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit);
int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit);
void CRC_DeInit(void);
en_flag_status_t CRC_GetResultStatus(void);
uint32_t CRC_AccumulateData8(const uint8_t au8Data[], uint32_t u32Len);
uint32_t CRC_AccumulateData16(const uint16_t au16Data[], uint32_t u32Len);
uint32_t CRC_AccumulateData32(const uint32_t au32Data[], uint32_t u32Len);
uint32_t CRC_CalculateData8(uint32_t u32InitValue, const uint8_t au8Data[], uint32_t u32Len);
uint32_t CRC_CalculateData16(uint32_t u32InitValue, const uint16_t au16Data[], uint32_t u32Len);
uint32_t CRC_CalculateData32(uint32_t u32InitValue, const uint32_t au32Data[], uint32_t u32Len);
en_flag_status_t CRC_CheckData8(uint32_t u32InitValue, const uint8_t au8Data[],
uint32_t u32Len, uint32_t u32ExpectValue);
en_flag_status_t CRC_CheckData16(uint32_t u32InitValue, const uint16_t au16Data[],
uint32_t u32Len, uint32_t u32ExpectValue);
en_flag_status_t CRC_CheckData32(uint32_t u32InitValue, const uint32_t au32Data[],
uint32_t u32Len, uint32_t u32ExpectValue);
/**
* @}
*/
#endif /* LL_CRC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_CRC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_ctc.h
* @brief This file contains all the functions prototypes of the Clock Trimming
* Controller(CTC) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_CTC_H__
#define __HC32_LL_CTC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_CTC
* @{
*/
#if (LL_CTC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CTC_Global_Types CTC Global Types
* @{
*/
/**
* @brief CTC continuous trim initialization structure definition
*/
typedef struct {
uint32_t u32RefClockFreq; /*!< Reference clock frequency
This parameter should refer user manual recommended values */
uint32_t u32RefClockSrc; /*!< Reference clock source selection
This parameter can be a value of @ref CTC_Continuous_Trim_Reference_Clock_Source */
uint32_t u32RefClockDiv; /*!< Reference clock division
This parameter can be a value of @ref CTC_Reference_Clock_Division */
float32_t f32TolerantErrRate; /*!< CTC tolerance deviation
This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */
uint8_t u8TrimValue; /*!< CTC TRMVAL value
This parameter can be a value between Min_Data=0 and Max_Data=0x3F */
} stc_ctc_ct_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CTC_Global_Macros CTC Global Macros
* @{
*/
/**
* @defgroup CTC_Continuous_Trim_Reference_Clock_Source CTC Continuous Trim Reference Clock Source
* @{
*/
#define CTC_REF_CLK_SRC_CTCREF (0UL) /*!< Clock source: CTCREF */
#define CTC_REF_CLK_SRC_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */
#define CTC_REF_CLK_SRC_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */
/**
* @}
*/
/**
* @defgroup CTC_Flag CTC Flag
* @{
*/
#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */
#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */
#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */
#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */
#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OVF | CTC_FLAG_TRIM_UDF | \
CTC_FLAG_TRIM_OK | CTC_FLAG_BUSY)
/**
* @}
*/
/**
* @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division
* @{
*/
#define CTC_REF_CLK_DIV8 (0UL) /*!< REFCLK/8 */
#define CTC_REF_CLK_DIV32 (1UL) /*!< REFCLK/32 */
#define CTC_REF_CLK_DIV128 (2UL) /*!< REFCLK/128 */
#define CTC_REF_CLK_DIV256 (3UL) /*!< REFCLK/256 */
#define CTC_REF_CLK_DIV512 (4UL) /*!< REFCLK/512 */
#define CTC_REF_CLK_DIV1024 (5UL) /*!< REFCLK/1024 */
#define CTC_REF_CLK_DIV2048 (6UL) /*!< REFCLK/2048 */
#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CTC_Global_Functions
* @{
*/
/**
* @brief Start CTC trimming.
* @param None
* @retval None
*/
__STATIC_INLINE void CTC_Start(void)
{
SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN);
}
/**
* @brief Stop CTC trimming.
* @param None
* @retval None
*/
__STATIC_INLINE void CTC_Stop(void)
{
CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN);
}
int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit);
int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit);
int32_t CTC_DeInit(void);
void CTC_IntCmd(en_functional_state_t enNewState);
en_flag_status_t CTC_GetStatus(uint32_t u32Flag);
void CTC_SetTrimValue(uint8_t u8TrimValue);
uint8_t CTC_GetTrimValue(void);
void CTC_SetReloadValue(uint16_t u16ReloadValue);
uint16_t CTC_GetReloadValue(void);
void CTC_SetOffsetValue(uint8_t u8OffsetValue);
uint8_t CTC_GetOffsetValue(void);
/**
* @}
*/
#endif /* LL_CTC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_CTC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_dac.h
* @brief This file contains all the functions prototypes of the DAC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DAC_H__
#define __HC32_LL_DAC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_DAC
* @{
*/
#if (LL_DAC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DAC_Global_Types DAC Global Types
* @{
*/
/**
* @brief Structure definition of DAC initialization.
*/
typedef struct {
uint16_t u16Src; /*!< Data source to be converted
This parameter can be a value of @ref DAC_DATA_SRC */
en_functional_state_t enOutput; /*!< Enable or disable analog output
This parameter can be a value of @ref en_functional_state_t */
} stc_dac_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DAC_Global_Macros DAC Global Macros
* @{
*/
/**
* @defgroup DAC_CH DAC channel
* @{
*/
#define DAC_CH1 (0U)
#define DAC_CH2 (1U)
/**
* @}
*/
/**
* @defgroup DAC_DATA_SRC DAC data source
* @{
*/
#define DAC_DATA_SRC_DATAREG (0U)
#define DAC_DATA_SRC_DCU (DAC_DACR_EXTDSL1)
/**
* @}
*/
/**
* @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern
* @{
*/
#define DAC_DATA_ALIGN_L (DAC_DACR_ALIGN)
#define DAC_DATA_ALIGN_R (0U)
/**
* @}
*/
/**
* @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern
* @{
*/
/**
* @}
*/
#define DAC_DATAREG_VALUE_MAX (4096UL)
/**
* @defgroup DAC_ADP_SELECT DAC ADCx priority select
* @{
*/
#define DAC_ADP_SELECT_ADC1 (DAC_DAADPCR_ADPSL1)
#define DAC_ADP_SELECT_ADC2 (DAC_DAADPCR_ADPSL2)
#define DAC_ADP_SELECT_ADC3 (DAC_DAADPCR_ADPSL3)
#define DAC_ADP_SELECT_ALL (DAC_DAADPCR_ADPSL1 | DAC_DAADPCR_ADPSL2 | DAC_DAADPCR_ADPSL3)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DAC_Global_Functions
* @{
*/
int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit);
int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit);
void DAC_DeInit(CM_DAC_TypeDef *DACx);
void DAC_SetDataSrc(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src);
void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align);
void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
int32_t DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState);
void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState);
int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch);
int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch);
void DAC_StartDualCh(CM_DAC_TypeDef *DACx);
void DAC_StopDualCh(CM_DAC_TypeDef *DACx);
void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data);
void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2);
int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch);
/**
* @}
*/
#endif /* LL_DAC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DAC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_dcu.h
* @brief This file contains all the functions prototypes of the DCU(Data
* Computing Unit) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DCU_H__
#define __HC32_LL_DCU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_DCU
* @{
*/
#if (LL_DCU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DCU_Global_Types DCU Global Types
* @{
*/
/**
* @brief DCU initialization structure definition
*/
typedef struct {
uint32_t u32Mode; /*!< Specifies DCU operation.
This parameter can be a value of @ref DCU_Mode */
uint32_t u32DataWidth; /*!< Specifies DCU data width.
This parameter can be a value of @ref DCU_Data_Width */
} stc_dcu_init_t;
/**
* @brief DCU wave output configure structure definition
*/
typedef struct {
uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
uint32_t u32Step; /*!< Defines the increasing/decreasing step.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
} stc_dcu_wave_config_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DCU_Global_Macros DCU Global Macros
* @{
*/
/**
* @defgroup DCU_Data_Width DCU Data Width
* @{
*/
#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */
#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */
#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */
/**
* @}
*/
/**
* @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition
* @{
*/
#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */
#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */
/**
* @}
*/
/**
* @defgroup DCU_Mode DCU Mode
* @{
*/
#define DCU_MD_INVD (0UL) /*!< DCU invalid */
#define DCU_MD_ADD (1UL) /*!< DCU add operation */
#define DCU_MD_SUB (2UL) /*!< DCU sub operation */
#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */
#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */
#define DCU_MD_CMP (5UL) /*!< DCU compare */
#define DCU_MD_TRIANGLE_WAVE (8UL) /*!< DCU triangle wave output mode */
#define DCU_MD_SAWTOOTH_WAVE_INC (9UL) /*!< DCU increasing sawtooth wave output mode */
#define DCU_MD_SAWTOOTH_WAVE_DEC (10UL) /*!< DCU decreasing sawtooth wave output mode */
/**
* @}
*/
/**
* @defgroup DCU_Flag DCU Flag
* @{
*/
#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */
#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */
#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */
#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */
#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */
#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */
#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */
#define DCU_FLAG_SAWTOOTH_WAVE_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */
#define DCU_FLAG_TRIANGLE_WAVE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */
#define DCU_FLAG_TRIANGLE_WAVE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */
#define DCU_FLAG_ALL (0x00000E7FUL)
/**
* @}
*/
/**
* @defgroup DCU_Category DCU Category
* @{
*/
#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */
#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */
#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */
#define DCU_CATEGORY_WAVE (3UL) /*!< DCU wave mode(sawtooth/triangle wave) */
/**
* @}
*/
/**
* @defgroup DCU_Interrupt_Type DCU Interrupt Type
* @{
*/
/**
* @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt
* @{
* @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode
*/
#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTSEL_INT_LS2) /*!< DCU DATA0 < DATA2 interrupt */
#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTSEL_INT_EQ2) /*!< DCU DATA0 = DATA2 interrupt */
#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTSEL_INT_GT2) /*!< DCU DATA0 > DATA2 interrupt */
#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTSEL_INT_LS1) /*!< DCU DATA0 < DATA1 interrupt */
#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTSEL_INT_EQ1) /*!< DCU DATA0 = DATA1 interrupt */
#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTSEL_INT_GT1) /*!< DCU DATA0 > DATA1 interrupt */
#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \
DCU_INT_CMP_DATA0_EQ_DATA2 | \
DCU_INT_CMP_DATA0_GT_DATA2 | \
DCU_INT_CMP_DATA0_LT_DATA1 | \
DCU_INT_CMP_DATA0_EQ_DATA1 | \
DCU_INT_CMP_DATA0_GT_DATA1)
/**
* @}
*/
/**
* @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt
* @{
*/
#define DCU_INT_CMP_WIN_INSIDE (DCU_INTSEL_INT_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */
#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTSEL_INT_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */
#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE)
/**
* @}
*/
/**
* @defgroup DCU_Operation_Interrupt DCU Operation Interrupt
* @{
*/
#define DCU_INT_OP_CARRY (DCU_INTSEL_INT_OP) /*!< DCU addition overflow or subtraction underflow interrupt */
/**
* @}
*/
/**
* @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt
* @{
*/
#define DCU_INT_SAWTOOTH_WAVE_RELOAD (DCU_INTSEL_INT_RLD) /*!< DCU sawtooth wave mode reload interrupt */
#define DCU_INT_TRIANGLE_WAVE_BOTTOM (DCU_INTSEL_INT_BTM) /*!< DCU triangle wave mode bottom interrupt */
#define DCU_INT_TRIANGLE_WAVE_TOP (DCU_INTSEL_INT_TOP) /*!< DCU triangle wave mode top interrupt */
#define DCU_INT_WAVE_MD_ALL (DCU_INT_TRIANGLE_WAVE_TOP | \
DCU_INT_TRIANGLE_WAVE_BOTTOM | \
DCU_INT_SAWTOOTH_WAVE_RELOAD)
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup DCU_Data_Register_Index DCU Data Register Index
* @{
*/
#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */
#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */
#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DCU_Global_Functions
* @{
*/
/* Initialization and configuration functions */
int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit);
int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit);
int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx);
int32_t DCU_WaveConfig(CM_DCU_TypeDef *DCUx, const stc_dcu_wave_config_t *pstcWaveconfig);
void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode);
void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth);
void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond);
/* Interrupt and flag management functions */
en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState);
void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState);
/* Read and write functions */
uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data);
uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data);
uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data);
/**
* @}
*/
#endif /* LL_DCU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DCU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_def.h
* @brief This file contains LL common definitions: enumeration, macros and
* structures definitions.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DEF_H__
#define __HC32_LL_DEF_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stddef.h>
#include <stdint.h>
/**
* @addtogroup LL_Common
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup LL_Common_Global_Types LL Common Global Types
* @{
*/
/**
* @brief Single precision floating point number (4 byte)
*/
typedef float float32_t;
/**
* @brief Double precision floating point number (8 byte)
*/
typedef double float64_t;
/**
* @brief Function pointer type to void/void function
*/
typedef void (*func_ptr_t)(void);
/**
* @brief Functional state
*/
typedef enum {
DISABLE = 0U,
ENABLE = 1U,
} en_functional_state_t;
/**
* @brief Flag status
*/
typedef enum {
RESET = 0U,
SET = 1U,
} en_flag_status_t, en_int_status_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup LL_Common_Global_Macros LL Common Global Macros
* @{
*/
/**
* @defgroup Compiler_Macros Compiler Macros
* @{
*/
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif /* __UNUSED */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned(4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
/* RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. */
#ifndef __RAM_FUNC
#define __RAM_FUNC
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned (4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: __RAM_FUNC void foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __attribute__((section(".noinit")))
#endif /* __NO_INIT */
#elif defined (__ICCARM__) /*!< IAR Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __weak
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __ramfunc
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __no_init
#endif /* __NO_INIT */
#elif defined (__CC_ARM) /*!< ARM Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __align(4)
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
/* RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((section("RAMCODE")))
#endif /* __RAM_FUNC */
/* Suppress warning message: extended constant initialiser used */
#pragma diag_suppress 1296
#else
#error "unsupported compiler!!"
#endif
/**
* @}
*/
/**
* @defgroup Extend_Macros Extend Macros
* @{
*/
/* Decimal to BCD */
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
/* BCD to decimal */
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
/* Returns the dimension of an array */
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
/* Returns the minimum value out of two values */
#define LL_MIN(x, y) ((x) < (y) ? (x) : (y))
/* Returns the maximum value out of two values */
#define LL_MAX(x, y) ((x) > (y) ? (x) : (y))
/**
* @}
*/
/**
* @defgroup Check_Parameters_Validity Check Parameters Validity
* @{
*/
/* Check Functional State */
#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE))
/**
* @defgroup Check_Address_Align_Validity Check Address Align Validity
* @{
*/
#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup Peripheral_Bit_Band Peripheral Bit Band
* @{
*/
#define __PERIPH_BIT_BAND_BASE (0x42000000UL)
#define __PERIPH_BASE (0x40000000UL)
#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE)
#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE)
#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos)))
/**
* @}
*/
/**
* @defgroup Generic_Error_Codes Generic Error Codes
* @{
*/
#define LL_OK (0) /*!< No error */
#define LL_ERR (-1) /*!< Non-specific error code */
#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */
#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */
#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */
#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */
#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */
#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */
#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */
#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */
/**
* @}
*/
/**
* @defgroup Chip_Module_Switch Chip Module Switch
* @{
*/
#define DDL_ON (1U)
#define DDL_OFF (0U)
/**
* @}
*/
/**
* @defgroup Bit_Mask_Macros Bit Mask Macros
* @{
*/
#define BIT_MASK_00 (1UL << 0U)
#define BIT_MASK_01 (1UL << 1U)
#define BIT_MASK_02 (1UL << 2U)
#define BIT_MASK_03 (1UL << 3U)
#define BIT_MASK_04 (1UL << 4U)
#define BIT_MASK_05 (1UL << 5U)
#define BIT_MASK_06 (1UL << 6U)
#define BIT_MASK_07 (1UL << 7U)
#define BIT_MASK_08 (1UL << 8U)
#define BIT_MASK_09 (1UL << 9U)
#define BIT_MASK_10 (1UL << 10U)
#define BIT_MASK_11 (1UL << 11U)
#define BIT_MASK_12 (1UL << 12U)
#define BIT_MASK_13 (1UL << 13U)
#define BIT_MASK_14 (1UL << 14U)
#define BIT_MASK_15 (1UL << 15U)
#define BIT_MASK_16 (1UL << 16U)
#define BIT_MASK_17 (1UL << 17U)
#define BIT_MASK_18 (1UL << 18U)
#define BIT_MASK_19 (1UL << 19U)
#define BIT_MASK_20 (1UL << 20U)
#define BIT_MASK_21 (1UL << 21U)
#define BIT_MASK_22 (1UL << 22U)
#define BIT_MASK_23 (1UL << 23U)
#define BIT_MASK_24 (1UL << 24U)
#define BIT_MASK_25 (1UL << 25U)
#define BIT_MASK_26 (1UL << 26U)
#define BIT_MASK_27 (1UL << 27U)
#define BIT_MASK_28 (1UL << 28U)
#define BIT_MASK_29 (1UL << 29U)
#define BIT_MASK_30 (1UL << 30U)
#define BIT_MASK_31 (1UL << 31U)
/**
* @}
*/
/**
* @defgroup Register_Macros Register Macros
* @{
*/
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT))
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT)))
#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
#define READ_REG_BIT(REG, BIT) ((REG) & (BIT))
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
#define CLR_REG(REG) ((REG) = (0U))
#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U)))
#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U)))
#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
#define READ_REG(REG) (REG)
#define READ_REG8(REG) (REG)
#define READ_REG16(REG) (REG)
#define READ_REG32(REG) (REG)
#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK)))))
#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK)))))
#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK)))))
#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK)))))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DEF_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_dma.h
* @brief This file contains all the functions prototypes of the DMA driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DMA_H__
#define __HC32_LL_DMA_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_DMA
* @{
*/
#if (LL_DMA_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DMA_Global_Types DMA Global Types
* @{
*/
/**
* @brief DMA basic configuration
*/
typedef struct {
uint32_t u32IntEn; /*!< Specifies the DMA interrupt function.
This parameter can be a value of @ref DMA_Int_Config */
uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */
uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */
uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width.
This parameter can be a value of @ref DMA_DataWidth_Sel */
uint32_t u32BlockSize; /*!< Specifies the DMA block size. */
uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */
uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode.
This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */
uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode.
This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */
} stc_dma_init_t;
/**
* @brief DMA repeat mode configuration
*/
typedef struct {
uint32_t u32Mode; /*!< Specifies the DMA source repeat function.
This parameter can be a value of @ref DMA_Repeat_Config */
uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */
uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */
} stc_dma_repeat_init_t;
/**
* @brief DMA non-sequence mode configuration
*/
typedef struct {
uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function.
This parameter can be a value of @ref DMA_NonSeq_Config */
uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */
uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */
uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */
uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */
} stc_dma_nonseq_init_t;
/**
* @brief DMA Link List Pointer (LLP) mode configuration
*/
typedef struct {
uint32_t u32State; /*!< Specifies the DMA LLP function.
This parameter can be a value of @ref DMA_Llp_En */
uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ.
This parameter can be a value of @ref DMA_Llp_Mode */
uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */
} stc_dma_llp_init_t;
/**
* @brief DMA re-config function configuration
*/
typedef struct {
uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode.
This parameter can be a value of @ref DMA_Reconfig_Count_Sel */
uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode.
This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */
uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode.
This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */
} stc_dma_reconfig_init_t;
/**
* @brief Dma LLP(linked list pointer) descriptor structure definition
*/
typedef struct {
uint32_t SARx; /*!< LLP source address */
uint32_t DARx; /*!< LLP destination address */
uint32_t DTCTLx; /*!< LLP transfer count and block size */
uint32_t RPTx; /*!< LLP source & destination repeat size */
uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */
uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */
uint32_t LLPx; /*!< LLP next list pointer */
uint32_t CHCTLx; /*!< LLP channel control */
} stc_dma_llp_descriptor_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DMA_Global_Macros DMA Global Macros
* @{
*/
/**
* @defgroup DMA_Channel_selection DMA Channel Position selection
* @{
*/
#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */
#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */
#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */
#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */
#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */
#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */
#define DMA_CH6 (0x06U) /*!< DMA Channel 6 */
#define DMA_CH7 (0x07U) /*!< DMA Channel 7 */
/**
* @}
*/
/**
* @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection
* @{
*/
#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */
#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */
#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */
#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */
#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */
#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */
#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */
#define DMA_MX_CH6 (0x40UL) /*!< DMA Channel 6 position */
#define DMA_MX_CH7 (0x80UL) /*!< DMA Channel 7 position */
/**
* @}
*/
/**
* @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection
* @{
*/
#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */
#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */
#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */
#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */
#define DMA_FLAG_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error flag CH.4 */
#define DMA_FLAG_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error flag CH.5 */
#define DMA_FLAG_REQ_ERR_CH6 (DMA_INTSTAT0_REQERR_6) /*!< DMA request error flag CH.6 */
#define DMA_FLAG_REQ_ERR_CH7 (DMA_INTSTAT0_REQERR_7) /*!< DMA request error flag CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection
* @{
*/
#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */
#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */
#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */
#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */
#define DMA_FLAG_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error flag CH.4 */
#define DMA_FLAG_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error flag CH.5 */
#define DMA_FLAG_TRANS_ERR_CH6 (DMA_INTSTAT0_TRNERR_6) /*!< DMA transfer error flag CH.6 */
#define DMA_FLAG_TRANS_ERR_CH7 (DMA_INTSTAT0_TRNERR_7) /*!< DMA transfer error flag CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection
* @{
*/
#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */
#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */
#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */
#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */
#define DMA_FLAG_BTC_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed flag CH.4 */
#define DMA_FLAG_BTC_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed flag CH.5 */
#define DMA_FLAG_BTC_CH6 (DMA_INTSTAT1_BTC_6) /*!< DMA block transfer completed flag CH.6 */
#define DMA_FLAG_BTC_CH7 (DMA_INTSTAT1_BTC_7) /*!< DMA block transfer completed flag CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection
* @{
*/
#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */
#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */
#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */
#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */
#define DMA_FLAG_TC_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed flag CH.4 */
#define DMA_FLAG_TC_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed flag CH.5 */
#define DMA_FLAG_TC_CH6 (DMA_INTSTAT1_TC_6) /*!< DMA transfer completed flag CH.6 */
#define DMA_FLAG_TC_CH7 (DMA_INTSTAT1_TC_7) /*!< DMA transfer completed flag CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection
* @{
*/
#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */
#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */
#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */
#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */
#define DMA_INT_REQ_ERR_CH4 (DMA_INTMASK0_MSKREQERR_4) /*!< DMA request error interrupt CH.4 */
#define DMA_INT_REQ_ERR_CH5 (DMA_INTMASK0_MSKREQERR_5) /*!< DMA request error interrupt CH.5 */
#define DMA_INT_REQ_ERR_CH6 (DMA_INTMASK0_MSKREQERR_6) /*!< DMA request error interrupt CH.6 */
#define DMA_INT_REQ_ERR_CH7 (DMA_INTMASK0_MSKREQERR_7) /*!< DMA request error interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection
* @{
*/
#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */
#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */
#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */
#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */
#define DMA_INT_TRANS_ERR_CH4 (DMA_INTMASK0_MSKTRNERR_4) /*!< DMA transfer error interrupt CH.4 */
#define DMA_INT_TRANS_ERR_CH5 (DMA_INTMASK0_MSKTRNERR_5) /*!< DMA transfer error interrupt CH.5 */
#define DMA_INT_TRANS_ERR_CH6 (DMA_INTMASK0_MSKTRNERR_6) /*!< DMA transfer error interrupt CH.6 */
#define DMA_INT_TRANS_ERR_CH7 (DMA_INTMASK0_MSKTRNERR_7) /*!< DMA transfer error interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection
* @{
*/
#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */
#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */
#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */
#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */
#define DMA_INT_BTC_CH4 (DMA_INTMASK1_MSKBTC_4) /*!< DMA block transfer completed interrupt CH.4 */
#define DMA_INT_BTC_CH5 (DMA_INTMASK1_MSKBTC_5) /*!< DMA block transfer completed interrupt CH.5 */
#define DMA_INT_BTC_CH6 (DMA_INTMASK1_MSKBTC_6) /*!< DMA block transfer completed interrupt CH.6 */
#define DMA_INT_BTC_CH7 (DMA_INTMASK1_MSKBTC_7) /*!< DMA block transfer completed interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection
* @{
*/
#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */
#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */
#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */
#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */
#define DMA_INT_TC_CH4 (DMA_INTMASK1_MSKTC_4) /*!< DMA transfer completed interrupt CH.4 */
#define DMA_INT_TC_CH5 (DMA_INTMASK1_MSKTC_5) /*!< DMA transfer completed interrupt CH.5 */
#define DMA_INT_TC_CH6 (DMA_INTMASK1_MSKTC_6) /*!< DMA transfer completed interrupt CH.6 */
#define DMA_INT_TC_CH7 (DMA_INTMASK1_MSKTC_7) /*!< DMA transfer completed interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_FlagMsk_Sel DMA flag mask selection
* @{
*/
#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */
#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */
/**
* @}
*/
/**
* @defgroup DMA_IntMsk_Sel DMA interrupt mask selection
* @{
*/
#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */
#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */
/**
* @}
*/
/**
* @defgroup DMA_Req_Status_Sel DMA request status
* @{
*/
#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */
#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */
#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */
#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */
#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */
#define DMA_STAT_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */
#define DMA_STAT_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */
#define DMA_STAT_REQ_CH6 (DMA_REQSTAT_CHREQ_6) /*!< DMA request from CH.6 */
#define DMA_STAT_REQ_CH7 (DMA_REQSTAT_CHREQ_7) /*!< DMA request from CH.7 */
#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */
/**
* @}
*/
/**
* @defgroup DMA_Trans_Status_Sel DMA transfer status
* @{
*/
#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */
#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */
#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */
#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */
#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */
#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */
#define DMA_STAT_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */
#define DMA_STAT_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */
#define DMA_STAT_TRANS_CH6 (DMA_CHSTAT_CHACT_6) /*!< DMA transfer status of CH.6 */
#define DMA_STAT_TRANS_CH7 (DMA_CHSTAT_CHACT_7) /*!< DMA transfer status of CH.7 */
#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT)
/**
* @}
*/
/**
* @defgroup DMA_DataWidth_Sel DMA transfer data width
* @{
*/
#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */
#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */
#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */
/**
* @}
*/
/**
* @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable
* @{
*/
#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */
#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */
/**
* @}
*/
/**
* @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete
* @{
*/
#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transfering complete */
#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transfering complete */
/**
* @}
*/
/**
* @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode
* @{
*/
#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */
#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */
#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */
/**
* @}
*/
/**
* @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode
* @{
*/
#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */
#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */
#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */
/**
* @}
*/
/**
* @defgroup DMA_Int_Config DMA interrupt function config
* @{
*/
#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */
#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */
/**
* @}
*/
/**
* @defgroup DMA_Repeat_Config DMA repeat mode function config
* @{
*/
#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */
#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */
#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */
#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */
/**
* @}
*/
/**
* @defgroup DMA_NonSeq_Config DMA non-sequence mode function config
* @{
*/
#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */
#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */
#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */
#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */
/**
* @}
*/
/**
* @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection
* @{
*/
#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */
#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */
#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */
/**
* @}
*/
/**
* @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection
* @{
*/
#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */
#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */
#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */
/**
* @}
*/
/**
* @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection
* @{
*/
#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */
#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */
#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DMA_Global_Functions
* @{
*/
void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState);
en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState);
en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState);
int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count);
int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit);
int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit);
void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit);
int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit);
int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit);
int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit);
void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit);
int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit);
void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
/**
* @}
*/
#endif /* LL_DMA_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DMA_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,416 @@
/**
*******************************************************************************
* @file hc32_ll_dmc.h
* @brief This file contains all the functions prototypes of the EXMC_DMC
* (External Memory Controller: Dynamic Memory Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DMC_H__
#define __HC32_LL_DMC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EXMC
* @{
*/
/**
* @addtogroup LL_DMC
* @{
*/
#if (LL_DMC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Global_Types EXMC_DMC Global Types
* @{
*/
/**
* @brief EXMC_DMC Chip Configuration Structure definition
*/
typedef struct {
uint32_t u32AddrMask; /*!< Defines the address mask.
This parameter can be a value of @ref EXMC_DMC_Mask_Address. */
uint32_t u32AddrMatch; /*!< Defines the address match.
This parameter can be a value between Min_Data = 0x80 and Max_Data = 0x87 */
uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode.
This parameter can be a value of @ref EXMC_DMC_Address_Decode_Mode. */
} stc_exmc_dmc_chip_config_t;
/**
* @brief EXMC_DMC Initialization Structure definition
*/
typedef struct {
uint32_t u32SampleClock; /*!< DMC sample clock.
This parameter can be a value of @ref EXMC_DMC_Sample_Clock. */
uint32_t u32MemoryWidth; /*!< DMC memory width.
This parameter can be a value of @ref EXMC_DMC_Memory_Width. */
uint32_t u32RefreshPeriod; /*!< DMC memory refresh period.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */
uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address.
This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */
uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address.
This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */
uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin.
This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */
uint32_t u32MemClockSel; /*!< Defines the memory clock selection.
This parameter can be a value of @ref EXMC_DMC_Clock_Selection */
uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection.
This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */
uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period.
This parameter can be a value between Min_Data = 0x00 and Max_Data = 0x3F */
uint32_t u32MemBurst; /*!< Defines the number of data accesses.
This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */
uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips.
This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */
struct {
uint8_t u8CASL; /*!< Defines the CAS latency in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8DQSS; /*!< Defines the DQSS in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 3 */
uint8_t u8MRD; /*!< Defines the the mode register command time in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */
uint8_t u8RAS; /*!< Defines the RAS in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint8_t u8RC; /*!< Defines the RC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint8_t u8RCD_B; /*!< Defines the RCD base value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8RCD_P; /*!< Defines the RCD append value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8RFC_B; /*!< Defines the RFC base value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */
uint8_t u8RFC_P; /*!< Defines the RFC append value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */
uint8_t u8RP_B; /*!< Defines the RP base value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8RP_P; /*!< Defines the RP append value in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8RRD; /*!< Defines the RRD in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint8_t u8WR; /*!< Defines the WR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8WTR; /*!< Defines the WTR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8XP; /*!< Defines the XP in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint8_t u8XSR; /*!< Defines the XSR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint8_t u8ESR; /*!< Defines the ESR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stcTimingConfig;
} stc_exmc_dmc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Global_Macros EXMC_DMC Global Macros
* @{
*/
/**
* @defgroup EXMC_DMC_Memory_Width EXMC_DMC Memory Width
* @{
*/
#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL)
#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Chip EXMC_DMC Chip
* @{
*/
#define EXMC_DMC_CHIP0 (0UL) /*!< Chip 0 */
#define EXMC_DMC_CHIP1 (1UL) /*!< Chip 1 */
#define EXMC_DMC_CHIP2 (2UL) /*!< Chip 2 */
#define EXMC_DMC_CHIP3 (3UL) /*!< Chip 3 */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Bank EXMC_DMC Bank
* @{
*/
#define EXMC_DMC_BANK0 (0UL) /*!< Bank 0 */
#define EXMC_DMC_BANK1 (1UL) /*!< Bank 1 */
#define EXMC_DMC_BANK2 (2UL) /*!< Bank 2 */
#define EXMC_DMC_BANK3 (3UL) /*!< Bank 3 */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Current_Status EXMC_DMC Current Status
* @{
*/
#define EXMC_DMC_CURR_STATUS_CONFIG (0UL)
#define EXMC_DMC_CURR_STATUS_RDY (DMC_STSR_STATUS_0)
#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1)
#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Control_State EXMC_DMC Control State
* @{
*/
#define EXMC_DMC_CTRL_STATE_GO (0UL)
#define EXMC_DMC_CTRL_STATE_SLEEP (1UL)
#define EXMC_DMC_CTRL_STATE_WAKEUP (2UL)
#define EXMC_DMC_CTRL_STATE_PAUSE (3UL)
#define EXMC_DMC_CTRL_STATE_CONFIG (4UL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Command EXMC_DMC Command
* @{
*/
#define EXMC_DMC_CMD_PRECHARGE_ALL (0UL) /*!< Precharge all */
#define EXMC_DMC_CMD_AUTO_REFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */
#define EXMC_DMC_CMD_MDREG_CONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */
#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Address_Decode_Mode EXMC_DMC Address Decode Mode
* @{
*/
#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */
#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Column_Bits_Number EXMC_DMC Column Bits Number
* @{
*/
#define EXMC_DMC_COLUMN_BITS_NUM8 (0UL)
#define EXMC_DMC_COLUMN_BITS_NUM9 (1UL << DMC_CPCR_COLBS_POS)
#define EXMC_DMC_COLUMN_BITS_NUM10 (2UL << DMC_CPCR_COLBS_POS)
#define EXMC_DMC_COLUMN_BITS_NUM11 (3UL << DMC_CPCR_COLBS_POS)
#define EXMC_DMC_COLUMN_BITS_NUM12 (4UL << DMC_CPCR_COLBS_POS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Row_Bits_Number EXMC_DMC Row Bits Number
* @{
*/
#define EXMC_DMC_ROW_BITS_NUM11 (0UL)
#define EXMC_DMC_ROW_BITS_NUM12 (1UL << DMC_CPCR_ROWBS_POS)
#define EXMC_DMC_ROW_BITS_NUM13 (2UL << DMC_CPCR_ROWBS_POS)
#define EXMC_DMC_ROW_BITS_NUM14 (3UL << DMC_CPCR_ROWBS_POS)
#define EXMC_DMC_ROW_BITS_NUM15 (4UL << DMC_CPCR_ROWBS_POS)
#define EXMC_DMC_ROW_BITS_NUM16 (5UL << DMC_CPCR_ROWBS_POS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC_DMC Auto Pre-charge Pin
* @{
*/
#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS)
#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_CKE_Output_Selection EXMC_DMC CKE Output Selection
* @{
*/
#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL)
#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Clock_Selection EXMC_DMC Clock Selection
* @{
*/
#define EXMC_DMC_CLK_NORMAL_OUTPUT (0UL)
#define EXMC_DMC_CLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Memory_Burst EXMC_DMC Memory Burst
* @{
*/
#define EXMC_DMC_BURST_1BEAT (0UL)
#define EXMC_DMC_BURST_2BEAT (1UL << DMC_CPCR_BURST_POS)
#define EXMC_DMC_BURST_4BEAT (2UL << DMC_CPCR_BURST_POS)
#define EXMC_DMC_BURST_8BEAT (3UL << DMC_CPCR_BURST_POS)
#define EXMC_DMC_BURST_16BEAT (4UL << DMC_CPCR_BURST_POS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC_DMC Auto Refresh
* @{
*/
#define EXMC_DMC_AUTO_REFRESH_1CHIP (0UL)
#define EXMC_DMC_AUTO_REFRESH_2CHIPS (DMC_CPCR_ACTCP_0)
#define EXMC_DMC_AUTO_REFRESH_3CHIPS (DMC_CPCR_ACTCP_1)
#define EXMC_DMC_AUTO_REFRESH_4CHIPS (DMC_CPCR_ACTCP)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Mask_Address EXMC_DMC Mask Address
* @{
*/
#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL)
#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL)
#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL)
#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Address_Space EXMC_DMC Address Space
* @{
*/
#define EXMC_DMC_ADDR_MIN (0x80000000UL)
#define EXMC_DMC_ADDR_MAX (0x87FFFFFFUL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Sample_Clock EXMC_DMC Sample Clock
* @{
*/
#define EXMC_DMC_SAMPLE_CLK_INTERNCLK (0UL)
#define EXMC_DMC_SAMPLE_CLK_INTERNCLK_INVT (DMC_BACR_CKSEL_0)
#define EXMC_DMC_SAMPLE_CLK_EXTCLK (DMC_BACR_CKSEL_1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_DMC_Global_Functions
* @{
*/
/**
* @brief Get DMC status.
* @param None
* @retval Returned value can be one of the macros group @ref EXMC_DMC_Current_Status
* - EXMC_DMC_CURR_STATUS_CONFIG: Configure status
* - EXMC_DMC_CURR_STATUS_RDY: Ready status
* - EXMC_DMC_CURR_STATUS_PAUSED: Pause status
* - EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status
*/
__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void)
{
return READ_REG32_BIT(CM_DMC->STSR, DMC_STSR_STATUS);
}
/* Initialization and configuration EXMC_DMC functions */
int32_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcDmcInit);
int32_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcDmcInit);
void EXMC_DMC_DeInit(void);
void EXMC_DMC_Cmd(en_functional_state_t enNewState);
void EXMC_DMC_SetState(uint32_t u32State);
int32_t EXMC_DMC_ChipConfig(uint32_t u32Chip, const stc_exmc_dmc_chip_config_t *pstcChipConfig);
uint32_t EXMC_DMC_GetChipStartAddr(uint32_t u32Chip);
uint32_t EXMC_DMC_GetChipEndAddr(uint32_t u32Chip);
void EXMC_DMC_SetCommand(uint32_t u32Chip, uint32_t u32Bank, uint32_t u32Cmd, uint32_t u32Addr);
/**
* @}
*/
#endif /* LL_DMC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DMC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,296 @@
/**
*******************************************************************************
* @file hc32_ll_dvp.h
* @brief This file contains all the functions prototypes of the DVP(Digital
* Video Processor) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_DVP_H__
#define __HC32_LL_DVP_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_DVP
* @{
*/
#if (LL_DVP_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DVP_Global_Types DVP Global Types
* @{
*/
/**
* @brief DVP Initialization Structure definition
*/
typedef struct {
uint32_t u32SyncMode; /*!< The DVP sync mode.
This parameter can be a value of @ref DVP_Sync_Mode. */
uint32_t u32DataWidth; /*!< The DVP data interface width.
This parameter can be a value of @ref DVP_Data_Width. */
uint32_t u32CaptureMode; /*!< The DVP capture mode.
This parameter can be a value of @ref DVP_Capture_Mode. */
uint32_t u32CaptureFreq; /*!< The DVP capture frequency.
This parameter can be a value of @ref DVP_Capture_Frequency. */
uint32_t u32PIXCLKPolarity; /*!< The DVP_PIXCLK Polarity.
This parameter can be a value of @ref DVP_PIXCLK_Polarity. */
uint32_t u32HSYNCPolarity; /*!< The DVP_HSYNC Polarity.
This parameter can be a value of @ref DVP_HSYNC_Polarity. */
uint32_t u32VSYNCPolarity; /*!< The DVP_VSYNC Polarity.
This parameter can be a value of @ref DVP_VSYNC_Polarity. */
} stc_dvp_init_t;
/**
* @brief DVP Crop Window Configure definition
*/
typedef struct {
uint16_t u16RowStartLine; /*!< The DVP window row start line.
This parameter can be a value between 0x00 and 0x3FFF */
uint16_t u16ColoumStartLine; /*!< The DVP window coloum start line.
This parameter can be a value between 0x00 and 0x3FFF */
uint16_t u16RowLineSize; /*!< The DVP window row line size.
This parameter can be a value between 0x04 and 0x3FFF */
uint16_t u16ColoumLineSize; /*!< The DVP window coloum line size.
This parameter can be a value between 0x00 and 0x3FFF */
} stc_dvp_crop_window_config_t;
/**
* @brief DVP Software Sync Code definition
*/
typedef struct {
uint8_t u8FrameStartSyncCode; /*!< The sync code of the frame start delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint8_t u8LineStartSyncCode; /*!< The sync code of the line start delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint8_t u8LineEndSyncCode; /*!< The sync code of the line end delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint8_t u8FrameEndSyncCode; /*!< The sync code of the frame end delimiter.
This parameter can be a value between 0x00 and 0xFF */
} stc_dvp_sw_sync_code_t;
/**
* @brief DVP Software Mask Code definition
*/
typedef struct {
uint8_t u8FrameStartMaskCode; /*!< The mask code of the frame start delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint8_t u8LineStartMaskCode; /*!< The mask code of the line start delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint8_t u8LineEndMaskCode; /*!< The mask code of the line end delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint8_t u8FrameEndMaskCode; /*!< The mask code of the frame end delimiter.
This parameter can be a value between between 0x00 and 0xFF */
} stc_dvp_sw_mask_code_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DVP_Global_Macros DVP Global Macros
* @{
*/
/**
* @defgroup DVP_Capture_Mode DVP Capture Mode
* @{
*/
#define DVP_CAPT_MD_CONTINUOS_FRAME (0UL)
#define DVP_CAPT_MD_SINGLE_FRAME (DVP_CTR_CAPMD)
/**
* @}
*/
/**
* @defgroup DVP_Sync_Mode DVP Sync Mode
* @{
*/
#define DVP_SYNC_MD_HW (0UL) /*!< Hardware sync */
#define DVP_SYNC_MD_SW (DVP_CTR_SWSYNC) /*!< Software sync */
/**
* @}
*/
/**
* @defgroup DVP_PIXCLK_Polarity DVP PIXCLK Polarity
* @{
*/
#define DVP_PIXCLK_FALLING (0UL) /*!< DVP_PIXCLK active on Falling edge */
#define DVP_PIXCLK_RISING (DVP_CTR_PIXCKSEL) /*!< DVP_PIXCLK active on Rising edge */
/**
* @}
*/
/**
* @defgroup DVP_HSYNC_Polarity DVP HSYNC Polarity
* @{
*/
#define DVP_HSYNC_LOW (0UL) /*!< DVP_HSYNC active Low */
#define DVP_HSYNC_HIGH (DVP_CTR_HSYNCSEL) /*!< DVP_HSYNC active High */
/**
* @}
*/
/**
* @defgroup DVP_VSYNC_Polarity DVP VSYNC Polarity
* @{
*/
#define DVP_VSYNC_LOW (0UL) /*!< DVP_VSYNC active Low */
#define DVP_VSYNC_HIGH (DVP_CTR_VSYNCSEL) /*!< DVP_VSYNC active High */
/**
* @}
*/
/**
* @defgroup DVP_Capture_Frequency DVP Capture Frequency
* @{
*/
#define DVP_CAPT_FREQ_ALL_FRAME (0UL) /*!< All frames are captured */
#define DVP_CAPT_FREQ_ONT_TIME_2FRAME (DVP_CTR_CAPFRC_0) /*!< One frame per 2 frames captured */
#define DVP_CAPT_FREQ_ONT_TIME_4FRAME (DVP_CTR_CAPFRC_1) /*!< One frame per 4 frames captured */
/**
* @}
*/
/**
* @defgroup DVP_Data_Width DVP Data Width
* @{
*/
#define DVP_DATA_WIDTH_8BIT (0UL) /*!< DVP captures 8-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_10BIT (DVP_CTR_BITSEL_0) /*!< DVP captures 10-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_12BIT (DVP_CTR_BITSEL_1) /*!< DVP captures 12-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_14BIT (DVP_CTR_BITSEL) /*!< DVP captures 14-bit data on every DVP_PIXCLK clock */
/**
* @}
*/
/**
* @defgroup DVP_Flag DVP Flag
* @{
*/
#define DVP_FLAG_FRAME_START (DVP_STR_FSF) /*!< Frame start flag */
#define DVP_FLAG_LINE_START (DVP_STR_LSF) /*!< Line start flag */
#define DVP_FLAG_LINE_END (DVP_STR_LEF) /*!< Line end flag */
#define DVP_FLAG_FRAME_END (DVP_STR_FEF) /*!< Frame end flag */
#define DVP_FLAG_FIFO_OVF (DVP_STR_FIFOERF) /*!< FIFO overflow error flag */
#define DVP_FLAG_SYNC_ERR (DVP_STR_SQUERF) /*!< Sync error flag */
#define DVP_FLAG_ALL (DVP_FLAG_SYNC_ERR | \
DVP_FLAG_FIFO_OVF | \
DVP_FLAG_LINE_END | \
DVP_FLAG_LINE_START | \
DVP_FLAG_FRAME_END | \
DVP_FLAG_FRAME_START)
/**
* @}
*/
/**
* @defgroup DVP_Interrupt DVP Interrupt
* @{
*/
#define DVP_INT_FRAME_START (DVP_IER_FSIEN) /*!< Frame start interrupt */
#define DVP_INT_LINE_START (DVP_IER_LSIEN) /*!< Line start interrupt */
#define DVP_INT_LINE_END (DVP_IER_LEIEN) /*!< Line end interrupt */
#define DVP_INT_FRAME_END (DVP_IER_FEIEN) /*!< Frame end interrupt */
#define DVP_INT_FIFO_OVF (DVP_IER_FIFOERIEN) /*!< FIFO overflow error interrupt */
#define DVP_INT_SYNC_ERR (DVP_IER_SQUERIEN) /*!< Sync error interrupt */
#define DVP_INT_ALL (DVP_INT_SYNC_ERR | \
DVP_INT_FIFO_OVF | \
DVP_INT_LINE_END | \
DVP_INT_LINE_START | \
DVP_INT_FRAME_END | \
DVP_INT_FRAME_START)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DVP_Global_Functions
* @{
*/
int32_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit);
int32_t DVP_Init(const stc_dvp_init_t *pstcDvpInit);
void DVP_DeInit(void);
void DVP_Cmd(en_functional_state_t enNewState);
void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
void DVP_CropCmd(en_functional_state_t enNewState);
void DVP_JPEGCmd(en_functional_state_t enNewState);
void DVP_CaptrueCmd(en_functional_state_t enNewState);
en_flag_status_t DVP_GetStatus(uint32_t u32Flag);
void DVP_ClearStatus(uint32_t u32Flag);
int32_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode);
int32_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode);
int32_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig);
/**
* @}
*/
#endif /* LL_DVP_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_DVP_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_efm.h
* @brief This file contains all the functions prototypes of the EFM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_EFM_H__
#define __HC32_LL_EFM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EFM
* @{
*/
#if (LL_EFM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EFM_Global_Types EFM Global Types
* @{
*/
/**
* @brief EFM unique ID definition
*/
typedef struct {
uint32_t u32UniqueID0; /*!< unique ID 0. */
uint32_t u32UniqueID1; /*!< unique ID 1. */
uint32_t u32UniqueID2; /*!< unique ID 2. */
} stc_efm_unique_id_t;
typedef struct {
uint32_t u32State;
uint32_t u32Addr;
uint32_t u32Size;
} stc_efm_remap_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EFM_Global_Macros EFM Global Macros
* @{
*/
/**
* @defgroup EFM_Address EFM Address Area
* @{
*/
#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */
#define EFM_END_ADDR (0x001FFFFFUL) /*!< Flash end address */
#define EFM_OTP_START_ADDR1 (0x00000000UL) /*!< OTP start address */
#define EFM_OTP_END_ADDR1 (0x0001FFFFUL)
#define EFM_OTP_START_ADDR (0x03000000UL)
#define EFM_OTP_END_ADDR (0x030017FFUL) /*!< OTP end address */
#define EFM_OTP_LOCK_ADDR_START (0x03001800UL) /*!< OTP lock address */
#define EFM_OTP_LOCK_ADDR_END (0x03001AD7UL) /*!< OTP lock address */
#define EFM_OTP_ENABLE_ADDR (0x03001AD8UL)
#define EFM_FLASH_1_START_ADDR (0x00100000UL)
/**
* @}
*/
/**
* @defgroup EFM_Chip_Sel EFM Chip Selection
* @{
*/
#define EFM_CHIP0 (EFM_FSTP_F0STP)
#define EFM_CHIP1 (EFM_FSTP_F1STP)
#define EFM_CHIP_ALL (EFM_FSTP_F0STP | EFM_FSTP_F1STP)
/**
* @}
*/
/**
* @defgroup EFM_Bus_Status EFM Bus Status
* @{
*/
#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */
#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */
/**
* @}
*/
/**
* @defgroup EFM_Wait_Cycle EFM Wait Cycle
* @{
*/
#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */
#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */
#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */
#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */
#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */
#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */
#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */
#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */
#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */
#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */
#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */
#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */
#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */
#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */
#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */
#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */
/**
* @}
*/
/**
* @defgroup EFM_Swap_Address EFM Swap Address
* @{
*/
#define EFM_SWAP_ADDR (0x03002000UL)
#define EFM_SWAP_DATA (0x005A5A5AUL)
/**
* @}
*/
/**
* @defgroup EFM_WriteLock_Sel EFM Write Protect Lock Selection
* @{
*/
#define EFM_WRLOCK0 (EFM_WLOCK_WLOCK_0) /*!< F0NWPRT0 controlled sector lock */
#define EFM_WRLOCK1 (EFM_WLOCK_WLOCK_1) /*!< F0NWPRT1 controlled sector lock */
#define EFM_WRLOCK2 (EFM_WLOCK_WLOCK_2) /*!< F0NWPRT2 controlled sector lock */
#define EFM_WRLOCK3 (EFM_WLOCK_WLOCK_3) /*!< F0NWPRT3 controlled sector lock */
#define EFM_WRLOCK4 (EFM_WLOCK_WLOCK_4) /*!< F1NWPRT0 controlled sector lock */
#define EFM_WRLOCK5 (EFM_WLOCK_WLOCK_5) /*!< F1NWPRT1 controlled sector lock */
#define EFM_WRLOCK6 (EFM_WLOCK_WLOCK_6) /*!< F1NWPRT2 controlled sector lock */
#define EFM_WRLOCK7 (EFM_WLOCK_WLOCK_7) /*!< F1NWPRT3 controlled sector lock */
/**
* @}
*/
/**
* @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection
* @{
*/
#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */
#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */
#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */
#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */
#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */
#define EFM_MD_ERASE_ONE_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< A flash Chip erase mode */
#define EFM_MD_ERASE_ALL_CHIP (0x6UL << EFM_FWMC_PEMOD_POS) /*!< All chip erase mode */
/**
* @}
*/
/**
* @defgroup EFM_Flag_Sel EFM Flag Selection
* @{
*/
#define EFM_FLAG_OTPWERR (EFM_FSR_OTPWERR0) /*!< EFM Flash0 otp Programming/erase error flag. */
#define EFM_FLAG_PEPRTERR (EFM_FSR_PRTWERR0) /*!< EFM Flash0 write protect address error flag. */
#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR0) /*!< EFM Flash0 programming size error flag. */
#define EFM_FLAG_PGMISMTCH (EFM_FSR_MISMTCH0) /*!< EFM Flash0 programming missing match error flag. */
#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND0) /*!< EFM Flash0 end of operation flag. */
#define EFM_FLAG_COLERR (EFM_FSR_COLERR0) /*!< EFM Flash0 read collide error flag. */
#define EFM_FLAG_RDY (EFM_FSR_RDY0) /*!< EFM Flash0 ready flag. */
#define EFM_FLAG_PEPRTERR1 (EFM_FSR_PRTWERR1) /*!< EFM Flash1 write protect address error flag. */
#define EFM_FLAG_PGSZERR1 (EFM_FSR_PGSZERR1) /*!< EFM Flash1 programming size error flag. */
#define EFM_FLAG_PGMISMTCH1 (EFM_FSR_MISMTCH1) /*!< EFM Flash1 programming missing match error flag. */
#define EFM_FLAG_OPTEND1 (EFM_FSR_OPTEND1) /*!< EFM Flash1 end of operation flag. */
#define EFM_FLAG_COLERR1 (EFM_FSR_COLERR1) /*!< EFM Flash1 read collide error flag. */
#define EFM_FLAG_RDY1 (EFM_FSR_RDY1) /*!< EFM Flash1 ready flag. */
#define EFM_FLAG_ALL (EFM_FLAG_OTPWERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | EFM_FLAG_PGMISMTCH | \
EFM_FLAG_OPTEND | EFM_FLAG_COLERR | EFM_FLAG_PEPRTERR1 | EFM_FLAG_PGSZERR1 | \
EFM_FLAG_OPTEND1 | EFM_FLAG_COLERR1 | EFM_FLAG_RDY | EFM_FLAG_PGMISMTCH1 | \
EFM_FLAG_RDY1)
/**
* @}
*/
/**
* @defgroup EFM_Interrupt_Sel EFM Interrupt Selection
* @{
*/
#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */
#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */
#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */
#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE)
/**
* @}
*/
/**
* @defgroup EFM_Keys EFM Keys
* @{
*/
#define EFM_REG_UNLOCK_KEY1 (0x0123UL)
#define EFM_REG_UNLOCK_KEY2 (0x3210UL)
#define EFM_REG_LOCK_KEY (0x0000UL)
/**
* @}
*/
/**
* @defgroup EFM_Sector_Size EFM Sector Size
* @{
*/
#define SECTOR_SIZE (0x2000UL)
/**
* @}
*/
/**
* @defgroup EFM_Sector_Address EFM Sector Address
* @{
*/
#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x))
/**
* @}
*/
/**
* @defgroup EFM_OTP_Base_Address EFM Otp Base Address
* @{
*/
#define EFM_OTP_BASE1_ADDR (0x00000000UL)
#define EFM_OTP_BASE1_SIZE (0x2000UL)
#define EFM_OTP_BASE1_OFFSET (0UL)
#define EFM_OTP_BASE2_ADDR (0x03000000UL)
#define EFM_OTP_BASE2_SIZE (0x800UL)
#define EFM_OTP_BASE2_OFFSET (16UL)
#define EFM_OTP_BASE3_ADDR (0x03001000UL)
#define EFM_OTP_BASE3_SIZE (0x100UL)
#define EFM_OTP_BASE3_OFFSET (18UL)
#define EFM_OTP_BASE4_ADDR (0x03001400UL)
#define EFM_OTP_BASE4_SIZE (0x10UL)
#define EFM_OTP_BASE4_OFFSET (22UL)
#define EFM_OTP_BASE5_ADDR (0x03001600UL)
#define EFM_OTP_BASE5_SIZE (0x04UL)
#define EFM_OTP_BASE5_OFFSET (54UL)
#define EFM_OTP_LOCK_ADDR (0x03001800UL)
/**
* @}
*/
/**
* @defgroup EFM_OTP_Address EFM Otp Address
* @{
*/
#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK15 (EFM_OTP_BASE1_ADDR + ((15UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
#define EFM_OTP_BLOCK16 (EFM_OTP_BASE2_ADDR + ((16UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE))
#define EFM_OTP_BLOCK17 (EFM_OTP_BASE2_ADDR + ((17UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE))
#define EFM_OTP_BLOCK18 (EFM_OTP_BASE3_ADDR + ((18UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
#define EFM_OTP_BLOCK19 (EFM_OTP_BASE3_ADDR + ((19UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
#define EFM_OTP_BLOCK20 (EFM_OTP_BASE3_ADDR + ((20UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
#define EFM_OTP_BLOCK21 (EFM_OTP_BASE3_ADDR + ((21UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
#define EFM_OTP_BLOCK22 (EFM_OTP_BASE4_ADDR + ((22UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK23 (EFM_OTP_BASE4_ADDR + ((23UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK24 (EFM_OTP_BASE4_ADDR + ((24UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK25 (EFM_OTP_BASE4_ADDR + ((25UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK26 (EFM_OTP_BASE4_ADDR + ((26UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK27 (EFM_OTP_BASE4_ADDR + ((27UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK28 (EFM_OTP_BASE4_ADDR + ((28UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK29 (EFM_OTP_BASE4_ADDR + ((29UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK30 (EFM_OTP_BASE4_ADDR + ((30UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK31 (EFM_OTP_BASE4_ADDR + ((31UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK32 (EFM_OTP_BASE4_ADDR + ((32UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK33 (EFM_OTP_BASE4_ADDR + ((33UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK34 (EFM_OTP_BASE4_ADDR + ((34UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK35 (EFM_OTP_BASE4_ADDR + ((35UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK36 (EFM_OTP_BASE4_ADDR + ((36UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK37 (EFM_OTP_BASE4_ADDR + ((37UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK38 (EFM_OTP_BASE4_ADDR + ((38UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK39 (EFM_OTP_BASE4_ADDR + ((39UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK40 (EFM_OTP_BASE4_ADDR + ((40UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK41 (EFM_OTP_BASE4_ADDR + ((41UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK42 (EFM_OTP_BASE4_ADDR + ((42UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK43 (EFM_OTP_BASE4_ADDR + ((43UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK44 (EFM_OTP_BASE4_ADDR + ((44UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK45 (EFM_OTP_BASE4_ADDR + ((45UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK46 (EFM_OTP_BASE4_ADDR + ((46UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK47 (EFM_OTP_BASE4_ADDR + ((47UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK48 (EFM_OTP_BASE4_ADDR + ((48UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK49 (EFM_OTP_BASE4_ADDR + ((49UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK50 (EFM_OTP_BASE4_ADDR + ((50UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK51 (EFM_OTP_BASE4_ADDR + ((51UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK52 (EFM_OTP_BASE4_ADDR + ((52UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK53 (EFM_OTP_BASE4_ADDR + ((53UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
#define EFM_OTP_BLOCK54 (EFM_OTP_BASE5_ADDR + ((54UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK55 (EFM_OTP_BASE5_ADDR + ((55UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK56 (EFM_OTP_BASE5_ADDR + ((56UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK57 (EFM_OTP_BASE5_ADDR + ((57UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK58 (EFM_OTP_BASE5_ADDR + ((58UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK59 (EFM_OTP_BASE5_ADDR + ((59UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK60 (EFM_OTP_BASE5_ADDR + ((60UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK61 (EFM_OTP_BASE5_ADDR + ((61UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK62 (EFM_OTP_BASE5_ADDR + ((62UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK63 (EFM_OTP_BASE5_ADDR + ((63UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK64 (EFM_OTP_BASE5_ADDR + ((64UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK65 (EFM_OTP_BASE5_ADDR + ((65UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK66 (EFM_OTP_BASE5_ADDR + ((66UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK67 (EFM_OTP_BASE5_ADDR + ((67UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK68 (EFM_OTP_BASE5_ADDR + ((68UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK69 (EFM_OTP_BASE5_ADDR + ((69UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK70 (EFM_OTP_BASE5_ADDR + ((70UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK71 (EFM_OTP_BASE5_ADDR + ((71UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK72 (EFM_OTP_BASE5_ADDR + ((72UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK73 (EFM_OTP_BASE5_ADDR + ((73UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK74 (EFM_OTP_BASE5_ADDR + ((74UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK75 (EFM_OTP_BASE5_ADDR + ((75UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK76 (EFM_OTP_BASE5_ADDR + ((76UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK77 (EFM_OTP_BASE5_ADDR + ((77UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK78 (EFM_OTP_BASE5_ADDR + ((78UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK79 (EFM_OTP_BASE5_ADDR + ((79UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK80 (EFM_OTP_BASE5_ADDR + ((80UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK81 (EFM_OTP_BASE5_ADDR + ((81UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK82 (EFM_OTP_BASE5_ADDR + ((82UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK83 (EFM_OTP_BASE5_ADDR + ((83UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK84 (EFM_OTP_BASE5_ADDR + ((84UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK85 (EFM_OTP_BASE5_ADDR + ((85UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK86 (EFM_OTP_BASE5_ADDR + ((86UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK87 (EFM_OTP_BASE5_ADDR + ((87UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK88 (EFM_OTP_BASE5_ADDR + ((88UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK89 (EFM_OTP_BASE5_ADDR + ((89UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK90 (EFM_OTP_BASE5_ADDR + ((90UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK91 (EFM_OTP_BASE5_ADDR + ((91UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK92 (EFM_OTP_BASE5_ADDR + ((92UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK93 (EFM_OTP_BASE5_ADDR + ((93UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK94 (EFM_OTP_BASE5_ADDR + ((94UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK95 (EFM_OTP_BASE5_ADDR + ((95UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK96 (EFM_OTP_BASE5_ADDR + ((96UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK97 (EFM_OTP_BASE5_ADDR + ((97UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK98 (EFM_OTP_BASE5_ADDR + ((98UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK99 (EFM_OTP_BASE5_ADDR + ((99UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK100 (EFM_OTP_BASE5_ADDR + ((100UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK101 (EFM_OTP_BASE5_ADDR + ((101UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK102 (EFM_OTP_BASE5_ADDR + ((102UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK103 (EFM_OTP_BASE5_ADDR + ((103UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK104 (EFM_OTP_BASE5_ADDR + ((104UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK105 (EFM_OTP_BASE5_ADDR + ((105UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK106 (EFM_OTP_BASE5_ADDR + ((106UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK107 (EFM_OTP_BASE5_ADDR + ((107UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK108 (EFM_OTP_BASE5_ADDR + ((108UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK109 (EFM_OTP_BASE5_ADDR + ((109UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK110 (EFM_OTP_BASE5_ADDR + ((110UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK111 (EFM_OTP_BASE5_ADDR + ((111UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK112 (EFM_OTP_BASE5_ADDR + ((112UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK113 (EFM_OTP_BASE5_ADDR + ((113UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK114 (EFM_OTP_BASE5_ADDR + ((114UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK115 (EFM_OTP_BASE5_ADDR + ((115UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK116 (EFM_OTP_BASE5_ADDR + ((116UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK117 (EFM_OTP_BASE5_ADDR + ((117UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK118 (EFM_OTP_BASE5_ADDR + ((118UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK119 (EFM_OTP_BASE5_ADDR + ((119UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK120 (EFM_OTP_BASE5_ADDR + ((120UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK121 (EFM_OTP_BASE5_ADDR + ((121UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK122 (EFM_OTP_BASE5_ADDR + ((122UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK123 (EFM_OTP_BASE5_ADDR + ((123UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK124 (EFM_OTP_BASE5_ADDR + ((124UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK125 (EFM_OTP_BASE5_ADDR + ((125UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK126 (EFM_OTP_BASE5_ADDR + ((126UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK127 (EFM_OTP_BASE5_ADDR + ((127UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK128 (EFM_OTP_BASE5_ADDR + ((128UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK129 (EFM_OTP_BASE5_ADDR + ((129UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK130 (EFM_OTP_BASE5_ADDR + ((130UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK131 (EFM_OTP_BASE5_ADDR + ((131UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK132 (EFM_OTP_BASE5_ADDR + ((132UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK133 (EFM_OTP_BASE5_ADDR + ((133UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK134 (EFM_OTP_BASE5_ADDR + ((134UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK135 (EFM_OTP_BASE5_ADDR + ((135UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK136 (EFM_OTP_BASE5_ADDR + ((136UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK137 (EFM_OTP_BASE5_ADDR + ((137UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK138 (EFM_OTP_BASE5_ADDR + ((138UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK139 (EFM_OTP_BASE5_ADDR + ((139UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK140 (EFM_OTP_BASE5_ADDR + ((140UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK141 (EFM_OTP_BASE5_ADDR + ((141UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK142 (EFM_OTP_BASE5_ADDR + ((142UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK143 (EFM_OTP_BASE5_ADDR + ((143UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK144 (EFM_OTP_BASE5_ADDR + ((144UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK145 (EFM_OTP_BASE5_ADDR + ((145UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK146 (EFM_OTP_BASE5_ADDR + ((146UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK147 (EFM_OTP_BASE5_ADDR + ((147UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK148 (EFM_OTP_BASE5_ADDR + ((148UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK149 (EFM_OTP_BASE5_ADDR + ((149UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK150 (EFM_OTP_BASE5_ADDR + ((150UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK151 (EFM_OTP_BASE5_ADDR + ((151UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK152 (EFM_OTP_BASE5_ADDR + ((152UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK153 (EFM_OTP_BASE5_ADDR + ((153UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK154 (EFM_OTP_BASE5_ADDR + ((154UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK155 (EFM_OTP_BASE5_ADDR + ((155UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK156 (EFM_OTP_BASE5_ADDR + ((156UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK157 (EFM_OTP_BASE5_ADDR + ((157UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK158 (EFM_OTP_BASE5_ADDR + ((158UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK159 (EFM_OTP_BASE5_ADDR + ((159UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK160 (EFM_OTP_BASE5_ADDR + ((160UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK161 (EFM_OTP_BASE5_ADDR + ((161UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK162 (EFM_OTP_BASE5_ADDR + ((162UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK163 (EFM_OTP_BASE5_ADDR + ((163UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK164 (EFM_OTP_BASE5_ADDR + ((164UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK165 (EFM_OTP_BASE5_ADDR + ((165UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK166 (EFM_OTP_BASE5_ADDR + ((166UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK167 (EFM_OTP_BASE5_ADDR + ((167UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK168 (EFM_OTP_BASE5_ADDR + ((168UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK169 (EFM_OTP_BASE5_ADDR + ((169UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK170 (EFM_OTP_BASE5_ADDR + ((170UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK171 (EFM_OTP_BASE5_ADDR + ((171UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK172 (EFM_OTP_BASE5_ADDR + ((172UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK173 (EFM_OTP_BASE5_ADDR + ((173UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK174 (EFM_OTP_BASE5_ADDR + ((174UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK175 (EFM_OTP_BASE5_ADDR + ((175UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK176 (EFM_OTP_BASE5_ADDR + ((176UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK177 (EFM_OTP_BASE5_ADDR + ((177UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK178 (EFM_OTP_BASE5_ADDR + ((178UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK179 (EFM_OTP_BASE5_ADDR + ((179UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK180 (EFM_OTP_BASE5_ADDR + ((180UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
#define EFM_OTP_BLOCK181 (EFM_OTP_BASE5_ADDR + ((181UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
/**
* @}
*/
/**
* @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address
* @note x at range of 0~14 while HC32F460, HC32F451, HC32F452
* x at range of 0~181 while HC32F4A0, HC32F472
* @{
*/
#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */
/**
* @}
*/
#define EFM_REMAP_REG_LOCK_KEY (0x0000UL)
#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL)
#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL)
/**
* @defgroup EFM_Remap_State EFM remap function state
* @{
*/
#define EFM_REMAP_OFF (0UL)
#define EFM_REMAP_ON EFM_MMF_REMCR_EN
/**
* @}
*/
/**
* @defgroup EFM_Remap_Size EFM remap size definition
* @note refer to chip user manual for details size spec.
* @{
*/
#define EFM_REMAP_4K (12UL)
#define EFM_REMAP_8K (13UL)
#define EFM_REMAP_16K (14UL)
#define EFM_REMAP_32K (15UL)
#define EFM_REMAP_64K (16UL)
#define EFM_REMAP_128K (17UL)
#define EFM_REMAP_256K (18UL)
#define EFM_REMAP_512K (19UL)
/**
* @}
*/
/**
* @defgroup EFM_Remap_Index EFM remap index
* @{
*/
#define EFM_REMAP_IDX0 (0U)
#define EFM_REMAP_IDX1 (1U)
/**
* @}
*/
/**
* @defgroup EFM_Remap_BaseAddr EFM remap base address
* @{
*/
#define EFM_REMAP_BASE_ADDR0 (0x2000000UL)
#define EFM_REMAP_BASE_ADDR1 (0x2080000UL)
/**
* @}
*/
/**
* @defgroup EFM_Remap_Region EFM remap ROM/RAM region
* @{
*/
#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR
#define EFM_REMAP_RAM_START_ADDR (0x1FFE0000UL)
#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EFM_Global_Functions
* @{
*/
/**
* @brief EFM Protect Unlock.
* @param None
* @retval None
*/
__STATIC_INLINE void EFM_REG_Unlock(void)
{
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1);
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2);
}
/**
* @brief EFM Protect Lock.
* @param None
* @retval None
*/
__STATIC_INLINE void EFM_REG_Lock(void)
{
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY);
}
/**
* @brief EFM remap Unlock.
* @param None
* @retval None
*/
__STATIC_INLINE void EFM_REMAP_Unlock(void)
{
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1);
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2);
}
/**
* @brief EFM remap Lock.
* @param None
* @retval None
*/
__STATIC_INLINE void EFM_REMAP_Lock(void)
{
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY);
}
void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState);
void EFM_FWMC_Cmd(en_functional_state_t enNewState);
void EFM_SetBusStatus(uint32_t u32Status);
void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState);
void EFM_ClearStatus(uint32_t u32Flag);
int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle);
int32_t EFM_SetOperateMode(uint32_t u32Mode);
int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen);
int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data);
int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data);
int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
int32_t EFM_SectorErase(uint32_t u32Addr);
int32_t EFM_ChipErase(uint8_t u8Chip);
en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag);
en_flag_status_t EFM_GetStatus(uint32_t u32Flag);
void EFM_GetUID(stc_efm_unique_id_t *pstcUID);
void EFM_DataCacheResetCmd(en_functional_state_t enNewState);
void EFM_PrefetchCmd(en_functional_state_t enNewState);
void EFM_DCacheCmd(en_functional_state_t enNewState);
void EFM_ICacheCmd(en_functional_state_t enNewState);
void EFM_LowVoltageReadCmd(en_functional_state_t enNewState);
int32_t EFM_SwapCmd(en_functional_state_t enNewState);
en_flag_status_t EFM_GetSwapStatus(void);
int32_t EFM_OTP_Lock(uint32_t u32Addr);
int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit);
int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit);
void EFM_REMAP_DeInit(void);
void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState);
void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr);
void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size);
uint32_t EFM_GetCID(void);
void EFM_OTP_WP_Unlock(void);
void EFM_OTP_WP_Lock(void);
int32_t EFM_OTP_Enable(void);
void EFM_SectorProtectRegLock(uint32_t u32RegLock);
void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState);
void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_EFM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_EFM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

509
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32_ll_emb.h Normal file
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@ -0,0 +1,509 @@
/**
*******************************************************************************
* @file hc32_ll_emb.h
* @brief This file contains all the functions prototypes of the EMB
* (Emergency Brake) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_EMB_H__
#define __HC32_LL_EMB_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EMB
* @{
*/
#if (LL_EMB_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EMB_Global_Types EMB Global Types
* @{
*/
/**
* @brief EMB monitor OSC failure configuration
*/
typedef struct {
uint32_t u32OscState; /*!< Enable or disable EMB detect OSC failure function
This parameter can be a value of @ref EMB_OSC_Selection */
} stc_emb_monitor_osc_t;
/**
* @brief EMB monitor EMB port configuration
*/
typedef struct {
uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function
This parameter can be a value of EMB_Port_Selection */
uint32_t u32PortLevel; /*!< EMB detect port level
This parameter can be a value of EMB_Detect_Port_Level */
uint32_t u32PortFilterDiv; /*!< EMB port filter division
This parameter can be a value of EMB_Port_Filter_Clock_Division */
uint32_t u32PortFilterState; /*!< EMB port filter division
This parameter can be a value of EMB_Port_Filter_Selection */
} stc_emb_monitor_port_config_t;
/**
* @brief EMB monitor TMR4 or TMR6 PWM configuration
*/
typedef struct {
uint32_t u32PwmState; /*!< Enable or disable EMB detect TMR4/6 PWM channel same phase function
This parameter can be a value of EMB_TMR4_PWM_Selection or EMB_TMR6_PWM_Selection */
uint32_t u32PwmLevel; /*!< Detect TMR4/6 PWM channel polarity level
This parameter can be a value of EMB_Detect_TMR4_PWM_Level or EMB_Detect_TMR6_PWM_Level */
} stc_emb_monitor_tmr_pwm_t;
/**
* @brief EMB monitor port in configuration
*/
typedef struct {
stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function
This parameter details refer @ref stc_emb_monitor_port_config_t structure */
stc_emb_monitor_port_config_t stcPort2; /*!< EMB detect EMB port in function
This parameter details refer @ref stc_emb_monitor_port_config_t structure */
stc_emb_monitor_port_config_t stcPort3; /*!< EMB detect EMB port in function
This parameter details refer @ref stc_emb_monitor_port_config_t structure */
stc_emb_monitor_port_config_t stcPort4; /*!< EMB detect EMB port in function
This parameter details refer @ref stc_emb_monitor_port_config_t structure */
} stc_emb_monitor_port_t;
/**
* @brief EMB monitor CMP configuration
*/
typedef struct {
uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function
This parameter can be a value of @ref EMB_CMP_Selection */
uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function
This parameter can be a value of @ref EMB_CMP_Selection */
uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function
This parameter can be a value of @ref EMB_CMP_Selection */
uint32_t u32Cmp4State; /*!< Enable or disable EMB detect CMP4 result function
This parameter can be a value of @ref EMB_CMP_Selection */
} stc_emb_monitor_cmp_t;
/**
* @brief EMB monitor TMR4 configuration
*/
typedef struct {
stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
} stc_emb_monitor_tmr4_t;
/**
* @brief EMB monitor TMR6 configuration
*/
typedef struct {
stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_4; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_5; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_6; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_7; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_8; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
} stc_emb_monitor_tmr6_t;
/**
* @brief EMB control TMR4 initialization configuration
*/
typedef struct {
stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
This parameter details refer @ref stc_emb_monitor_cmp_t structure */
stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function
This parameter details refer @ref stc_emb_monitor_osc_t structure */
stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr4_t structure */
} stc_emb_tmr4_init_t;
/**
* @brief EMB control TMR6 initialization configuration
*/
typedef struct {
stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
This parameter details refer @ref stc_emb_monitor_cmp_t structure */
stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function
This parameter details refer @ref stc_emb_monitor_osc_t structure */
stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr6_t structure */
} stc_emb_tmr6_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EMB_Global_Macros EMB Global Macros
* @{
*/
/**
* @defgroup EMB_CMP_Selection EMB CMP Selection
* @{
*/
#define EMB_CMP1_DISABLE (0UL)
#define EMB_CMP2_DISABLE (0UL)
#define EMB_CMP3_DISABLE (0UL)
#define EMB_CMP4_DISABLE (0UL)
#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN0)
#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN1)
#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN2)
#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN3)
/**
* @}
*/
/**
* @defgroup EMB_OSC_Selection EMB OSC Selection
* @{
*/
#define EMB_OSC_DISABLE (0UL)
#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN)
/**
* @}
*/
/**
* @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection
* @{
*/
#define EMB_TMR4_PWM_W_DISABLE (0UL)
#define EMB_TMR4_PWM_V_DISABLE (0UL)
#define EMB_TMR4_PWM_U_DISABLE (0UL)
#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN0)
#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN1)
#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN2)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level
* @{
*/
#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV0)
#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV1)
#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV2)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection
* @{
*/
#define EMB_TMR6_1_PWM_DISABLE (0UL)
#define EMB_TMR6_2_PWM_DISABLE (0UL)
#define EMB_TMR6_3_PWM_DISABLE (0UL)
#define EMB_TMR6_4_PWM_DISABLE (0UL)
#define EMB_TMR6_5_PWM_DISABLE (0UL)
#define EMB_TMR6_6_PWM_DISABLE (0UL)
#define EMB_TMR6_7_PWM_DISABLE (0UL)
#define EMB_TMR6_8_PWM_DISABLE (0UL)
#define EMB_TMR6_9_PWM_DISABLE (0UL)
#define EMB_TMR6_10_PWM_DISABLE (0UL)
#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN0)
#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN1)
#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL1_PWMSEN2)
#define EMB_TMR6_4_PWM_ENABLE (EMB_CTL1_PWMSEN3)
#define EMB_TMR6_5_PWM_ENABLE (EMB_CTL1_PWMSEN4)
#define EMB_TMR6_6_PWM_ENABLE (EMB_CTL1_PWMSEN5)
#define EMB_TMR6_7_PWM_ENABLE (EMB_CTL1_PWMSEN6)
#define EMB_TMR6_8_PWM_ENABLE (EMB_CTL1_PWMSEN7)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_PWM_Level EMB TMR6 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_9_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_10_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV0)
#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV1)
#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_CTL2_PWMLV2)
#define EMB_DETECT_TMR6_4_PWM_BOTH_HIGH (EMB_CTL2_PWMLV3)
#define EMB_DETECT_TMR6_5_PWM_BOTH_HIGH (EMB_CTL2_PWMLV4)
#define EMB_DETECT_TMR6_6_PWM_BOTH_HIGH (EMB_CTL2_PWMLV5)
#define EMB_DETECT_TMR6_7_PWM_BOTH_HIGH (EMB_CTL2_PWMLV6)
#define EMB_DETECT_TMR6_8_PWM_BOTH_HIGH (EMB_CTL2_PWMLV7)
#define EMB_DETECT_TMR6_9_PWM_BOTH_HIGH (EMB_CTL2_PWMLV8)
#define EMB_DETECT_TMR6_10_PWM_BOTH_HIGH (EMB_CTL2_PWMLV9)
/**
* @}
*/
/**
* @defgroup EMB_Port_Selection EMB Port Selection
* @{
*/
#define EMB_PORT1_DISABLE (0UL)
#define EMB_PORT2_DISABLE (0UL)
#define EMB_PORT3_DISABLE (0UL)
#define EMB_PORT4_DISABLE (0UL)
#define EMB_PORT5_DISABLE (0UL)
#define EMB_PORT6_DISABLE (0UL)
#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1)
#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2)
#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3)
#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN4)
/**
* @}
*/
/**
* @defgroup EMB_Detect_Port_Level EMB Detect Port Level
* @{
*/
#define EMB_PORT1_DETECT_LVL_HIGH (0UL)
#define EMB_PORT2_DETECT_LVL_HIGH (0UL)
#define EMB_PORT3_DETECT_LVL_HIGH (0UL)
#define EMB_PORT4_DETECT_LVL_HIGH (0UL)
#define EMB_PORT5_DETECT_LVL_HIGH (0UL)
#define EMB_PORT6_DETECT_LVL_HIGH (0UL)
#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL1_INVSEL1)
#define EMB_PORT2_DETECT_LVL_LOW (EMB_CTL1_INVSEL2)
#define EMB_PORT3_DETECT_LVL_LOW (EMB_CTL1_INVSEL3)
#define EMB_PORT4_DETECT_LVL_LOW (EMB_CTL1_INVSEL4)
/**
* @}
*/
/**
* @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection
* @{
*/
#define EMB_PORT1_FILTER_DISABLE (0UL)
#define EMB_PORT2_FILTER_DISABLE (0UL)
#define EMB_PORT3_FILTER_DISABLE (0UL)
#define EMB_PORT4_FILTER_DISABLE (0UL)
#define EMB_PORT5_FILTER_DISABLE (0UL)
#define EMB_PORT6_FILTER_DISABLE (0UL)
#define EMB_PORT1_FILTER_ENABLE (EMB_CTL2_NFEN1)
#define EMB_PORT2_FILTER_ENABLE (EMB_CTL2_NFEN2)
#define EMB_PORT3_FILTER_ENABLE (EMB_CTL2_NFEN3)
#define EMB_PORT4_FILTER_ENABLE (EMB_CTL2_NFEN4)
/**
* @}
*/
/**
* @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division
* @{
*/
#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL1_POS)
#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL1_POS)
#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL1_POS)
#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL1_POS)
#define EMB_PORT2_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL2_POS)
#define EMB_PORT2_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL2_POS)
#define EMB_PORT2_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL2_POS)
#define EMB_PORT2_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL2_POS)
#define EMB_PORT3_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL3_POS)
#define EMB_PORT3_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL3_POS)
#define EMB_PORT3_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL3_POS)
#define EMB_PORT3_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL3_POS)
#define EMB_PORT4_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL4_POS)
#define EMB_PORT4_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL4_POS)
#define EMB_PORT4_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL4_POS)
#define EMB_PORT4_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL4_POS)
/**
* @}
*/
/**
* @defgroup EMB_Flag_State EMB Flag State
* @{
*/
#define EMB_FLAG_PWMS (EMB_STAT_PWMSF)
#define EMB_FLAG_CMP (EMB_STAT_CMPF)
#define EMB_FLAG_OSC (EMB_STAT_OSF)
#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1)
#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2)
#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3)
#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4)
#define EMB_STAT_PWMS (EMB_STAT_PWMST)
#define EMB_STAT_CMP (EMB_STAT_CMPST)
#define EMB_STAT_OSC (EMB_STAT_OSST)
#define EMB_STAT_PORT1 (EMB_STAT_PORTINST1)
#define EMB_STAT_PORT2 (EMB_STAT_PORTINST2)
#define EMB_STAT_PORT3 (EMB_STAT_PORTINST3)
#define EMB_STAT_PORT4 (EMB_STAT_PORTINST4)
#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_OSC | EMB_FLAG_PORT1 | \
EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4 | EMB_STAT_PWMS | \
EMB_STAT_CMP | EMB_STAT_OSC | EMB_STAT_PORT1 | EMB_STAT_PORT2 | \
EMB_STAT_PORT3 | EMB_STAT_PORT4)
/**
* @}
*/
/**
* @defgroup EMB_Interrupt EMB Interrupt
* @{
*/
#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN)
#define EMB_INT_CMP (EMB_INTEN_CMPINTEN)
#define EMB_INT_OSC (EMB_INTEN_OSINTEN)
#define EMB_INT_PORT1 (EMB_INTEN_PORTINTEN1)
#define EMB_INT_PORT2 (EMB_INTEN_PORTINTEN2)
#define EMB_INT_PORT3 (EMB_INTEN_PORTINTEN3)
#define EMB_INT_PORT4 (EMB_INTEN_PORTINTEN4)
#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_OSC | \
EMB_INT_PORT1 | EMB_INT_PORT2 | EMB_INT_PORT3 | EMB_INT_PORT4)
/**
* @}
*/
/**
* @defgroup EMB_Release_TMR_PWM_Condition EMB Release TMR PWM Condition
* @{
*/
#define EMB_RELEASE_PWM_COND_FLAG_ZERO (0UL)
#define EMB_RELEASE_PWM_COND_STAT_ZERO (1UL)
/**
* @}
*/
/**
* @defgroup EMB_Monitor_Event EMB Monitor Event
* @{
*/
#define EMB_EVT_PWMS (EMB_RLSSEL_PWMRSEL)
#define EMB_EVT_CMP (EMB_RLSSEL_CMPRSEL)
#define EMB_EVT_OSC (EMB_RLSSEL_OSRSEL)
#define EMB_EVT_PORT1 (EMB_RLSSEL_PORTINRSEL1)
#define EMB_EVT_PORT2 (EMB_RLSSEL_PORTINRSEL2)
#define EMB_EVT_PORT3 (EMB_RLSSEL_PORTINRSEL3)
#define EMB_EVT_PORT4 (EMB_RLSSEL_PORTINRSEL4)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EMB_Global_Functions
* @{
*/
int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit);
int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit);
int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit);
int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit);
void EMB_DeInit(CM_EMB_TypeDef *EMBx);
void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState);
void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState);
void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond);
/**
* @}
*/
#endif /* LL_EMB_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_EMB_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_event_port.h
* @brief This file contains all the functions prototypes of the Event Port
* driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_EVENT_PORT_H__
#define __HC32_LL_EVENT_PORT_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EVENT_PORT
* @{
*/
#if (LL_EVENT_PORT_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EP_Global_Types Event Port Global Types
* @{
*/
/**
* @brief Event Pin Set and Reset enumeration
*/
typedef enum {
EVT_PIN_RESET = 0U, /*!< Pin reset */
EVT_PIN_SET = 1U /*!< Pin set */
} en_ep_state_t;
typedef struct {
uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */
en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */
uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */
uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */
uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */
uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */
} stc_ep_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EP_Global_Macros Event Port Global Macros
* @{
*/
/**
* @defgroup EP_Port_source EP Port Source
* @{
*/
#define EVT_PORT_1 (0U) /*!< Event port 1 */
#define EVT_PORT_2 (1U) /*!< Event port 2 */
#define EVT_PORT_3 (2U) /*!< Event port 3 */
#define EVT_PORT_4 (3U) /*!< Event port 4 */
/**
* @}
*/
/**
* @defgroup EP_pins_define EP Pin Source
* @{
*/
#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */
#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */
#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */
#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */
#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */
#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */
#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */
#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */
#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */
#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */
#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */
#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */
#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */
#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */
#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */
#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */
#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */
#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */
/**
* @}
*/
/**
* @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection
* @{
*/
#define EP_DIR_IN (0UL) /*!< EP input */
#define EP_DIR_OUT (1UL) /*!< EP output */
/**
* @}
*/
/**
* @defgroup EP_FilterClock_Sel Event Port Filter Function Selection
* @{
*/
#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */
#define EP_FILTER_ON (1UL) /*!< EP filter function ON */
/**
* @}
*/
/**
* @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection
* @{
*/
#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */
#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */
#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */
#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */
/**
* @}
*/
/**
* @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection
* @{
*/
#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */
#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */
#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */
#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */
/**
* @}
*/
/**
* @defgroup EP_TriggerOps_Sel Event Port Operation
* @{
*/
#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */
#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */
#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */
#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EP_Global_Functions
* @{
*/
void EP_DeInit(void);
int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit);
int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit);
int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge);
int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops);
en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin);
uint16_t EP_ReadInputPort(uint8_t u8EventPort);
en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin);
uint16_t EP_ReadOutputPort(uint8_t u8EventPort);
void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin);
void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin);
void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir);
/**
* @}
*/
#endif /* LL_EVENT_PORT_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_EVENT_PORT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_fcg.h
* @brief This file contains all the functions prototypes of the FCG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_FCG_H__
#define __HC32_LL_FCG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_FCG
* @{
*/
#if (LL_FCG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup FCG_Global_Macros FCG Global Macros
* @{
*/
/**
* @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral
* @{
*/
#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH)
#define FCG0_PERIPH_SRAM1 (PWC_FCG0_SRAM1)
#define FCG0_PERIPH_SRAM2 (PWC_FCG0_SRAM2)
#define FCG0_PERIPH_SRAM3 (PWC_FCG0_SRAM3)
#define FCG0_PERIPH_SRAM4 (PWC_FCG0_SRAM4)
#define FCG0_PERIPH_SRAMB (PWC_FCG0_SRAMB)
#define FCG0_PERIPH_KEY (PWC_FCG0_KEY)
#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1)
#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2)
#define FCG0_PERIPH_FCM (PWC_FCG0_FCM)
#define FCG0_PERIPH_AOS (PWC_FCG0_AOS)
#define FCG0_PERIPH_CTC (PWC_FCG0_CTC)
#define FCG0_PERIPH_MAU (PWC_FCG0_MAU)
#define FCG0_PERIPH_AES (PWC_FCG0_AES)
#define FCG0_PERIPH_HASH (PWC_FCG0_HASH)
#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG)
#define FCG0_PERIPH_CRC (PWC_FCG0_CRC)
#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1)
#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2)
#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3)
#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4)
#define FCG0_PERIPH_DCU5 (PWC_FCG0_DCU5)
#define FCG0_PERIPH_DCU6 (PWC_FCG0_DCU6)
#define FCG0_PERIPH_DCU7 (PWC_FCG0_DCU7)
#define FCG0_PERIPH_DCU8 (PWC_FCG0_DCU8)
/**
* @}
*/
/**
* @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral
* @{
*/
#define FCG1_PERIPH_CAN1 (PWC_FCG1_CAN1)
#define FCG1_PERIPH_CAN2 (PWC_FCG1_CAN2)
#define FCG1_PERIPH_ETHMAC (PWC_FCG1_ETHMAC)
#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI)
#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1)
#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2)
#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3)
#define FCG1_PERIPH_I2C4 (PWC_FCG1_I2C4)
#define FCG1_PERIPH_I2C5 (PWC_FCG1_I2C5)
#define FCG1_PERIPH_I2C6 (PWC_FCG1_I2C6)
#define FCG1_PERIPH_SDIOC1 (PWC_FCG1_SDIOC1)
#define FCG1_PERIPH_SDIOC2 (PWC_FCG1_SDIOC2)
#define FCG1_PERIPH_I2S1 (PWC_FCG1_I2S1)
#define FCG1_PERIPH_I2S2 (PWC_FCG1_I2S2)
#define FCG1_PERIPH_I2S3 (PWC_FCG1_I2S3)
#define FCG1_PERIPH_I2S4 (PWC_FCG1_I2S4)
#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1)
#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2)
#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3)
#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4)
#define FCG1_PERIPH_SPI5 (PWC_FCG1_SPI5)
#define FCG1_PERIPH_SPI6 (PWC_FCG1_SPI6)
#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS)
#define FCG1_PERIPH_USBHS (PWC_FCG1_USBHS)
#define FCG1_PERIPH_FMAC1 (PWC_FCG1_FMAC1)
#define FCG1_PERIPH_FMAC2 (PWC_FCG1_FMAC2)
#define FCG1_PERIPH_FMAC3 (PWC_FCG1_FMAC3)
#define FCG1_PERIPH_FMAC4 (PWC_FCG1_FMAC4)
/**
* @}
*/
/**
* @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral
* @{
*/
#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TMR6_1)
#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TMR6_2)
#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TMR6_3)
#define FCG2_PERIPH_TMR6_4 (PWC_FCG2_TMR6_4)
#define FCG2_PERIPH_TMR6_5 (PWC_FCG2_TMR6_5)
#define FCG2_PERIPH_TMR6_6 (PWC_FCG2_TMR6_6)
#define FCG2_PERIPH_TMR6_7 (PWC_FCG2_TMR6_7)
#define FCG2_PERIPH_TMR6_8 (PWC_FCG2_TMR6_8)
#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TMR4_1)
#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TMR4_2)
#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TMR4_3)
#define FCG2_PERIPH_HRPWM (PWC_FCG2_HRPWM)
#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TMR0_1)
#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TMR0_2)
#define FCG2_PERIPH_EMB (PWC_FCG2_EMB)
#define FCG2_PERIPH_TMR2_1 (PWC_FCG2_TMR2_1)
#define FCG2_PERIPH_TMR2_2 (PWC_FCG2_TMR2_2)
#define FCG2_PERIPH_TMR2_3 (PWC_FCG2_TMR2_3)
#define FCG2_PERIPH_TMR2_4 (PWC_FCG2_TMR2_4)
#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TMRA_1)
#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TMRA_2)
#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TMRA_3)
#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TMRA_4)
#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TMRA_5)
#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TMRA_6)
#define FCG2_PERIPH_TMRA_7 (PWC_FCG2_TMRA_7)
#define FCG2_PERIPH_TMRA_8 (PWC_FCG2_TMRA_8)
#define FCG2_PERIPH_TMRA_9 (PWC_FCG2_TMRA_9)
#define FCG2_PERIPH_TMRA_10 (PWC_FCG2_TMRA_10)
#define FCG2_PERIPH_TMRA_11 (PWC_FCG2_TMRA_11)
#define FCG2_PERIPH_TMRA_12 (PWC_FCG2_TMRA_12)
/**
* @}
*/
/**
* @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral
* @{
*/
#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1)
#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2)
#define FCG3_PERIPH_ADC3 (PWC_FCG3_ADC3)
#define FCG3_PERIPH_CMBIAS (PWC_FCG3_CMBIAS)
#define FCG3_PERIPH_DAC1 (PWC_FCG3_DAC1)
#define FCG3_PERIPH_DAC2 (PWC_FCG3_DAC2)
#define FCG3_PERIPH_CMP1_2 (PWC_FCG3_CMP1)
#define FCG3_PERIPH_CMP3_4 (PWC_FCG3_CMP2)
#define FCG3_PERIPH_OTS (PWC_FCG3_OTS)
#define FCG3_PERIPH_DVP (PWC_FCG3_DVP)
#define FCG3_PERIPH_SMC (PWC_FCG3_SMC)
#define FCG3_PERIPH_DMC (PWC_FCG3_DMC)
#define FCG3_PERIPH_NFC (PWC_FCG3_NFC)
#define FCG3_PERIPH_USART1 (PWC_FCG3_USART1)
#define FCG3_PERIPH_USART2 (PWC_FCG3_USART2)
#define FCG3_PERIPH_USART3 (PWC_FCG3_USART3)
#define FCG3_PERIPH_USART4 (PWC_FCG3_USART4)
#define FCG3_PERIPH_USART5 (PWC_FCG3_USART5)
#define FCG3_PERIPH_USART6 (PWC_FCG3_USART6)
#define FCG3_PERIPH_USART7 (PWC_FCG3_USART7)
#define FCG3_PERIPH_USART8 (PWC_FCG3_USART8)
#define FCG3_PERIPH_USART9 (PWC_FCG3_USART9)
#define FCG3_PERIPH_USART10 (PWC_FCG3_USART10)
/**
* @}
*/
/**
* @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask
* @{
*/
#define FCG_FCG0_PERIPH_MASK (0xFFFFE4F1UL)
#define FCG_FCG1_PERIPH_MASK (0x0FFFFFFFUL)
#define FCG_FCG2_PERIPH_MASK (0xFFFFBFFFUL)
#define FCG_FCG3_PERIPH_MASK (0x3FF7933FUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup FCG_Global_Functions
* @{
*/
void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_FCG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_FCG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_fcm.h
* @brief This file contains all the functions prototypes of the FCM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_FCM_H__
#define __HC32_LL_FCM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_FCM
* @{
*/
#if (LL_FCM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup FCM_Global_Types FCM Global Types
* @{
*/
/**
* @brief FCM Init structure definition
*/
typedef struct {
uint16_t u16LowerLimit; /*!< FCM lower limit value */
uint16_t u16UpperLimit; /*!< FCM upper limit value */
uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */
uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */
uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */
uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */
uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */
uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */
uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */
uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */
} stc_fcm_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup FCM_Global_Macros FCM Global Macros
* @{
*/
/**
* @defgroup FCM_Target_Clock_Src FCM Target Clock Source
* @{
*/
#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_PLLAP (0x06UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS)
#define FCM_TARGET_CLK_RTCLRC (0x09UL << FCM_MCCR_MCKS_POS)
/**
* @}
*/
/**
* @defgroup FCM_Target_Clock_Div FCM Target Clock Division
* @{
*/
#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS)
#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS)
#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS)
#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS)
/**
* @}
*/
/**
* @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config
* @{
*/
#define FCM_EXT_REF_OFF (0x00UL)
#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE)
/**
* @}
*/
/**
* @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge
* @{
*/
#define FCM_REF_CLK_RISING (0x00UL)
#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
/**
* @}
*/
/**
* @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config
* @{
*/
#define FCM_DIG_FILTER_OFF (0x00UL)
#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0)
#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1)
#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS)
/**
* @}
*/
/**
* @defgroup FCM_Ref_Clock_Src FCM Feference Clock Source
* @{
*/
#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PLLAP (0x16UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_RTCLRC (0x19UL << FCM_RCCR_RCKS_POS)
/**
* @}
*/
/**
* @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division
* @{
*/
#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS)
#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS)
#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS)
#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS)
/**
* @}
*/
/**
* @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config
* @{
*/
#define FCM_ERR_RST_OFF (0x00UL)
#define FCM_ERR_RST_ON (FCM_RIER_ERRE)
/**
* @}
*/
/**
* @defgroup FCM_Exception_Type FCM Exception Type
* @{
*/
#define FCM_EXP_TYPE_INT (0x00UL)
#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS)
/**
* @}
*/
/**
* @defgroup FCM_Int_Type FCM Interrupt Type
* @{
*/
#define FCM_INT_OVF (FCM_RIER_OVFIE)
#define FCM_INT_END (FCM_RIER_MENDIE)
#define FCM_INT_ERR (FCM_RIER_ERRIE)
/**
* @}
*/
/**
* @defgroup FCM_Flag_Sel FCM Status Flag Selection
* @{
*/
#define FCM_FLAG_ERR (FCM_SR_ERRF)
#define FCM_FLAG_END (FCM_SR_MENDF)
#define FCM_FLAG_OVF (FCM_SR_OVF)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup FCM_Global_Functions
* @{
*/
/**
* @brief Set FCM upper limit value.
* @param u16Limit
* @retval None.
*/
__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit)
{
WRITE_REG32(CM_FCM->UVR, u16Limit);
}
/**
* @brief Set FCM lower limit value.
* @param u16Limit
* @retval None
*/
__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit)
{
WRITE_REG32(CM_FCM->LVR, u16Limit);
}
int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
void FCM_DeInit(void);
uint16_t FCM_GetCountValue(void);
void FCM_SetUpperLimit(uint16_t u16Limit);
void FCM_SetLowerLimit(uint16_t u16Limit);
void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div);
void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div);
en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
void FCM_ClearStatus(uint32_t u32Flag);
void FCM_ResetCmd(en_functional_state_t enNewState);
void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
void FCM_Cmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_FCM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_FCM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_fmac.h
* @brief This file contains all the functions prototypes of the FMAC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_FMAC_H__
#define __HC32_LL_FMAC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_FMAC
* @{
*/
#if (LL_FMAC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup FMAC_Global_Types FMAC Global Types
* @{
*/
/**
* @brief FMAC configuration structure
*/
typedef struct {
uint32_t u32Stage; /*!< FMAC filter stage number config.
This parameter can be a value of @ref FMAC_Filter_Stage.*/
uint32_t u32Shift; /*!< FMAC filter result right shift bits.
This parameter can be a value of @ref FMAC_Filter_Shift.*/
int16_t *pi16Factor; /*!< FMAC filter factor config. FIR factor array */
uint32_t u32IntCmd; /*!< Enable or disable FMAC interrupt.
This parameter can be a value of @ref FMAC_Interrupt_Selection.*/
} stc_fmac_init_t;
/**
* @brief FMAC result definition
*/
typedef struct {
uint32_t u32ResultHigh; /*!< The high value of the result. */
uint32_t u32ResultLow; /*!< The low value of the result. */
} stc_fmac_result_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup FMAC_Global_Macros FMAC Global Macros
* @{
*/
/**
* @defgroup FMAC_Interrupt_Selection FMAC Interrupt Selection
* @{
*/
#define FMAC_INT_ENABLE (FMAC_IER_INTEN)
#define FMAC_INT_DISABLE (0x0UL)
/**
* @}
*/
/**
* @defgroup FMAC_Filter_Shift FMAC Filter Shift
* @{
*/
#define FMAC_FIR_SHIFT_0BIT (0U)
#define FMAC_FIR_SHIFT_1BIT (1U)
#define FMAC_FIR_SHIFT_2BIT (2U)
#define FMAC_FIR_SHIFT_3BIT (3U)
#define FMAC_FIR_SHIFT_4BIT (4U)
#define FMAC_FIR_SHIFT_5BIT (5U)
#define FMAC_FIR_SHIFT_6BIT (6U)
#define FMAC_FIR_SHIFT_7BIT (7U)
#define FMAC_FIR_SHIFT_8BIT (8U)
#define FMAC_FIR_SHIFT_9BIT (9U)
#define FMAC_FIR_SHIFT_10BIT (10U)
#define FMAC_FIR_SHIFT_11BIT (11U)
#define FMAC_FIR_SHIFT_12BIT (12U)
#define FMAC_FIR_SHIFT_13BIT (13U)
#define FMAC_FIR_SHIFT_14BIT (14U)
#define FMAC_FIR_SHIFT_15BIT (15U)
#define FMAC_FIR_SHIFT_16BIT (16U)
#define FMAC_FIR_SHIFT_17BIT (17U)
#define FMAC_FIR_SHIFT_18BIT (18U)
#define FMAC_FIR_SHIFT_19BIT (19U)
#define FMAC_FIR_SHIFT_20BIT (20U)
#define FMAC_FIR_SHIFT_21BIT (21U)
/**
* @}
*/
/**
* @defgroup FMAC_Filter_Stage FMAC Filter Stage
* @{
*/
#define FMAC_FIR_STAGE_0 (0U)
#define FMAC_FIR_STAGE_1 (1U)
#define FMAC_FIR_STAGE_2 (2U)
#define FMAC_FIR_STAGE_3 (3U)
#define FMAC_FIR_STAGE_4 (4U)
#define FMAC_FIR_STAGE_5 (5U)
#define FMAC_FIR_STAGE_6 (6U)
#define FMAC_FIR_STAGE_7 (7U)
#define FMAC_FIR_STAGE_8 (8U)
#define FMAC_FIR_STAGE_9 (9U)
#define FMAC_FIR_STAGE_10 (10U)
#define FMAC_FIR_STAGE_11 (11U)
#define FMAC_FIR_STAGE_12 (12U)
#define FMAC_FIR_STAGE_13 (13U)
#define FMAC_FIR_STAGE_14 (14U)
#define FMAC_FIR_STAGE_15 (15U)
#define FMAC_FIR_STAGE_16 (16U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup FMAC_Global_Functions
* @{
*/
int32_t FMAC_StructInit(stc_fmac_init_t *pstcFmacInit);
void FMAC_DeInit(CM_FMAC_TypeDef *FMACx);
int32_t FMAC_Init(CM_FMAC_TypeDef *FMACx, const stc_fmac_init_t *pstcFmacInit);
void FMAC_Cmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState);
void FMAC_SetResultShift(CM_FMAC_TypeDef *FMACx, uint32_t u32ShiftNum);
void FMAC_SetStageFactor(CM_FMAC_TypeDef *FMACx, uint32_t u32FilterStage, int16_t *pi16Factor);
void FMAC_IntCmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState);
void FMAC_FIRInput(CM_FMAC_TypeDef *FMACx, int16_t i16Factor);
en_flag_status_t FMAC_GetStatus(const CM_FMAC_TypeDef *FMACx);
int32_t FMAC_GetResult(const CM_FMAC_TypeDef *FMACx, stc_fmac_result_t *pstcResult);
/**
* @}
*/
#endif /* LL_FMAC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_FMAC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_gpio.h
* @brief This file contains all the functions prototypes of the GPIO driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_GPIO_H__
#define __HC32_LL_GPIO_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_GPIO
* @{
*/
#if (LL_GPIO_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup GPIO_Global_Types GPIO Global Types
* @{
*/
/**
* @brief GPIO Pin Set and Reset enumeration
*/
typedef enum {
PIN_RESET = 0U, /*!< Pin reset */
PIN_SET = 1U /*!< Pin set */
} en_pin_state_t;
/**
* @brief GPIO Init structure definition
*/
typedef struct {
uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */
uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */
uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */
uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */
uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */
uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */
uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel */
uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */
uint16_t u16PinInputType; /*!< Input type setting, @ref GPIO_PinInType_Sel */
uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */
} stc_gpio_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup GPIO_Global_Macros GPIO Global Macros
* @{
*/
/**
* @defgroup GPIO_Pins_Define GPIO Pin Source
* @{
*/
#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */
#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */
#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */
#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */
#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */
#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */
#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */
#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */
#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */
#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */
#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */
#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */
#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */
#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */
#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */
#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */
#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */
/**
* @}
*/
/**
* @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product
* @{
*/
#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/
#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/
#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/
#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/
#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/
#define GPIO_PIN_F_ALL (0xFFFFU) /*!< Pin F all*/
#define GPIO_PIN_G_ALL (0xFFFFU) /*!< Pin G all*/
#define GPIO_PIN_H_ALL (0xFFFFU) /*!< Pin H all*/
#define GPIO_PIN_I_ALL (0x3FFFU) /*!< Pin I all*/
/**
* @}
*/
/**
* @defgroup GPIO_Port_Source GPIO Port Source
* @{
*/
#define GPIO_PORT_A (0x00U) /*!< Port A selected */
#define GPIO_PORT_B (0x01U) /*!< Port B selected */
#define GPIO_PORT_C (0x02U) /*!< Port C selected */
#define GPIO_PORT_D (0x03U) /*!< Port D selected */
#define GPIO_PORT_E (0x04U) /*!< Port E selected */
#define GPIO_PORT_F (0x05U) /*!< Port F selected */
#define GPIO_PORT_G (0x06U) /*!< Port G selected */
#define GPIO_PORT_H (0x07U) /*!< Port H selected */
#define GPIO_PORT_I (0x08U) /*!< Port I selected */
/**
* @}
*/
/**
* @defgroup GPIO_Function_Sel GPIO Function Selection
* @{
*/
#define GPIO_FUNC_0 (0U)
#define GPIO_FUNC_1 (1U)
#define GPIO_FUNC_2 (2U)
#define GPIO_FUNC_3 (3U)
#define GPIO_FUNC_4 (4U)
#define GPIO_FUNC_5 (5U)
#define GPIO_FUNC_6 (6U)
#define GPIO_FUNC_7 (7U)
#define GPIO_FUNC_8 (8U)
#define GPIO_FUNC_9 (9U)
#define GPIO_FUNC_10 (10U)
#define GPIO_FUNC_11 (11U)
#define GPIO_FUNC_12 (12U)
#define GPIO_FUNC_13 (13U)
#define GPIO_FUNC_14 (14U)
#define GPIO_FUNC_15 (15U)
#define GPIO_FUNC_16 (16U)
#define GPIO_FUNC_17 (17U)
#define GPIO_FUNC_18 (18U)
#define GPIO_FUNC_19 (19U)
#define GPIO_FUNC_20 (20U)
#define GPIO_FUNC_32 (32U)
#define GPIO_FUNC_33 (33U)
#define GPIO_FUNC_34 (34U)
#define GPIO_FUNC_35 (35U)
#define GPIO_FUNC_36 (36U)
#define GPIO_FUNC_37 (37U)
#define GPIO_FUNC_38 (38U)
#define GPIO_FUNC_39 (39U)
#define GPIO_FUNC_40 (40U)
#define GPIO_FUNC_41 (41U)
#define GPIO_FUNC_42 (42U)
#define GPIO_FUNC_43 (43U)
#define GPIO_FUNC_44 (44U)
#define GPIO_FUNC_45 (45U)
#define GPIO_FUNC_46 (46U)
#define GPIO_FUNC_47 (47U)
#define GPIO_FUNC_48 (48U)
#define GPIO_FUNC_49 (49U)
#define GPIO_FUNC_50 (50U)
#define GPIO_FUNC_51 (51U)
#define GPIO_FUNC_52 (52U)
#define GPIO_FUNC_53 (53U)
#define GPIO_FUNC_54 (54U)
#define GPIO_FUNC_55 (55U)
#define GPIO_FUNC_56 (56U)
#define GPIO_FUNC_57 (57U)
#define GPIO_FUNC_58 (58U)
#define GPIO_FUNC_59 (59U)
#define GPIO_FUNC_60 (60U)
#define GPIO_FUNC_61 (61U)
#define GPIO_FUNC_62 (62U)
#define GPIO_FUNC_63 (63U)
/**
* @}
*/
/**
* @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection
* @{
*/
#define GPIO_PIN_TCK (0x01U)
#define GPIO_PIN_TMS (0x02U)
#define GPIO_PIN_TDO (0x04U)
#define GPIO_PIN_TDI (0x08U)
#define GPIO_PIN_TRST (0x10U)
#define GPIO_PIN_DEBUG_JTAG (0x1FU)
#define GPIO_PIN_SWCLK (0x01U)
#define GPIO_PIN_SWDIO (0x02U)
#define GPIO_PIN_SWO (0x04U)
#define GPIO_PIN_DEBUG_SWD (0x07U)
#define GPIO_PIN_DEBUG (0x1FU)
/**
* @}
*/
/**
* @defgroup GPIO_Hprwm_Pin_Sel GPIO Hrpwm Pin Selection
* @{
*/
/**
* @}
*/
/**
* @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection
* @{
*/
#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT4 (0x04U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT5 (0x05U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT6 (0x06U << GPIO_PCCR_RDWT_POS)
#define GPIO_RD_WAIT7 (0x07U << GPIO_PCCR_RDWT_POS)
/**
* @}
*/
/**
* @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection
* @{
*/
#define PIN_STAT_RST (0U)
#define PIN_STAT_SET (GPIO_PCR_POUT)
/**
* @}
*/
/**
* @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection
* @{
*/
#define PIN_DIR_IN (0U)
#define PIN_DIR_OUT (GPIO_PCR_POUTE)
/**
* @}
*/
/**
* @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection
* @{
*/
#define PIN_OUT_TYPE_CMOS (0U)
#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD)
/**
* @}
*/
/**
* @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection
* @{
*/
#define PIN_LOW_DRV (0U)
#define PIN_MID_DRV (GPIO_PCR_DRV_0)
#define PIN_HIGH_DRV (GPIO_PCR_DRV_1)
/**
* @}
*/
/**
* @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection
* @{
*/
#define PIN_LATCH_OFF (0U)
#define PIN_LATCH_ON (GPIO_PCR_LTE)
/**
* @}
*/
/**
* @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection
* @{
*/
#define PIN_PU_OFF (0U)
#define PIN_PU_ON (GPIO_PCR_PUU)
/**
* @}
*/
/**
* @defgroup GPIO_PinPD_Sel GPIO Pin Internal Pull-Down Resistor Selection
* @{
*/
#define PIN_PD_OFF (0U)
#define PIN_PD_ON (GPIO_PCR_PUD)
/**
* @}
*/
/**
* @defgroup GPIO_PinInputSw_Sel GPIO Pin Input Switch Resistor Selection
* @{
*/
#define PIN_IN_SW_OFF (0U)
#define PIN_IN_SW_ON (GPIO_PCR_PINAE)
/**
* @}
*/
/**
* @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection
* @{
*/
#define PIN_INVT_OFF (0U)
#define PIN_INVT_ON (GPIO_PCR_INVE)
/**
* @}
*/
/**
* @defgroup GPIO_PinInType_Sel GPIO Pin Input Type Selection
* @{
*/
#define PIN_IN_TYPE_SMT (0U)
#define PIN_IN_TYPE_CMOS (GPIO_PCR_CINSEL)
/**
* @}
*/
/**
* @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection
* @{
*/
#define PIN_EXTINT_OFF (0U)
#define PIN_EXTINT_ON (GPIO_PCR_INTE)
/**
* @}
*/
/**
* @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection
* @{
*/
#define PIN_ATTR_DIGITAL (0U)
#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS)
/**
* @}
*/
/**
* @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable
* @{
*/
#define PIN_SUBFUNC_DISABLE (0U)
#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE)
/**
* @}
*/
/**
* @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key
* @{
*/
#define GPIO_REG_LOCK_KEY (0xA500U)
#define GPIO_REG_UNLOCK_KEY (0xA501U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup GPIO_Global_Functions
* @{
*/
/**
* @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable
* @param None
* @retval None
*/
__STATIC_INLINE void GPIO_REG_Lock(void)
{
WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY);
}
/**
* @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable
* @param None
* @retval None
*/
__STATIC_INLINE void GPIO_REG_Unlock(void)
{
WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY);
}
int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit);
void GPIO_DeInit(void);
int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit);
void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState);
void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func);
void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
void GPIO_SetSubFunc(uint8_t u8Func);
void GPIO_SetReadWaitCycle(uint16_t u16ReadWait);
void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState);
void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin);
uint16_t GPIO_ReadInputPort(uint8_t u8Port);
en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin);
uint16_t GPIO_ReadOutputPort(uint8_t u8Port);
void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin);
void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin);
void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal);
void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin);
/**
* @}
*/
#endif /* LL_GPIO_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_GPIO_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_hash.h
* @brief This file contains all the functions prototypes of the HASH driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_HASH_H__
#define __HC32_LL_HASH_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_HASH
* @{
*/
#if (LL_HASH_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HASH_Global_Macros HASH Global Macros
* @{
*/
/**
* @defgroup HASH_Mode HASH Mode
* @{
*/
#define HASH_MD_SHA256 (0x0UL) /*!< SHA256 operating mode */
#define HASH_MD_HMAC (HASH_CR_MODE_0) /*!< HMAC operating mode */
/**
* @}
*/
/**
* @defgroup HASH_Key_Size_Mode HASH Key Size Mode
* @{
*/
#define HASH_KEY_MD_SHORT_SIZE (0x0UL) /*!< Key length <= 64 Bytes */
#define HASH_KEY_MD_LONG_SIZE (HASH_CR_LKEY) /*!< Key length > 64 Bytes */
/**
* @}
*/
/**
* @defgroup HASH_Interrupt HASH Interrupt
* @{
*/
#define HASH_INT_GRP (HASH_CR_HEIE) /*!< A set of data operations complete interrupt */
#define HASH_INT_ALL_CPLT (HASH_CR_HCIE) /*!< All data operations complete interrupt */
#define HASH_INT_ALL (HASH_INT_GRP | HASH_INT_ALL_CPLT)
/**
* @}
*/
/**
* @defgroup HASH_Msg_Group HASH Messages Group
* @{
*/
#define HASH_MSG_GRP_FIRST (HASH_CR_FST_GRP) /*!< The first group of messages or keys */
#define HASH_MSG_GRP_END (HASH_CR_KMSG_END) /*!< The last group of messages or keys */
#define HASH_MSG_GRP_ONLY_ONE (HASH_CR_FST_GRP | \
HASH_CR_KMSG_END) /*!< Only one set of message or key */
/**
* @}
*/
/**
* @defgroup HASH_Status_Flag HASH Status Flag
* @{
*/
#define HASH_FLAG_START (HASH_CR_START) /*!< Operation in progress */
#define HASH_FLAG_BUSY (HASH_CR_BUSY) /*!< HASH in operation */
#define HASH_FLAG_CYC_END (HASH_CR_CYC_END) /*!< key or message operation completed */
#define HASH_FLAG_HMAC_END (HASH_CR_HMAC_END) /*!< HMAC operation completed */
#define HASH_FLAG_ALL (HASH_FLAG_START | HASH_FLAG_BUSY | \
HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END)
#define HASH_FLAG_CLR_ALL (HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END)
/**
* @}
*/
/**
* @defgroup HASH_Trigger_Event HASH Trigger Event
* @{
*/
#define HASH_TRIG_EVT_DMA1_TC0 (EVT_SRC_DMA1_TC0) /*!< Select the DMA1 ch0 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC1 (EVT_SRC_DMA1_TC1) /*!< Select the DMA1 ch1 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC2 (EVT_SRC_DMA1_TC2) /*!< Select the DMA1 ch2 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC3 (EVT_SRC_DMA1_TC3) /*!< Select the DMA1 ch3 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC4 (EVT_SRC_DMA1_TC4) /*!< Select the DMA1 ch4 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC5 (EVT_SRC_DMA1_TC5) /*!< Select the DMA1 ch5 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC6 (EVT_SRC_DMA1_TC6) /*!< Select the DMA1 ch6 transfer complete*/
#define HASH_TRIG_EVT_DMA1_TC7 (EVT_SRC_DMA1_TC7) /*!< Select the DMA1 ch7 transfer complete*/
#define HASH_TRIG_EVT_DMA1_BTC0 (EVT_SRC_DMA1_BTC0) /*!< Select the DMA1 ch0 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC1 (EVT_SRC_DMA1_BTC1) /*!< Select the DMA1 ch1 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC2 (EVT_SRC_DMA1_BTC2) /*!< Select the DMA1 ch2 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC3 (EVT_SRC_DMA1_BTC3) /*!< Select the DMA1 ch3 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC4 (EVT_SRC_DMA1_BTC4) /*!< Select the DMA1 ch4 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC5 (EVT_SRC_DMA1_BTC5) /*!< Select the DMA1 ch5 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC6 (EVT_SRC_DMA1_BTC6) /*!< Select the DMA1 ch6 block transfer complete */
#define HASH_TRIG_EVT_DMA1_BTC7 (EVT_SRC_DMA1_BTC7) /*!< Select the DMA1 ch7 block transfer complete */
#define HASH_TRIG_EVT_DMA2_TC0 (EVT_SRC_DMA2_TC0) /*!< Select the DMA2 ch0 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC1 (EVT_SRC_DMA2_TC1) /*!< Select the DMA2 ch1 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC2 (EVT_SRC_DMA2_TC2) /*!< Select the DMA2 ch2 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC3 (EVT_SRC_DMA2_TC3) /*!< Select the DMA2 ch3 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC4 (EVT_SRC_DMA2_TC4) /*!< Select the DMA2 ch4 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC5 (EVT_SRC_DMA2_TC5) /*!< Select the DMA2 ch5 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC6 (EVT_SRC_DMA2_TC6) /*!< Select the DMA2 ch6 transfer complete*/
#define HASH_TRIG_EVT_DMA2_TC7 (EVT_SRC_DMA2_TC7) /*!< Select the DMA2 ch7 transfer complete*/
#define HASH_TRIG_EVT_DMA2_BTC0 (EVT_SRC_DMA2_BTC0) /*!< Select the DMA2 ch0 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC1 (EVT_SRC_DMA2_BTC1) /*!< Select the DMA2 ch1 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC2 (EVT_SRC_DMA2_BTC2) /*!< Select the DMA2 ch2 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC3 (EVT_SRC_DMA2_BTC3) /*!< Select the DMA2 ch3 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC4 (EVT_SRC_DMA2_BTC4) /*!< Select the DMA2 ch4 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC5 (EVT_SRC_DMA2_BTC5) /*!< Select the DMA2 ch5 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC6 (EVT_SRC_DMA2_BTC6) /*!< Select the DMA2 ch6 block transfer complete */
#define HASH_TRIG_EVT_DMA2_BTC7 (EVT_SRC_DMA2_BTC7) /*!< Select the DMA2 ch7 block transfer complete */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HASH_Global_Functions
* @{
*/
int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest);
int32_t HASH_HMAC_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize,
const uint8_t *pu8Key, uint32_t u32KeySize,
uint8_t *pu8MsgDigest);
int32_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState);
en_flag_status_t HASH_GetStatus(uint32_t u32Flag);
int32_t HASH_ClearStatus(uint32_t u32Flag);
int32_t HASH_SetMode(uint32_t u32HashMode);
int32_t HASH_SetKeySizeMode(uint32_t u32SizeMode);
int32_t HASH_SetMsgGroup(uint32_t u32MsgGroup);
int32_t HASH_Start(void);
void HASH_GetMsgDigest(uint8_t *pu8MsgDigest);
/**
* @}
*/
#endif /* LL_HASH_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_HASH_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_hrpwm.h
* @brief Head file for HRPWM module.
*
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_HRPWM_H__
#define __HC32_LL_HRPWM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_HRPWM
* @{
*/
#if (LL_HRPWM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HRPWM_Global_Macros HRPWM Global Macros
* @{
*/
#define HRPWM_CH_MIN (1UL)
#define HRPWM_CH_MAX (16UL)
#define HRPWM_CH_DELAY_NUM_MIN (1U)
#define HRPWM_CH_DELAY_NUM_MAX (256U)
/**
* @defgroup HRPWM_Calibrate_Unit_Define HRPWM Calibrate Unit Define
* @{
*/
#define HRPWM_CAL_UNIT0 (0x00UL)
#define HRPWM_CAL_UNIT1 (0x01UL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HRPWM_Global_Functions
* @{
*/
/* HRPWM Judge the condition of calibration function */
en_functional_state_t HRPWM_CondConfirm(void);
/* Process for getting HRPWM Calibrate function code */
int32_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t *pu8Code);
/* HRPWM Calibrate function enable or disable for specified unit */
void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState);
/* HRPWM Calibrate function status get for specified unit */
en_functional_state_t HRPWM_GetCalibrateState(uint32_t u32Unit);
/* HRPWM Calibrate code get for specified unit */
uint8_t HRPWM_GetCalibrateCode(uint32_t u32Unit);
/* HRPWM function enable or disable for specified channel */
void HRPWM_ChCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM positive edge adjust enable or disable for specified channel */
void HRPWM_ChPositiveAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM negative edge adjust enable or disable for specified channel */
void HRPWM_ChNegativeAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM positive edge adjust delay counts configration for specified channel */
void HRPWM_ChPositiveAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum);
/* HRPWM negative edge adjust delay counts configration for specified channel */
void HRPWM_ChNegativeAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum);
/**
* @}
*/
#endif /* LL_HRPWM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_HRPWM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_i2c.h
* @brief This file contains all the functions prototypes of the Inter-Integrated
* Circuit(I2C).
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_I2C_H__
#define __HC32_LL_I2C_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_I2C
* @{
*/
#if (LL_I2C_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2C_Global_Types I2C Global Types
* @{
*/
/**
* @brief I2c configuration structure
*/
typedef struct {
uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */
uint32_t u32Baudrate; /*!< I2C baudrate config */
uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */
} stc_i2c_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2C_Global_Macros I2C Global Macros
* @{
*/
/**
* @defgroup I2C_Trans_Dir I2C Transfer Direction
* @{
*/
#define I2C_DIR_TX (0x0U)
#define I2C_DIR_RX (0x1U)
/**
* @}
*/
/**
* @defgroup I2C_Addr_Config I2C Address Configurate
* @{
*/
#define I2C_ADDR_DISABLE (0U)
#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN)
#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN)
/**
* @}
*/
/**
* @defgroup I2C_Clock_Division I2C Clock Division
* @{
*/
#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */
#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */
#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */
#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */
#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */
#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */
#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */
#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */
/**
* @}
*/
/**
* @defgroup I2C_Address_Num I2C Address Number
* @{
*/
#define I2C_ADDR0 (0UL)
#define I2C_ADDR1 (1UL)
/**
* @}
*/
/**
* @defgroup I2C_Ack_Config I2C ACK Configurate
* @{
*/
#define I2C_ACK (0UL) /*!< Send ACK after date receive */
#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */
/**
* @}
*/
/**
* @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configurate
* @{
*/
#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN)
#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/**
* @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock
* @{
*/
#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */
#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */
#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */
#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */
/**
* @}
*/
/**
* @defgroup I2C_Flag I2C Flag
* @{
*/
#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */
#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */
#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */
#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */
#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */
#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */
#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */
#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */
#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */
#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */
#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */
#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */
#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */
#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */
#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */
#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */
#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */
#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */
#define I2C_FLAG_CLR_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 \
| I2C_FLAG_TX_CPLT | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY \
| I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF \
| I2C_FLAG_GENERAL_CALL | I2C_FLAG_SMBUS_DEFAULT_MATCH \
| I2C_FLAG_SMBUS_HOST_MATCH | I2C_FLAG_SMBUS_ALARM_MATCH)
#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_TX_CPLT \
| I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY | I2C_FLAG_ARBITRATE_FAIL\
| I2C_FLAG_ACKR | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF | I2C_FLAG_MASTER \
| I2C_FLAG_BUSY | I2C_FLAG_TRA | I2C_FLAG_GENERAL_CALL \
| I2C_FLAG_SMBUS_DEFAULT_MATCH | I2C_FLAG_SMBUS_HOST_MATCH \
| I2C_FLAG_SMBUS_ALARM_MATCH)
/**
* @}
*/
/**
* @defgroup I2C_Int_Flag I2C Interrupt Flag Bits
* @{
*/
#define I2C_INT_START (I2C_CR2_STARTIE)
#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE)
#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE)
#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE)
#define I2C_INT_STOP (I2C_CR2_STOPIE)
#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE)
#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE)
#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE)
#define I2C_INT_NACK (I2C_CR2_NACKIE)
#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE)
#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE)
#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE)
#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE)
#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE)
#define I2C_INT_ALL (I2C_INT_START | I2C_INT_MATCH_ADDR0 | I2C_INT_MATCH_ADDR1 | I2C_INT_TX_CPLT \
| I2C_INT_STOP | I2C_INT_RX_FULL | I2C_INT_TX_EMPTY | I2C_INT_ARBITRATE_FAIL \
| I2C_INT_NACK | I2C_INT_TMOUTIE | I2C_INT_GENERAL_CALL \
| I2C_INT_SMBUS_DEFAULT_MATCH | I2C_INT_SMBUS_HOST_MATCH \
| I2C_INT_SMBUS_ALARM_MATCH)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2C_Global_Functions
* @{
*/
/* Initialization and Configuration **********************************/
int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit);
int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
void I2C_DeInit(CM_I2C_TypeDef *I2Cx);
int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock);
void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState);
/* Start/Restart/Stop ************************************************/
void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx);
void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx);
void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx);
/* Status management *************************************************/
en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
/* Data transfer ************************************ ***************/
void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data);
uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx);
void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig);
/* Time out function *************************************************/
void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH);
void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL);
void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
/* High level functions for reference ********************************/
int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout);
int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout);
/**
* @}
*/
#endif /* LL_I2C_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_I2C_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_i2s.h
* @brief This file contains all the functions prototypes of the I2S driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_I2S_H__
#define __HC32_LL_I2S_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_I2S
* @{
*/
#if (LL_I2S_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2S_Global_Types I2S Global Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S.
This parameter can be a value of @ref I2S_Clock_Source */
uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S.
This parameter can be a value of @ref I2S_Mode */
uint32_t u32Protocol; /*!< Specifies the communication protocol of I2S.
This parameter can be a value of @ref I2S_Protocol */
uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication.
This parameter can be a value of @ref I2S_Trans_Mode */
uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t u32ChWidth; /*!< Specifies the channel length for the I2S communication.
This parameter can be a value of @ref I2S_Channel_Length */
uint32_t u32DataWidth; /*!< Specifies the data length for the I2S communication.
This parameter can be a value of @ref I2S_Data_Length */
uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S.
This parameter can be a value of @ref I2S_MCK_Output */
uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO.
This parameter can be a value of @ref I2S_Trans_Level */
uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO.
This parameter can be a value of @ref I2S_Receive_Level */
} stc_i2s_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2S_Global_Macros I2S Global Macros
* @{
*/
/**
* @defgroup I2S_External_Clock_Frequency I2S External Clock Frequency
* @{
*/
#ifndef I2S_EXT_CLK_FREQ
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
#endif /* I2S_EXT_CLK_FREQ */
/**
* @}
*/
/**
* @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */
#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */
/**
* @}
*/
/**
* @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MD_MASTER (0UL) /*!< Master mode */
#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */
/**
* @}
*/
/**
* @defgroup I2S_Protocol I2S Communication Protocol
* @{
*/
#define I2S_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */
#define I2S_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */
#define I2S_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */
#define I2S_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */
#define I2S_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */
/**
* @}
*/
/**
* @defgroup I2S_Trans_Mode I2S Transfer Mode
* @{
*/
#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */
#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */
#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */
/**
* @}
*/
/**
* @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */
#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */
#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */
#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */
#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */
#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */
#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */
#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */
#define I2S_AUDIO_FREQ_DEFAULT (2UL)
/**
* @}
*/
/**
* @defgroup I2S_Channel_Length I2S Channel Length
* @{
*/
#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */
#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */
/**
* @}
*/
/**
* @defgroup I2S_Data_Length I2S Data Length
* @{
*/
#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */
#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */
#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */
/**
* @}
*/
/**
* @defgroup I2S_MCK_Output I2S MCK Output
* @{
*/
#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */
#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */
/**
* @}
*/
/**
* @defgroup I2S_Trans_Level I2S Transfer Level
* @{
*/
#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */
#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */
#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */
#define I2S_TRANS_LVL3 (0x03UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 3 */
#define I2S_TRANS_LVL4 (0x04UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 4 */
/**
* @}
*/
/**
* @defgroup I2S_Receive_Level I2S Receive Level
* @{
*/
#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */
#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */
#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */
#define I2S_RECEIVE_LVL3 (0x03UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 3 */
#define I2S_RECEIVE_LVL4 (0x04UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 4 */
/**
* @}
*/
/**
* @defgroup I2S_Com_Func I2S Communication Function
* @{
*/
#define I2S_FUNC_TX (I2S_CTRL_TXE) /*!< Transfer function */
#define I2S_FUNC_RX (I2S_CTRL_RXE) /*!< Receive function */
#define I2S_FUNC_ALL (I2S_FUNC_TX | I2S_FUNC_RX)
/**
* @}
*/
/**
* @defgroup I2S_Reset_Type I2S Reset Type
* @{
*/
#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */
#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */
#define I2S_RST_TYPE_SW (I2S_CTRL_SRST) /*!< I2S software reset */
#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO | I2S_RST_TYPE_SW)
/**
* @}
*/
/**
* @defgroup I2S_Interrupt I2S Interrupt
* @{
*/
#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */
#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */
#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */
#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR)
/**
* @}
*/
/**
* @defgroup I2S_Flag I2S Flag
* @{
*/
#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */
#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */
#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */
#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */
#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */
#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */
#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */
#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */
#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \
I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \
I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
#define I2S_FLAG_CLR_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2S_Global_Functions
* @{
*/
/* Initialization and configuration functions */
void I2S_DeInit(CM_I2S_TypeDef *I2Sx);
int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit);
int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit);
void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type);
void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode);
void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level);
void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level);
void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol);
int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq);
void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState);
void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState);
/* Transfer and receive data functions */
void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data);
uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx);
int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout);
int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf,
void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
/* Interrupt and flag management functions */
void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag);
void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_I2S_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_I2S_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_icg.h
* @brief This file contains all the Macro Definitions of the ICG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_ICG_H__
#define __HC32_LL_ICG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_ICG
* @{
*/
#if (LL_ICG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup ICG_Global_Macros ICG Global Macros
* @{
*/
/**
* @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
* @{
*/
#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */
#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type
* @{
*/
#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */
#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period
* @{
*/
#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
* @{
*/
#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */
#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */
#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */
#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */
#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */
#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */
#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
* @{
*/
#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */
#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */
#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */
#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */
#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */
#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */
#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */
#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */
#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */
#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */
#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */
#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
* @brief Counting control of SWDT in sleep/stop mode
* @{
*/
#define ICG_SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */
#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */
/**
* @}
*/
/* WDT function */
/**
* @defgroup ICG_WDT_Reset_State ICG WDT Reset State
* @{
*/
#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */
#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type
* @{
*/
#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Count_Period ICG WDT Count Period
* @{
*/
#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS
#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */
#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */
#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
* @{
*/
#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS
#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */
#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */
#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */
#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */
#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */
#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */
#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */
#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
* @{
*/
#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS
#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */
#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */
#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */
#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */
#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */
#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */
#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */
#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */
#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */
#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */
#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */
#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */
#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */
#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */
#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */
/**
* @}
*/
/**
* @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
* @brief Counting control of WDT in sleep mode
* @{
*/
#define ICG_WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */
#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */
/**
* @}
*/
/* NMI Pin function */
/* BOR function */
/**
* @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
* @{
*/
#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */
#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
/**
* @}
*/
/**
* @defgroup ICG_BOR_Reset_State ICG BOR Reset State
* @{
*/
#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
* @{
*/
#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */
#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Reset_State ICG HRC Reset State
* @{
*/
#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
/**
* @}
*/
/* LVD function */
/* Core lockup function */
/* Flash function */
/**
* @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State
* @{
*/
#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */
#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */
/**
* @}
*/
/**
* @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State
* @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF
* @{
*/
#define ICG_FLASH_PROTECT_RST_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */
#define ICG_FLASH_PROTECT_RST_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Configuration ICG Register Configuration
* @{
*/
/**
*******************************************************************************
* @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
* @{
*******************************************************************************
*/
/* SWDT register config */
#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_STOP)
#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST)
#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD65536)
#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV2048)
#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP)
/* SWDT register value */
#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \
ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
* @{
*******************************************************************************
*/
/* WDT register config */
#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP)
#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST)
#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536)
#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192)
#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP)
/* WDT register value */
#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \
ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
* @{
*******************************************************************************
*/
/* BOR register config */
#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3)
#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE)
/* BOR register value */
#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
* @{
*******************************************************************************
*/
/* HRC register config */
#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M)
#define ICG_RB_HRC_STOP (ICG_HRC_RST_STOP)
/* HRC register value */
#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Bank register value */
#define ICG_REG_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Read Protect register value */
#define ICG_REG_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RST_DISABLE)
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Value ICG Register Value
* @{
*/
/* ICG register value */
#ifndef ICG_REG_CFG0_CONST
#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL)
#endif
#ifndef ICG_REG_CFG1_CONST
#define ICG_REG_CFG1_CONST (ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0xFFF8FEFEUL)
#endif
#ifndef ICG_REG_CFG2_CONST
#define ICG_REG_CFG2_CONST (ICG_REG_FLASH_BANK_CONFIG | 0xFF000000UL)
#endif
#ifndef ICG_REG_CFG3_CONST
#define ICG_REG_CFG3_CONST (ICG_REG_FLASH_PROTECT_CONFIG | 0xFFFF0000UL)
#endif
/* ICG reserved value */
#define ICG_REG_RESV_CONST (0xFFFFFFFFUL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
#endif /* LL_ICG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_ICG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,591 @@
/**
*******************************************************************************
* @file hc32_ll_interrupts.h
* @brief This file contains all the functions prototypes of the interrupt driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_INTERRUPTS_H__
#define __HC32_LL_INTERRUPTS_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_INTERRUPTS
* @{
*/
#if (LL_INTERRUPTS_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup INTC_Global_Types INTC Global Types
* @{
*/
/**
* @brief Interrupt registration structure definition
*/
typedef struct {
en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */
IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */
func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */
} stc_irq_signin_config_t;
/**
* @brief NMI initialize configuration structure definition
*/
typedef struct {
uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */
} stc_nmi_init_t;
/**
* @brief EXTINT initialize configuration structure definition
*/
typedef struct {
uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */
uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */
uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */
uint32_t u32FilterB; /*!< NMI, ExtInt filter B function setting, @ref NMI_EXTINT_FilterBClock_Sel for details */
uint32_t u32FilterBClock; /*!< NMI, ExtInt filter B time, @ref NMI_EXTINT_FilterBTim_Sel for details */
} stc_extint_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup INTC_Global_Macros INTC Global Macros
* @{
*/
/**
* @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15
* @{
*/
#define DDL_IRQ_PRIO_00 (0U)
#define DDL_IRQ_PRIO_01 (1U)
#define DDL_IRQ_PRIO_02 (2U)
#define DDL_IRQ_PRIO_03 (3U)
#define DDL_IRQ_PRIO_04 (4U)
#define DDL_IRQ_PRIO_05 (5U)
#define DDL_IRQ_PRIO_06 (6U)
#define DDL_IRQ_PRIO_07 (7U)
#define DDL_IRQ_PRIO_08 (8U)
#define DDL_IRQ_PRIO_09 (9U)
#define DDL_IRQ_PRIO_10 (10U)
#define DDL_IRQ_PRIO_11 (11U)
#define DDL_IRQ_PRIO_12 (12U)
#define DDL_IRQ_PRIO_13 (13U)
#define DDL_IRQ_PRIO_14 (14U)
#define DDL_IRQ_PRIO_15 (15U)
#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15)
/**
* @}
*/
/**
* @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection
* @{
*/
#define NMI_SRC_SWDT (INTC_NMIFR_SWDTFR)
#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1FR)
#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2FR)
#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPFR)
#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_REPFR)
#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCFR)
#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSMFR)
#define NMI_SRC_WDT (INTC_NMIFR_WDTFR)
#define NMI_SRC_ALL (NMI_SRC_SWDT | NMI_SRC_LVD1 | NMI_SRC_LVD2 | \
NMI_SRC_XTAL | NMI_SRC_BUS_ERR | NMI_SRC_SRAM_PARITY | \
NMI_SRC_WDT | NMI_SRC_SRAM_ECC)
/**
* @}
*/
/**
* @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection
* @{
*/
#define EXTINT_CH00 (1UL << 0U)
#define EXTINT_CH01 (1UL << 1U)
#define EXTINT_CH02 (1UL << 2U)
#define EXTINT_CH03 (1UL << 3U)
#define EXTINT_CH04 (1UL << 4U)
#define EXTINT_CH05 (1UL << 5U)
#define EXTINT_CH06 (1UL << 6U)
#define EXTINT_CH07 (1UL << 7U)
#define EXTINT_CH08 (1UL << 8U)
#define EXTINT_CH09 (1UL << 9U)
#define EXTINT_CH10 (1UL <<10U)
#define EXTINT_CH11 (1UL <<11U)
#define EXTINT_CH12 (1UL <<12U)
#define EXTINT_CH13 (1UL <<13U)
#define EXTINT_CH14 (1UL <<14U)
#define EXTINT_CH15 (1UL <<15U)
#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \
EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \
EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \
EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15)
/**
* @}
*/
/**
* @defgroup INT_Channel_Sel Interrupt Channel Selection
* @{
*/
#define INTC_INT0 INTC_IER_IER0
#define INTC_INT1 INTC_IER_IER1
#define INTC_INT2 INTC_IER_IER2
#define INTC_INT3 INTC_IER_IER3
#define INTC_INT4 INTC_IER_IER4
#define INTC_INT5 INTC_IER_IER5
#define INTC_INT6 INTC_IER_IER6
#define INTC_INT7 INTC_IER_IER7
#define INTC_INT8 INTC_IER_IER8
#define INTC_INT9 INTC_IER_IER9
#define INTC_INT10 INTC_IER_IER10
#define INTC_INT11 INTC_IER_IER11
#define INTC_INT12 INTC_IER_IER12
#define INTC_INT13 INTC_IER_IER13
#define INTC_INT14 INTC_IER_IER14
#define INTC_INT15 INTC_IER_IER15
#define INTC_INT16 INTC_IER_IER16
#define INTC_INT17 INTC_IER_IER17
#define INTC_INT18 INTC_IER_IER18
#define INTC_INT19 INTC_IER_IER19
#define INTC_INT20 INTC_IER_IER20
#define INTC_INT21 INTC_IER_IER21
#define INTC_INT22 INTC_IER_IER22
#define INTC_INT23 INTC_IER_IER23
#define INTC_INT24 INTC_IER_IER24
#define INTC_INT25 INTC_IER_IER25
#define INTC_INT26 INTC_IER_IER26
#define INTC_INT27 INTC_IER_IER27
#define INTC_INT28 INTC_IER_IER28
#define INTC_INT29 INTC_IER_IER29
#define INTC_INT30 INTC_IER_IER30
#define INTC_INT31 INTC_IER_IER31
#define INTC_INT_ALL (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @defgroup INTC_Event_Channel_Sel Event Channel Selection
* @{
*/
#define INTC_EVT0 INTC_EVTER_EVTE0
#define INTC_EVT1 INTC_EVTER_EVTE1
#define INTC_EVT2 INTC_EVTER_EVTE2
#define INTC_EVT3 INTC_EVTER_EVTE3
#define INTC_EVT4 INTC_EVTER_EVTE4
#define INTC_EVT5 INTC_EVTER_EVTE5
#define INTC_EVT6 INTC_EVTER_EVTE6
#define INTC_EVT7 INTC_EVTER_EVTE7
#define INTC_EVT8 INTC_EVTER_EVTE8
#define INTC_EVT9 INTC_EVTER_EVTE9
#define INTC_EVT10 INTC_EVTER_EVTE10
#define INTC_EVT11 INTC_EVTER_EVTE11
#define INTC_EVT12 INTC_EVTER_EVTE12
#define INTC_EVT13 INTC_EVTER_EVTE13
#define INTC_EVT14 INTC_EVTER_EVTE14
#define INTC_EVT15 INTC_EVTER_EVTE15
#define INTC_EVT16 INTC_EVTER_EVTE16
#define INTC_EVT17 INTC_EVTER_EVTE17
#define INTC_EVT18 INTC_EVTER_EVTE18
#define INTC_EVT19 INTC_EVTER_EVTE19
#define INTC_EVT20 INTC_EVTER_EVTE20
#define INTC_EVT21 INTC_EVTER_EVTE21
#define INTC_EVT22 INTC_EVTER_EVTE22
#define INTC_EVT23 INTC_EVTER_EVTE23
#define INTC_EVT24 INTC_EVTER_EVTE24
#define INTC_EVT25 INTC_EVTER_EVTE25
#define INTC_EVT26 INTC_EVTER_EVTE26
#define INTC_EVT27 INTC_EVTER_EVTE27
#define INTC_EVT28 INTC_EVTER_EVTE28
#define INTC_EVT29 INTC_EVTER_EVTE29
#define INTC_EVT30 INTC_EVTER_EVTE30
#define INTC_EVT31 INTC_EVTER_EVTE31
#define INTC_EVT_ALL (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection
* @{
*/
#define SWINT_CH00 INTC_SWIER_SWIE0
#define SWINT_CH01 INTC_SWIER_SWIE1
#define SWINT_CH02 INTC_SWIER_SWIE2
#define SWINT_CH03 INTC_SWIER_SWIE3
#define SWINT_CH04 INTC_SWIER_SWIE4
#define SWINT_CH05 INTC_SWIER_SWIE5
#define SWINT_CH06 INTC_SWIER_SWIE6
#define SWINT_CH07 INTC_SWIER_SWIE7
#define SWINT_CH08 INTC_SWIER_SWIE8
#define SWINT_CH09 INTC_SWIER_SWIE9
#define SWINT_CH10 INTC_SWIER_SWIE10
#define SWINT_CH11 INTC_SWIER_SWIE11
#define SWINT_CH12 INTC_SWIER_SWIE12
#define SWINT_CH13 INTC_SWIER_SWIE13
#define SWINT_CH14 INTC_SWIER_SWIE14
#define SWINT_CH15 INTC_SWIER_SWIE15
#define SWINT_CH16 INTC_SWIER_SWIE16
#define SWINT_CH17 INTC_SWIER_SWIE17
#define SWINT_CH18 INTC_SWIER_SWIE18
#define SWINT_CH19 INTC_SWIER_SWIE19
#define SWINT_CH20 INTC_SWIER_SWIE20
#define SWINT_CH21 INTC_SWIER_SWIE21
#define SWINT_CH22 INTC_SWIER_SWIE22
#define SWINT_CH23 INTC_SWIER_SWIE23
#define SWINT_CH24 INTC_SWIER_SWIE24
#define SWINT_CH25 INTC_SWIER_SWIE25
#define SWINT_CH26 INTC_SWIER_SWIE26
#define SWINT_CH27 INTC_SWIER_SWIE27
#define SWINT_CH28 INTC_SWIER_SWIE28
#define SWINT_CH29 INTC_SWIER_SWIE29
#define SWINT_CH30 INTC_SWIER_SWIE30
#define SWINT_CH31 INTC_SWIER_SWIE31
#define SWINT_ALL (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection
* @{
*/
#define EXTINT_FILTER_OFF (0UL)
#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN
/**
* @}
*/
/**
* @defgroup NMI_EXTINT_FilterBClock_Sel External Interrupt Filter B Function Selection
* @{
*/
#define NMI_EXTINT_FILTER_B_OFF (0UL)
#define NMI_EXTINT_FILTER_B_ON INTC_EIRQCR_NOCEN
/**
* @}
*/
/**
* @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection
* @{
*/
#define EXTINT_FCLK_DIV1 (0UL)
#define EXTINT_FCLK_DIV8 INTC_EIRQCR_EISMPCLK_0
#define EXTINT_FCLK_DIV32 INTC_EIRQCR_EISMPCLK_1
#define EXTINT_FCLK_DIV64 INTC_EIRQCR_EISMPCLK
/**
* @}
*/
/**
* @defgroup NMI_EXTINT_FilterBTim_Sel External Interrupt Filter B Time Selection
* @{
*/
#define NMI_EXTINT_FCLK_B_500NS (0UL)
#define NMI_EXTINT_FCLK_B_1US (1UL << INTC_NOCCR_NOCSEL_POS)
#define NMI_EXTINT_FCLK_B_2US (2UL << INTC_NOCCR_NOCSEL_POS)
#define NMI_EXTINT_FCLK_B_4US INTC_NOCCR_NOCSEL
/**
* @}
*/
/**
* @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection
* @{
*/
#define EXTINT_TRIG_FALLING (0UL)
#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0
#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1
#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG
/**
* @}
*/
/**
* @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection
* @{
*/
#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WUPEN_EIRQWUEN_0
#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WUPEN_EIRQWUEN_1
#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WUPEN_EIRQWUEN_2
#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WUPEN_EIRQWUEN_3
#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WUPEN_EIRQWUEN_4
#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WUPEN_EIRQWUEN_5
#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WUPEN_EIRQWUEN_6
#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WUPEN_EIRQWUEN_7
#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WUPEN_EIRQWUEN_8
#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WUPEN_EIRQWUEN_9
#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WUPEN_EIRQWUEN_10
#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WUPEN_EIRQWUEN_11
#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WUPEN_EIRQWUEN_12
#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WUPEN_EIRQWUEN_13
#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WUPEN_EIRQWUEN_14
#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WUPEN_EIRQWUEN_15
#define INTC_STOP_WKUP_SWDT INTC_WUPEN_SWDTWUEN
#define INTC_STOP_WKUP_LVD1 INTC_WUPEN_PVD1WUEN
#define INTC_STOP_WKUP_LVD2 INTC_WUPEN_PVD2WUEN
#define INTC_STOP_WKUP_CMP INTC_WUPEN_CMPWUEN
#define INTC_STOP_WKUP_WKTM INTC_WUPEN_WKTMWUEN
#define INTC_STOP_WKUP_RTC_ALM INTC_WUPEN_RTCALMWUEN
#define INTC_STOP_WKUP_RTC_PRD INTC_WUPEN_RTCPRDWUEN
#define INTC_STOP_WKUP_TMR0_CMP INTC_WUPEN_TMR0GCMWUEN
#define INTC_STOP_WKUP_TMR2_CMP INTC_WUPEN_TMR2GCMWUEN
#define INTC_STOP_WKUP_TMR2_OVF INTC_WUPEN_TMR2OVFWUEN
#define INTC_STOP_WKUP_USART1_RX INTC_WUPEN_RXWUEN
#define INTC_STOP_WKUP_USBHS INTC_WUPEN_USHWUEN
#define INTC_STOP_WKUP_USBFS INTC_WUPEN_USFWUEN
#define INTC_STOP_WKUP_ETH INTC_WUPEN_ETHWUEN
#define INTC_WUPEN_ALL \
(INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \
INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \
INTC_WUPEN_CMPWUEN | INTC_WUPEN_WKTMWUEN | \
INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \
INTC_WUPEN_TMR0GCMWUEN | INTC_WUPEN_TMR2GCMWUEN | \
INTC_WUPEN_TMR2OVFWUEN | INTC_WUPEN_RXWUEN | \
INTC_WUPEN_USHWUEN | INTC_WUPEN_USFWUEN | \
INTC_WUPEN_ETHWUEN)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup INTC_Global_Functions
* @{
*/
int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig);
int32_t INTC_IrqSignOut(IRQn_Type enIRQn);
void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState);
void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState);
void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState);
void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority);
void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState);
int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit);
int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit);
en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src);
void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState);
void NMI_ClearNmiStatus(uint32_t u32Src);
int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit);
int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit);
en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh);
void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh);
void IRQ000_Handler(void);
void IRQ001_Handler(void);
void IRQ002_Handler(void);
void IRQ003_Handler(void);
void IRQ004_Handler(void);
void IRQ005_Handler(void);
void IRQ006_Handler(void);
void IRQ007_Handler(void);
void IRQ008_Handler(void);
void IRQ009_Handler(void);
void IRQ010_Handler(void);
void IRQ011_Handler(void);
void IRQ012_Handler(void);
void IRQ013_Handler(void);
void IRQ014_Handler(void);
void IRQ015_Handler(void);
void IRQ016_Handler(void);
void IRQ017_Handler(void);
void IRQ018_Handler(void);
void IRQ019_Handler(void);
void IRQ020_Handler(void);
void IRQ021_Handler(void);
void IRQ022_Handler(void);
void IRQ023_Handler(void);
void IRQ024_Handler(void);
void IRQ025_Handler(void);
void IRQ026_Handler(void);
void IRQ027_Handler(void);
void IRQ028_Handler(void);
void IRQ029_Handler(void);
void IRQ030_Handler(void);
void IRQ031_Handler(void);
void IRQ032_Handler(void);
void IRQ033_Handler(void);
void IRQ034_Handler(void);
void IRQ035_Handler(void);
void IRQ036_Handler(void);
void IRQ037_Handler(void);
void IRQ038_Handler(void);
void IRQ039_Handler(void);
void IRQ040_Handler(void);
void IRQ041_Handler(void);
void IRQ042_Handler(void);
void IRQ043_Handler(void);
void IRQ044_Handler(void);
void IRQ045_Handler(void);
void IRQ046_Handler(void);
void IRQ047_Handler(void);
void IRQ048_Handler(void);
void IRQ049_Handler(void);
void IRQ050_Handler(void);
void IRQ051_Handler(void);
void IRQ052_Handler(void);
void IRQ053_Handler(void);
void IRQ054_Handler(void);
void IRQ055_Handler(void);
void IRQ056_Handler(void);
void IRQ057_Handler(void);
void IRQ058_Handler(void);
void IRQ059_Handler(void);
void IRQ060_Handler(void);
void IRQ061_Handler(void);
void IRQ062_Handler(void);
void IRQ063_Handler(void);
void IRQ064_Handler(void);
void IRQ065_Handler(void);
void IRQ066_Handler(void);
void IRQ067_Handler(void);
void IRQ068_Handler(void);
void IRQ069_Handler(void);
void IRQ070_Handler(void);
void IRQ071_Handler(void);
void IRQ072_Handler(void);
void IRQ073_Handler(void);
void IRQ074_Handler(void);
void IRQ075_Handler(void);
void IRQ076_Handler(void);
void IRQ077_Handler(void);
void IRQ078_Handler(void);
void IRQ079_Handler(void);
void IRQ080_Handler(void);
void IRQ081_Handler(void);
void IRQ082_Handler(void);
void IRQ083_Handler(void);
void IRQ084_Handler(void);
void IRQ085_Handler(void);
void IRQ086_Handler(void);
void IRQ087_Handler(void);
void IRQ088_Handler(void);
void IRQ089_Handler(void);
void IRQ090_Handler(void);
void IRQ091_Handler(void);
void IRQ092_Handler(void);
void IRQ093_Handler(void);
void IRQ094_Handler(void);
void IRQ095_Handler(void);
void IRQ096_Handler(void);
void IRQ097_Handler(void);
void IRQ098_Handler(void);
void IRQ099_Handler(void);
void IRQ100_Handler(void);
void IRQ101_Handler(void);
void IRQ102_Handler(void);
void IRQ103_Handler(void);
void IRQ104_Handler(void);
void IRQ105_Handler(void);
void IRQ106_Handler(void);
void IRQ107_Handler(void);
void IRQ108_Handler(void);
void IRQ109_Handler(void);
void IRQ110_Handler(void);
void IRQ111_Handler(void);
void IRQ112_Handler(void);
void IRQ113_Handler(void);
void IRQ114_Handler(void);
void IRQ115_Handler(void);
void IRQ116_Handler(void);
void IRQ117_Handler(void);
void IRQ118_Handler(void);
void IRQ119_Handler(void);
void IRQ120_Handler(void);
void IRQ121_Handler(void);
void IRQ122_Handler(void);
void IRQ123_Handler(void);
void IRQ124_Handler(void);
void IRQ125_Handler(void);
void IRQ126_Handler(void);
void IRQ127_Handler(void);
/**
* @}
*/
#endif /* LL_INTERRUPTS_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_INTERRUPTS_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_keyscan.h
* @brief This file contains all the functions prototypes of the KEYSCAN driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_KEYSCAN_H__
#define __HC32_LL_KEYSCAN_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_KEYSCAN
* @{
*/
#if (LL_KEYSCAN_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Types KEYSCAN Global Types
* @{
*/
/**
* @brief KEYSCAN configuration
*/
typedef struct {
uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles.
This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */
uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */
uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Clock_Sel */
uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyout_Sel */
uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyin_Sel */
} stc_keyscan_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros
* @{
*/
/**
* @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection
* @{
*/
#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */
#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection
* @{
*/
#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */
#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */
#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */
#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */
#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */
#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */
#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */
#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */
#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */
#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */
#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */
#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */
#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */
#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */
#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */
#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */
#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */
#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */
#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */
#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */
#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */
#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */
#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection
* @{
*/
#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */
#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */
#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection
* @{
*/
#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */
#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */
#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */
#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */
#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */
#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */
#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection
* @{
*/
#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */
#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */
#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */
#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */
#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */
#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */
#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */
#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */
#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */
#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */
#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */
#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */
#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */
#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */
#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */
#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */
#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup KEYSCAN_Global_Functions
* @{
*/
/**
* @brief Get KEYOUT index.
* @param None
* @retval uint32_t: KEYOUT index 0~7.
*/
__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void)
{
return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX);
}
int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit);
int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit);
void KEYSCAN_Cmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_KEYSCAN_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_KEYSCAN_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_mau.h
* @brief This file contains all the functions prototypes of the MAU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_MAU_H__
#define __HC32_LL_MAU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_MAU
* @{
*/
#if (LL_MAU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup MAU_Global_Macros MAU Global Macros
* @{
*/
#define MAU_SQRT_TIMEOUT (HCLK_VALUE / 10000UL)/* About 1mS timeout */
#define MAU_SQRT_OUTPUT_LSHIFT_MAX (16U)
#define MAU_SIN_Q15_SCALAR (0x8000UL)
#define MAU_SIN_ANGIDX_TOTAL (0x1000UL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup MAU_Global_Functions
* @{
*/
void MAU_SqrtInit(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState);
void MAU_SqrtDeInit(CM_MAU_TypeDef *MAUx);
void MAU_SqrtResultLShiftConfig(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber);
void MAU_SqrtIntCmd(CM_MAU_TypeDef *MAUx, en_functional_state_t enNewState);
void MAU_SqrtWriteData(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand);
en_flag_status_t MAU_SqrtGetStatus(const CM_MAU_TypeDef *MAUx);
uint32_t MAU_SqrtReadData(const CM_MAU_TypeDef *MAUx);
void MAU_SqrtStart(CM_MAU_TypeDef *MAUx);
int32_t MAU_Sqrt(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result);
int16_t MAU_Sin(CM_MAU_TypeDef *MAUx, uint16_t u16AngleIdx);
/**
* @}
*/
#endif /* LL_MAU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_MAU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_mpu.h
* @brief This file contains all the functions prototypes of the MPU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_MPU_H__
#define __HC32_LL_MPU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_MPU
* @{
*/
#if (LL_MPU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup MPU_Global_Types MPU Global Types
* @{
*/
/**
* @brief MPU Unit configure structure definition
*/
typedef struct {
uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region.
This parameter can be a value of @ref MPU_Exception_Type */
uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space.
This parameter can be a value of @ref MPU_Background_Write_Permission */
uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space
This parameter can be a value of @ref MPU_Background_Read_Permission */
} stc_mpu_unit_config_t;
/**
* @brief MPU Init structure definition
*/
typedef struct {
stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */
stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */
stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */
stc_mpu_unit_config_t stcUsbHSDma; /*!< Configure storage protection unit of USBHS_DMA */
stc_mpu_unit_config_t stcEthDma; /*!< Configure storage protection unit of ETH_DMA */
} stc_mpu_init_t;
/**
* @brief MPU Region Permission structure definition
*/
typedef struct {
uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region.
This parameter can be a value of @ref MPU_Region_Write_Permission */
uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region.
This parameter can be a value of @ref MPU_Region_Read_Permission */
} stc_mpu_region_permission_t;
/**
* @brief MPU region initialization structure definition
* @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region,
* and the low 'u32Size+1' bits are fixed at 0.
*/
typedef struct {
uint32_t u32BaseAddr; /*!< Specifies the base address of the region.
This parameter can be a number between 0UL and 0xFFFFFFE0UL */
uint32_t u32Size; /*!< Specifies the size of the region.
This parameter can be a value of @ref MPU_Region_Size */
stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */
stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */
stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */
stc_mpu_region_permission_t stcUsbHSDma; /*!< Specifies the USBHS_DMA access permission for the region */
stc_mpu_region_permission_t stcEthDma; /*!< Specifies the ETH_DMA access permission for the region */
} stc_mpu_region_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup MPU_Global_Macros MPU Global Macros
* @{
*/
/**
* @defgroup MPU_Unit_Type MPU Unit Type
* @{
*/
#define MPU_UNIT_DMA1 (0x01UL) /*!< System DMA_1 MPU */
#define MPU_UNIT_DMA2 (0x02UL) /*!< System DMA_2 MPU */
#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */
#define MPU_UNIT_USBHS_DMA (0x08UL) /*!< USBHS_DMA MPU */
#define MPU_UNIT_ETH_DMA (0x10UL) /*!< ETH_DMA MPU */
#define MPU_UNIT_ALL (MPU_UNIT_DMA1 | MPU_UNIT_DMA2 | MPU_UNIT_USBFS_DMA | \
MPU_UNIT_USBHS_DMA | MPU_UNIT_ETH_DMA)
/**
* @}
*/
/**
* @defgroup MPU_Region_Number MPU Region Number
* @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
* @{
*/
#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */
#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */
#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */
#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */
#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */
#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */
#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */
#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */
#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */
#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */
#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */
#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */
#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */
#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */
#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */
#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */
/**
* @}
*/
/**
* @defgroup MPU_Background_Write_Permission MPU Background Write Permission
* @{
*/
#define MPU_BACKGROUND_WR_DISABLE (MPU_S1CR_SMPU1BWP) /*!< Disable write the background space */
#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */
/**
* @}
*/
/**
* @defgroup MPU_Background_Read_Permission MPU Background Read Permission
* @{
*/
#define MPU_BACKGROUND_RD_DISABLE (MPU_S1CR_SMPU1BRP) /*!< Disable read the background space */
#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */
/**
* @}
*/
/**
* @defgroup MPU_Exception_Type MPU Exception Type
* @{
*/
#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */
#define MPU_EXP_TYPE_BUS_ERR (MPU_S1CR_SMPU1ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */
#define MPU_EXP_TYPE_NMI (MPU_S1CR_SMPU1ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */
#define MPU_EXP_TYPE_RST (MPU_S1CR_SMPU1ACT) /*!< The host unit access protection regions will trigger the reset */
/**
* @}
*/
/**
* @defgroup MPU_Region_Write_Permission MPU Region Write Permission
* @{
*/
#define MPU_REGION_WR_DISABLE (MPU_S1RGWP_S1RG0WP) /*!< Disable write the region */
#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */
/**
* @}
*/
/**
* @defgroup MPU_Region_Read_Permission MPU Region Read Permission
* @{
*/
#define MPU_REGION_RD_DISABLE (MPU_S1RGRP_S1RG0RP) /*!< Disable read the region */
#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */
/**
* @}
*/
/**
* @defgroup MPU_Region_Size MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */
#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */
#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */
#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */
#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */
#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */
#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */
#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */
#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */
#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */
#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */
#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */
#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */
#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */
#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */
#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */
#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */
#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */
#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */
#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */
#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */
#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */
#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */
#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */
#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */
#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */
#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */
#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */
/**
* @}
*/
/**
* @defgroup MPU_Flag MPU Flag
* @{
*/
#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */
#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */
#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */
#define MPU_FLAG_HMPUEAF (MPU_SR_HMPUEAF) /*!< USBHS_DMA error flag */
#define MPU_FLAG_EMPUEAF (MPU_SR_EMPUEAF) /*!< ETH_DMA error flag */
#define MPU_FLAG_ALL (MPU_FLAG_SMPU1EAF | MPU_FLAG_SMPU2EAF | MPU_FLAG_FMPUEAF | \
MPU_FLAG_HMPUEAF | MPU_FLAG_EMPUEAF)
/**
* @}
*/
/**
* @defgroup MPU_IP_Type MPU IP Type
* @note IP access protection is not available in privileged mode.
* @{
*/
#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */
#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */
#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */
#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */
#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */
#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */
#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */
#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */
#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */
#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */
#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */
#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */
#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */
#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */
#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \
MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \
MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \
MPU_IP_FCG | MPU_IP_RMU_CMU_PWC)
/**
* @}
*/
/**
* @defgroup MPU_IP_Exception_Type MPU IP Exception Type
* @{
*/
#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */
#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */
/**
* @}
*/
/**
* @defgroup MPU_Register_Protect_Key INTC Registers Protect Key
* @{
*/
#define MPU_REG_LOCK_KEY (0x96A4UL)
#define MPU_REG_UNLOCK_KEY (0x96A5UL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup MPU_Global_Functions
* @{
*/
/**
* @brief MPU write protect unlock.
* @param None
* @retval None
*/
__STATIC_INLINE void MPU_REG_Unlock(void)
{
WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY);
}
/**
* @brief MPU write protect lock.
* @param None
* @retval None
*/
__STATIC_INLINE void MPU_REG_Lock(void)
{
WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY);
}
void MPU_REG_Unlock(void);
void MPU_REG_Lock(void);
void MPU_DeInit(void);
int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit);
int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit);
void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type);
void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState);
en_flag_status_t MPU_GetStatus(uint32_t u32Flag);
void MPU_ClearStatus(uint32_t u32Flag);
int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit);
int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit);
void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr);
void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size);
void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_IP_SetExceptionType(uint32_t u32Type);
void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState);
void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_MPU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_MPU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,591 @@
/**
*******************************************************************************
* @file hc32_ll_nfc.h
* @brief This file contains all the functions prototypes of the EXMC NFC
* (External Memory Controller: NAND Flash Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_NFC_H__
#define __HC32_LL_NFC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EXMC
* @{
*/
/**
* @addtogroup LL_NFC
* @{
*/
#if (LL_NFC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_NFC_Global_Types EXMC_NFC Global Types
* @{
*/
/**
* @brief EXMC_NFC Base Configuration Structure definition
*/
typedef struct {
uint32_t u32CapacitySize; /*!< Defines the capacity size.
This parameter can be a value of @ref EXMC_NFC_BANK_Memory_Capacity. */
uint32_t u32MemoryWidth; /*!< Defines the memory width.
This parameter can be a value of @ref EXMC_NFC_Memory_Width. */
uint32_t u32BankNum; /*!< Defines the bank number.
This parameter can be a value of @ref EXMC_NFC_Bank_Number */
uint32_t u32PageSize; /*!< Defines the page size.
This parameter can be a value of @ref EXMC_NFC_Page_Size. */
uint32_t u32WriteProtect; /*!< Defines the write protect.
This parameter can be a value of @ref EXMC_NFC_Write_Protect. */
uint32_t u32EccMode; /*!< Defines the ECC mode.
This parameter can be a value of @ref EXMC_NFC_ECC_Mode. */
uint32_t u32RowAddrCycle; /*!< Defines the row address cycle.
This parameter can be a value of @ref EXMC_NFC_Row_Address_Cycle. */
uint8_t u8SpareSizeForUserData; /*!< Defines the spare column size for user data.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_base_config_t;
/**
* @brief EXMC_NFC Timing Register 0 Configuration Structure definition
*/
typedef struct {
uint32_t u32TS; /*!< Defines the CLE/ALE/CE setup time in memory clock cycles(tALS/tCS/tCLS).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWP; /*!< Defines the WE# pulse width time in memory clock cycles(tWP).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRP; /*!< Defines the RE# pulse width time in memory clock cycles(tRP).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TH; /*!< Defines the CLE/ALE/CE hold time in memory clock cycles(tALH/tCH/tCLH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_timing_reg0_config_t;
/**
* @brief EXMC_NFC Timing Register 1 Configuration Structure definition
*/
typedef struct {
uint32_t u32TWH; /*!< Defines the WE# pulse width HIGH time in memory clock cycles(tWH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRH; /*!< Defines the RE# HIGH hold time in memory clock cycles(tREH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRR; /*!< Defines the Ready to RE# LOW time in memory clock cycles(tRR).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWB; /*!< Defines the WE# HIGH to busy time in memory clock cycles(tWB).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_timing_reg1_config_t;
/**
* @brief EXMC_NFC Timing Register 2 Configuration Structure definition
*/
typedef struct {
uint32_t u32TCCS; /*!< Defines the command(change read/write column) delay time in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWTR; /*!< Defines the WE# HIGH to RE# LOW time in memory clock cycles(tWHR).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRTW; /*!< Defines the RE# HIGH to WE# LOW time in memory clock cycles(tRHW).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TADL; /*!< Defines the Address to Data Loading time in memory clock cycles(tADL).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_timing_reg2_config_t;
/**
* @brief EXMC_NFC Initialization Structure definition
*/
typedef struct {
uint32_t u32OpenPage; /*!< NFC memory open-page selection.
This structure details refer @ref EXMC_NFC_Open_Page. */
stc_exmc_nfc_base_config_t stcBaseConfig; /*!< NFC memory base configure.
This structure details refer @ref stc_exmc_nfc_base_config_t. */
stc_exmc_nfc_timing_reg0_config_t stcTimingReg0; /*!< NFC memory timing configure 0.
This structure details refer @ref stc_exmc_nfc_timing_reg0_config_t. */
stc_exmc_nfc_timing_reg1_config_t stcTimingReg1; /*!< NFC memory timing configure 1.
This structure details refer @ref stc_exmc_nfc_timing_reg1_config_t. */
stc_exmc_nfc_timing_reg2_config_t stcTimingReg2; /*!< NFC memory timing configure 2.
This structure details refer @ref stc_exmc_nfc_timing_reg2_config_t. */
} stc_exmc_nfc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_NFC_Global_Macros EXMC_NFC Global Macros
* @{
*/
/**
* @defgroup EXMC_NFC_Bank EXMC_NFC Bank
* @{
*/
#define EXMC_NFC_BANK0 (0UL) /*!< Bank 0 */
#define EXMC_NFC_BANK1 (1UL) /*!< Bank 1 */
#define EXMC_NFC_BANK2 (2UL) /*!< Bank 2 */
#define EXMC_NFC_BANK3 (3UL) /*!< Bank 3 */
#define EXMC_NFC_BANK4 (4UL) /*!< Bank 4 */
#define EXMC_NFC_BANK5 (5UL) /*!< Bank 5 */
#define EXMC_NFC_BANK6 (6UL) /*!< Bank 6 */
#define EXMC_NFC_BANK7 (7UL) /*!< Bank 7 */
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Page_Size EXMC_NFC Page Size
* @{
*/
#define EXMC_NFC_PAGE_SIZE_2KBYTE (NFC_BACR_PAGE_0)
#define EXMC_NFC_PAGE_SIZE_4KBYTE (NFC_BACR_PAGE_1)
#define EXMC_NFC_PAGE_SIZE_8KBYTE (NFC_BACR_PAGE)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_BANK_Memory_Capacity EXMC_NFC BANK Memory Capacity
* @{
*/
#define EXMC_NFC_BANK_CAPACITY_512MBIT (3UL)
#define EXMC_NFC_BANK_CAPACITY_1GBIT (4UL)
#define EXMC_NFC_BANK_CAPACITY_2GBIT (5UL)
#define EXMC_NFC_BANK_CAPACITY_4GBIT (6UL)
#define EXMC_NFC_BANK_CAPACITY_8GBIT (7UL)
#define EXMC_NFC_BANK_CAPACITY_16GBIT (0UL)
#define EXMC_NFC_BANK_CAPACITY_32GBIT (1UL)
#define EXMC_NFC_BANK_CAPACITY_64GBIT (2UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Memory_Width EXMC_NFC Memory Width
* @{
*/
#define EXMC_NFC_MEMORY_WIDTH_8BIT (0UL)
#define EXMC_NFC_MEMORY_WIDTH_16BIT (NFC_BACR_B16BIT)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Bank_Number EXMC_NFC Bank Number
* @{
*/
#define EXMC_NFC_1BANK (0UL)
#define EXMC_NFC_2BANKS (NFC_BACR_BANK_0)
#define EXMC_NFC_4BANKS (NFC_BACR_BANK_1)
#define EXMC_NFC_8BANKS (NFC_BACR_BANK)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Open_Page EXMC_NFC Open Page
* @{
*/
#define EXMC_NFC_OPEN_PAGE_DISABLE (0UL)
#define EXMC_NFC_OPEN_PAGE_ENABLE (PERIC_NFC_STCR_OPENP)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Write_Protect EXMC_NFC Write Protect
* @{
*/
#define EXMC_NFC_WR_PROTECT_ENABLE (0UL)
#define EXMC_NFC_WR_PROTECT_DISABLE (NFC_BACR_WP)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Mode EXMC_NFC ECC Mode
* @{
*/
#define EXMC_NFC_1BIT_ECC (0UL)
#define EXMC_NFC_4BIT_ECC (NFC_BACR_ECCM_0)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Row_Address_Cycle EXMC_NFC Row Address Cycle
* @{
*/
#define EXMC_NFC_2_ROW_ADDR_CYCLE (0UL)
#define EXMC_NFC_3_ROW_ADDR_CYCLE (NFC_BACR_RAC)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Calculate_Bytes EXMC_NFC ECC Calculate Bytes
* @{
*/
#define EXMC_NFC_ECC_CALCULATE_BLOCK_BYTE (512UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Value_Bytes EXMC_NFC ECC Value Bytes
* @{
*/
#define EXMC_NFC_1BIT_ECC_VALUE_BYTE (3UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_1Bit_ECC_Result EXMC_NFC 1Bit ECC Result
* @{
*/
#define EXMC_NFC_1BIT_ECC_NONE_ERR (0UL)
#define EXMC_NFC_1BIT_ECC_SINGLE_BIT_ERR (NFC_ECCR_SE)
#define EXMC_NFC_1BIT_ECC_MULTIPLE_BITS_ERR (NFC_ECCR_ME)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_1Bit_ECC_Error_Bit_Location EXMC_NFC 1Bit ECC Error Bit Location
* @{
*/
#define EXMC_NFC_1BIT_ECC_ERR_BIT0 (0UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT1 (1UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT2 (2UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT3 (3UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT4 (4UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT5 (5UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT6 (6UL)
#define EXMC_NFC_1BIT_ECC_ERR_BIT7 (7UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Section EXMC_NFC ECC Section
* @{
*/
#define EXMC_NFC_ECC_SECTION0 (0UL)
#define EXMC_NFC_ECC_SECTION1 (1UL)
#define EXMC_NFC_ECC_SECTION2 (2UL)
#define EXMC_NFC_ECC_SECTION3 (3UL)
#define EXMC_NFC_ECC_SECTION4 (4UL)
#define EXMC_NFC_ECC_SECTION5 (5UL)
#define EXMC_NFC_ECC_SECTION6 (6UL)
#define EXMC_NFC_ECC_SECTION7 (7UL)
#define EXMC_NFC_ECC_SECTION8 (8UL)
#define EXMC_NFC_ECC_SECTION9 (9UL)
#define EXMC_NFC_ECC_SECTION10 (10UL)
#define EXMC_NFC_ECC_SECTION11 (11UL)
#define EXMC_NFC_ECC_SECTION12 (12UL)
#define EXMC_NFC_ECC_SECTION13 (13UL)
#define EXMC_NFC_ECC_SECTION14 (14UL)
#define EXMC_NFC_ECC_SECTION15 (15UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Interrupt EXMC_NFC Interrupt
* @{
*/
#define EXMC_NFC_INT_RB_BANK0 (NFC_IENR_RBEN_0)
#define EXMC_NFC_INT_RB_BANK1 (NFC_IENR_RBEN_1)
#define EXMC_NFC_INT_RB_BANK2 (NFC_IENR_RBEN_2)
#define EXMC_NFC_INT_RB_BANK3 (NFC_IENR_RBEN_3)
#define EXMC_NFC_INT_RB_BANK4 (NFC_IENR_RBEN_4)
#define EXMC_NFC_INT_RB_BANK5 (NFC_IENR_RBEN_5)
#define EXMC_NFC_INT_RB_BANK6 (NFC_IENR_RBEN_6)
#define EXMC_NFC_INT_RB_BANK7 (NFC_IENR_RBEN_7)
#define EXMC_NFC_INT_ECC_ERROR (NFC_IENR_ECCEEN)
#define EXMC_NFC_INT_ECC_CALC_COMPLETION (NFC_IENR_ECCCEN)
#define EXMC_NFC_INT_ECC_CORRECTABLE_ERR (NFC_IENR_ECCECEN)
#define EXMC_NFC_INT_ECC_UNCORRECTABLE_ERR (NFC_IENR_ECCEUEN)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Flag EXMC_NFC Flag
* @{
*/
#define EXMC_NFC_FLAG_RB_BANK0 (NFC_ISTR_RBST_0)
#define EXMC_NFC_FLAG_RB_BANK1 (NFC_ISTR_RBST_1)
#define EXMC_NFC_FLAG_RB_BANK2 (NFC_ISTR_RBST_2)
#define EXMC_NFC_FLAG_RB_BANK3 (NFC_ISTR_RBST_3)
#define EXMC_NFC_FLAG_RB_BANK4 (NFC_ISTR_RBST_4)
#define EXMC_NFC_FLAG_RB_BANK5 (NFC_ISTR_RBST_5)
#define EXMC_NFC_FLAG_RB_BANK6 (NFC_ISTR_RBST_6)
#define EXMC_NFC_FLAG_RB_BANK7 (NFC_ISTR_RBST_7)
#define EXMC_NFC_FLAG_ECC_ERR (NFC_ISTR_ECCEST)
#define EXMC_NFC_FLAG_ECC_CALC_COMPLETION (NFC_ISTR_ECCCST)
#define EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR (NFC_ISTR_ECCECST)
#define EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR (NFC_ISTR_ECCEUST)
#define EXMC_NFC_FLAG_ECC_CALCULATING (1UL << 31UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Max_Timeout EXMC_NFC Max Timeout
* @{
*/
#define EXMC_NFC_MAX_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Memory_Command EXMC_NFC Memory Command
* @{
*/
#define EXMC_NFC_CMD_RD_1ST (0x00UL)
#define EXMC_NFC_CMD_RD_2ND (0xE0UL)
#define EXMC_NFC_CMD_COPYBACK_READ_1ST (0x00UL)
#define EXMC_NFC_CMD_COPYBACK_READ_2ND (0x35UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_1ST (0x05UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_2ND (0xE0UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_1ST (0x06UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_2ND (0xE0UL)
#define EXMC_NFC_CMD_RD_CACHE_RANDOM_1ST (0x00UL)
#define EXMC_NFC_CMD_RD_CACHE_RANDOM_2ND (0x31UL)
#define EXMC_NFC_CMD_CALCULATE_ECC (0x23UL)
#define EXMC_NFC_CMD_RD_CACHE_SEQ (0x31UL)
#define EXMC_NFC_CMD_RD_CACHE_END (0x3FUL)
#define EXMC_NFC_CMD_BLK_ERASE_1ST (0x60UL)
#define EXMC_NFC_CMD_BLK_ERASE_2ND (0xD0UL)
#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_1ST (0x60UL)
#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_2ND (0xD1UL)
#define EXMC_NFC_CMD_RD_STATUS (0x70UL)
#define EXMC_NFC_CMD_RD_STATUS_ENHANCED (0x78UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_2ND (0x10UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_2ND (0x11UL)
#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_2ND (0x15UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_1ST (0x85UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_2ND (0x10UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_1ST (0x85UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_2ND (0x11UL)
#define EXMC_NFC_CMD_CHANGE_WR_COL (0x85UL)
#define EXMC_NFC_CMD_CHANGE_ROW_ADDR (0x85UL)
#define EXMC_NFC_CMD_RD_ID (0x90UL)
#define EXMC_NFC_CMD_RD_PARAMETER_PAGE (0xECUL)
#define EXMC_NFC_CMD_RD_UNIQUE_ID (0xEDUL)
#define EXMC_NFC_CMD_GET_FEATURES (0xEEUL)
#define EXMC_NFC_CMD_SET_FEATURES (0xEFUL)
#define EXMC_NFC_CMD_RST_LUN (0xFAUL)
#define EXMC_NFC_CMD_ASYNCHRONOUS_RST (0xFCUL)
#define EXMC_NFC_CMD_DESELECT_CHIP (0xFEUL)
#define EXMC_NFC_CMD_RESET (0xFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_NFC_Global_Functions
* @{
*/
/**
* @brief Set EXMC_NFC command register value.
* @param [in] u32Value The combination value of command @ref EXMC_NFC_Memory_Command and arguments.
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteCmdReg(uint32_t u32Value)
{
WRITE_REG32(CM_NFC->CMDR, u32Value);
}
/**
* @brief Set EXMC_NFC Index register value.
* @param [in] u32Value The value of NFC_IDXR0.
* This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteIDXR0(uint32_t u32Value)
{
WRITE_REG32(CM_NFC->IDXR0, u32Value);
}
/**
* @brief Set EXMC_NFC Index register value.
* @param [in] u8Value The value of NFC_IDXR1.
* This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteIDXR1(uint8_t u8Value)
{
WRITE_REG32(CM_NFC->IDXR1, u8Value);
}
/**
* @brief De-select NFC bank.
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_DeselectChip(void)
{
WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP);
}
/**
* @brief Get the 4BIT ECC error section.
* @param None
* @retval The 4BIT ECC error section
*/
__STATIC_INLINE uint16_t EXMC_NFC_Get4BitEccErrSection(void)
{
return (uint16_t)READ_REG32(CM_NFC->ECC_STAT);
}
/* Initialization and configuration EXMC_NFC functions */
int32_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcNfcInit);
int32_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcNfcInit);
void EXMC_NFC_DeInit(void);
void EXMC_NFC_Cmd(en_functional_state_t enNewState);
void EXMC_NFC_EccCmd(en_functional_state_t enNewState);
void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState);
void EXMC_NFC_IntCmd(uint16_t u16IntType, en_functional_state_t enNewState);
en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag);
void EXMC_NFC_ClearStatus(uint32_t u32Flag);
en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag);
uint32_t EXMC_NFC_Get1BitEccResult(uint32_t u32Section);
uint32_t EXMC_NFC_Get1BitEccErrBitLocation(uint32_t u32Section);
uint32_t EXMC_NFC_Get1BitEccErrByteLocation(uint32_t u32Section);
void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData);
void EXMC_NFC_SetEccMode(uint32_t u32EccMode);
int32_t EXMC_NFC_GetSyndrome(uint32_t u32Section, uint16_t au16Synd[], uint8_t u8Len);
/* EXMC_NFC command functions */
uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank);
uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank, uint32_t u32RowAddr);
int32_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout);
int32_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout);
int32_t EXMC_NFC_ResetLun(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout);
int32_t EXMC_NFC_ReadId(uint32_t u32Bank, uint32_t u32IdAddr,
uint8_t au8DevId[], uint32_t u32NumBytes, uint32_t u32Timeout);
int32_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank, uint32_t au32UniqueId[], uint8_t u8NumWords, uint32_t u32Timeout);
int32_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank,
uint32_t au32Data[], uint16_t u16NumWords, uint32_t u32Timeout);
int32_t EXMC_NFC_SetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr,
const uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout);
int32_t EXMC_NFC_GetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr,
uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout);
int32_t EXMC_NFC_EraseBlock(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout);
int32_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank, uint32_t u32Page, uint8_t *pu8Data,
uint32_t u32NumBytes, uint32_t u32Timeout);
int32_t EXMC_NFC_WritePageMeta(uint32_t u32Bank, uint32_t u32Page,
const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout);
int32_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank, uint32_t u32Page,
uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout);
int32_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank, uint32_t u32Page,
const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout);
/**
* @}
*/
#endif /* LL_NFC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_NFC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_ots.h
* @brief This file contains all the functions prototypes of the OTS driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_OTS_H__
#define __HC32_LL_OTS_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_OTS
* @{
*/
#if (LL_OTS_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup OTS_Global_Types OTS Global Types
* @{
*/
/**
* @brief Conditions of default parameters(slope K and offset M).
* @note Paramter 'u8T1' CANNOT equal to parameter 'u8T2'.
*/
typedef struct {
uint16_t u16ClockFreq; /*!< Frequency(MHz) of clock sources that OTS is going to use. */
uint8_t u8T1; /*!< Temperature value T1 for the default parameter.
This parameter can be a value of @ref OTS_Param_Temp_Cond */
uint8_t u8T2; /*!< Temperature value T2 for the default parameter.
This parameter can be a value of @ref OTS_Param_Temp_Cond */
} stc_para_temp_cond_t;
/**
* @brief OTS initialization structure.
*/
typedef struct {
uint16_t u16ClockSrc; /*!< Specifies clock source for OTS.
This parameter can be a value of @ref OTS_Clock_Source */
uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature).
This parameter can be a value of @ref OTS_Auto_Off_En */
float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment).
If you want to use the default parameters(slope K and offset M),
specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment).
If you want to use the default parameters(slope K and offset M),
specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
stc_para_temp_cond_t stcParaCond; /*!< Specifies the temperature conditions of the default parameters(slope K and offset M) if you
want to use the default parameters. */
} stc_ots_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup OTS_Global_Macros OTS Global Macros
* @{
*/
/**
* @defgroup OTS_Clock_Source OTS Clock Source
* @{
*/
#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */
#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */
/**
* @}
*/
/**
* @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control
* @{
*/
#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */
#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */
/**
* @}
*/
/**
* @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition
* @{
*/
#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */
#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */
#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup OTS_Global_Functions
* @{
*/
/**
* @brief Start OTS.
* @param None
* @retval None
*/
__STATIC_INLINE void OTS_Start(void)
{
WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U);
}
/**
* @brief Stop OTS.
* @param None
* @retval None
*/
__STATIC_INLINE void OTS_Stop(void)
{
WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U);
}
int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit);
int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit);
void OTS_DeInit(void);
int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
void OTS_IntCmd(en_functional_state_t enNewState);
int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2,
uint16_t *pu16Ecr, float32_t *pf32A,
uint32_t u32Timeout);
float32_t OTS_CalculateTemp(void);
/**
* @}
*/
#endif /* LL_OTS_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_OTS_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_pwc.h
* @brief This file contains all the functions prototypes of the PWC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_PWC_H__
#define __HC32_LL_PWC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_PWC
* @{
*/
#if (LL_PWC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup PWC_Global_Types PWC Global Types
* @{
*/
/**
* @brief PWC LVD Init
*/
typedef struct {
uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */
uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */
uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */
uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */
uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */
uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */
uint32_t u32TriggerEdge; /*!< LVD trigger setting, @ref PWC_LVD_TRIG_Sel for details */
} stc_pwc_lvd_init_t;
/**
* @brief PWC LVD Init
*/
typedef struct {
uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */
uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */
uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */
} stc_pwc_pd_mode_config_t;
/**
* @brief PWC Stop mode Init
*/
typedef struct {
uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode,
@ref PWC_STOP_CLK_Sel for details. */
uint8_t u8StopDrv; /*!< Stop mode drive capacity,
@ref PWC_STOP_DRV_Sel for details. */
uint16_t u16ExBusHold; /*!< Expos status in stop mode,
@ref PWC_STOP_EXBUS_Sel for details. */
uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode,
@ref STOP_FLASH_WAIT_Sel for details. */
} stc_pwc_stop_mode_config_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup PWC_Global_Macros PWC Global Macros
* @{
*/
/**
* @defgroup PWC_PDMode_Sel Power down mode selection
* @{
*/
#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */
#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */
#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */
#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */
/**
* @}
*/
/**
* @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode
* @{
*/
#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */
#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */
#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */
/**
* @}
*/
/**
* @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode
* @{
*/
#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */
#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */
/**
* @}
*/
/**
* @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode
* @{
*/
#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */
#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode
* @{
*/
#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */
#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode
* @{
*/
#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */
#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode
* @{
*/
#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */
#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup PWC_RAM_Config Operating mode for RAM Config
* @{
*/
#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */
#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */
/**
* @}
*/
/**
* @defgroup PWC_PD_Periph_Ram Peripheral ram to power down
* @{
*/
#define PWC_RAM_PD_CAN1 (PWC_PRAMLPC_PRAMPDC0)
#define PWC_RAM_PD_CAN2 (PWC_PRAMLPC_PRAMPDC1)
#define PWC_RAM_PD_CACHE (PWC_PRAMLPC_PRAMPDC2)
#define PWC_RAM_PD_USBFS (PWC_PRAMLPC_PRAMPDC3)
#define PWC_RAM_PD_USBHS (PWC_PRAMLPC_PRAMPDC4)
#define PWC_RAM_PD_ETHERTX (PWC_PRAMLPC_PRAMPDC5)
#define PWC_RAM_PD_ETHERRX (PWC_PRAMLPC_PRAMPDC6)
#define PWC_RAM_PD_SDIO1 (PWC_PRAMLPC_PRAMPDC7)
#define PWC_RAM_PD_SDIO2 (PWC_PRAMLPC_PRAMPDC8)
#define PWC_RAM_PD_NFC (PWC_PRAMLPC_PRAMPDC9)
#define PWC_RAM_PD_ALL (0x3FFU)
/**
* @}
*/
/**
* @defgroup PWC_PD_Ram Peripheral ram to power down
* @{
*/
#define PWC_RAM_PD_SRAM1_1 (PWC_RAMPC0_RAMPDC0) /*< 0x20000000 ~ 0x2000FFFF */
#define PWC_RAM_PD_SRAM1_2 (PWC_RAMPC0_RAMPDC1) /*< 0x20010000 ~ 0x2001FFFF */
#define PWC_RAM_PD_SRAM2_1 (PWC_RAMPC0_RAMPDC2) /*< 0x20020000 ~ 0x2002FFFF */
#define PWC_RAM_PD_SRAM2_2 (PWC_RAMPC0_RAMPDC3) /*< 0x20030000 ~ 0x2003FFFF */
#define PWC_RAM_PD_SRAM3_1 (PWC_RAMPC0_RAMPDC4) /*< 0x20040000 ~ 0x2004FFFF */
#define PWC_RAM_PD_SRAM3_2 (PWC_RAMPC0_RAMPDC5) /*< 0x20050000 ~ 0x20057FFF */
#define PWC_RAM_PD_SRAM4 (PWC_RAMPC0_RAMPDC6) /*< 0x20058000 ~ 0x2005FFFF */
#define PWC_RAM_PD_SRAMH_1 (PWC_RAMPC0_RAMPDC7) /*< 0x1FFE0000 ~ 0x1FFE7FFF */
#define PWC_RAM_PD_SRAMH_2 (PWC_RAMPC0_RAMPDC8) /*< 0x1FFE8000 ~ 0x1FFEFFFF */
#define PWC_RAM_PD_SRAMH_3 (PWC_RAMPC0_RAMPDC9) /*< 0x1FFF0000 ~ 0x1FFF7FFF */
#define PWC_RAM_PD_SRAMH_4 (PWC_RAMPC0_RAMPDC10) /*< 0x1FFF8000 ~ 0x1FFFFFFF */
/**
* @}
*/
/**
* @defgroup PWC_LVD_Channel PWC LVD channel
* @{
*/
#define PWC_LVD_CH1 (0x00U)
#define PWC_LVD_CH2 (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_LVD_Config PWC LVD Config
* @{
*/
#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN)
#define PWC_LVD_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select
* @{
*/
#define PWC_LVD_EXP_TYPE_NONE (0x00U)
#define PWC_LVD_EXP_TYPE_INT (0x0101U)
#define PWC_LVD_EXP_TYPE_NMI (0x0001U)
#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)
/**
* @}
*/
/**
* @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config
* @{
*/
#define PWC_LVD_CMP_OFF (0x00U)
#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE)
/**
* @}
*/
/**
* @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF
* @{
*/
#define PWC_LVD_FILTER_ON (0x00U)
#define PWC_LVD_FILTER_OFF (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability
* @note modified this value must when PWC_LVD_FILTER_OFF
* @{
*/
#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */
#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */
#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */
#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */
/**
* @}
*/
/**
* @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage
* @{
* @note | HC32F472 || HC32F451,HC32F452 || || ||
* | HC32F4A0 || HC32F460 || HC32M423/HC32M424 || HC32F120/HC32M120/HC32F160 ||
* | LVD1 | LVD2 || LVD1 | LVD2 || LVD1 | LVD2 || LVD ||
* LVL0 | 2.0V | 2.1V || 2.0V | 2.1V || 4.29V ~ 4.39V || 3.92V ~ 4.07V ||
* LVL1 | 2.1V | 2.3V || 2.1V | 2.3V || 4.14V ~ 4.23V || 3.67V ~ 3.77V ||
* LVL2 | 2.3V | 2.5V || 2.3V | 2.5V || 4.02V ~ 4.14V || 3.06V ~ 3.15V ||
* LVL3 | 2.5V | 2.6V || 2.5V | 2.6V || 3.84V ~ 3.96V || 2.96V ~ 3.04V ||
* LVL4 | 2.6V | 2.7V || 2.6V | 2.6V || 3.10V ~ 3.20V || 2.86V ~ 2.94V ||
* LVL5 | 2.7V | 2.8V || 2.6V | 2.8V || 3.00V ~ 3.09V || 2.75V ~ 2.83V ||
* LVL6 | 2.8V | 2.9V || 2.8V | 2.9V || 2.90V ~ 2.99V || 2.65V ~ 2.73V ||
* LVL7 | 2.9V | --- || 2.9V | --- || 2.79V ~ 2.87V || 2.55V ~ 2.63V ||
* LVL8 | --- | --- || --- | --- || 2.68V ~ 2.75V || 2.45V ~ 2.52V ||
* LVL9 | --- | --- || --- | --- || 2.34V ~ 2.41V || 2.04V ~ 2.11V ||
* LVL10 | --- | --- || --- | --- || 2.14V ~ 2.21V || 1.94V ~ 2.00V ||
* LVL11 | --- | --- || --- | --- || 1.94V ~ 2.01V || 1.84V ~ 1.90V ||
* LVL12 | --- | --- || --- | --- || 1.84V ~ 1.90V || ------------- ||
* EXVCC | --- | EXVCC || --- | EXVC C || ---- | EXVCC || EXVCC ||
*/
#define PWC_LVD_THRESHOLD_LVL0 (0x00U)
#define PWC_LVD_THRESHOLD_LVL1 (0x01U)
#define PWC_LVD_THRESHOLD_LVL2 (0x02U)
#define PWC_LVD_THRESHOLD_LVL3 (0x03U)
#define PWC_LVD_THRESHOLD_LVL4 (0x04U)
#define PWC_LVD_THRESHOLD_LVL5 (0x05U)
#define PWC_LVD_THRESHOLD_LVL6 (0x06U)
#define PWC_LVD_THRESHOLD_LVL7 (0x07U)
#define PWC_LVD_EXTVCC (0x07U)
/**
* @}
*/
/**
* @defgroup PWC_LVD_TRIG_Sel LVD trigger setting
* @{
*/
#define PWC_LVD_TRIG_FALLING (0x00UL << PWC_PVDICR_PVD1EDGS_POS)
#define PWC_LVD_TRIG_RISING (0x01UL << PWC_PVDICR_PVD1EDGS_POS)
#define PWC_LVD_TRIG_BOTH (0x02UL << PWC_PVDICR_PVD1EDGS_POS)
/**
* @}
*/
/**
* @defgroup PWC_LVD_Flag LVD flag
* @{
*/
#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */
#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */
#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */
#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection
* @{
*/
#define PWC_PD_WKUP0_POS (0U)
#define PWC_PD_WKUP1_POS (8U)
#define PWC_PD_WKUP2_POS (16U)
#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS)
#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS)
#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS)
#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS)
#define PWC_PD_WKUP_NMI (PWC_PDWKE2_NMIWKE << PWC_PD_WKUP2_POS)
#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS)
#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS)
#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge.
* @{
*/
#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS)
#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS)
#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS)
#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS)
#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS)
#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS)
#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \
PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection
* @{
*/
#define PWC_PD_WKUP_TRIG_FALLING (0x00U)
#define PWC_PD_WKUP_TRIG_RISING (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection
* @{
*/
#define PWC_PD_WKUP_FLAG0_POS (0U)
#define PWC_PD_WKUP_FLAG1_POS (8U)
#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS)
#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS)
#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS)
#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS)
#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \
PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \
PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | PWC_PD_WKUP_FLAG_WKTM)
/**
* @}
*/
/**
* @defgroup PWC_Monitor_Power PWC Power Monitor voltage definition
* @{
*/
#define PWC_PWR_MON_IREF (0x00U) /*!< Internal reference voltage */
#define PWC_PWR_MON_VBAT_DIV2 (PWC_PWRC4_ADBUFS) /*!< 1/2 VBAT voltage */
/**
* @}
*/
/**
* @defgroup PWC_VBAT_Reference_Voltage PWC VBAT Reference Voltage
* @{
*/
#define PWC_VBAT_REF_VOL_1P8V (0x00U) /*!< Vbat reference voltage is 1.8V */
#define PWC_VBAT_REF_VOL_2P1V (0x01U) /*!< Vbat reference voltage is 2.1V */
/**
* @}
*/
/**
* @defgroup PWC_BACKUP_RAM_Flag PWC Backup RAM Flag
* @{
*/
#define PWC_BACKUP_RAM_FLAG_RAMPDF (PWC_VBATCR_RAMPDF) /*!< Backup RAM power down flag */
#define PWC_BACKUP_RAM_FLAG_RAMVALID (PWC_VBATCR_RAMVALID) /*!< Backup RAM read/write flag */
/**
* @}
*/
/**
* @defgroup PWC_WKT_State PWC WKT State
* @{
*/
#define PWC_WKT_OFF (0x00U)
#define PWC_WKT_ON (PWC_WKTC2_WKTCE)
/**
* @}
*/
/**
* @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source
* @{
*/
#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTC2_WKCKS_POS)) /*!< 64Hz Clock */
#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTC2_WKCKS_POS)) /*!< XTAL32 Clock */
#define PWC_WKT_CLK_SRC_RTCLRC ((0x02U << PWC_WKTC2_WKCKS_POS)) /*!< RTCLRC Clock */
/**
* @}
*/
/**
* @defgroup PWC_Ldo_Sel PWC LDO Selection
* @{
*/
#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD)
#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD)
#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL)
/**
* @}
*/
/**
* @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code.
* @brief Lock/unlock Code for each module
* PWC_UNLOCK_CODE0:
* Below registers are locked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* PWC_UNLOCK_CODE1:
* Below registers are locked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are locked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is locked in RMU module.
* RSTF0
* PWC_UNLOCK_CODE2:
* Below registers are locked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @{
*/
#define PWC_WRITE_ENABLE (0xA500U)
#define PWC_UNLOCK_CODE0 (0xA501U)
#define PWC_UNLOCK_CODE1 (0xA502U)
#define PWC_UNLOCK_CODE2 (0xA508U)
/**
* @brief PWC FCG0 Unlock/Lock code
*/
#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL)
#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup PWC_Global_Functions
* @{
*/
/**
* @brief Lock PWC, CLK, RMU register.
* @param [in] u16Module Lock code for each module.
* @arg PWC_UNLOCK_CODE0
* @arg PWC_UNLOCK_CODE1
* @arg PWC_UNLOCK_CODE2
* @retval None
*/
__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module)
{
CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC)));
}
/**
* @brief Unlock PWC, CLK, RMU register.
* @param [in] u16Module Unlock code for each module.
* @arg PWC_UNLOCK_CODE0
* @arg PWC_UNLOCK_CODE1
* @arg PWC_UNLOCK_CODE2
* @retval None
*/
__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module)
{
SET_REG16_BIT(CM_PWC->FPRC, u16Module);
}
/**
* @brief Lock PWC_FCG0 register .
* @param None
* @retval None
*/
__STATIC_INLINE void PWC_FCG0_REG_Lock(void)
{
WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY);
}
/**
* @brief Unlock PWR_FCG0 register.
* @param None
* @retval None
* @note Call this function before FCG_Fcg0PeriphClockCmd()
*/
__STATIC_INLINE void PWC_FCG0_REG_Unlock(void)
{
WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY);
}
/* PWC PD Function */
void PWC_PD_Enter(void);
int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig);
int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig);
void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState);
void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge);
en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag);
void PWC_PD_ClearWakeupStatus(uint16_t u16Flag);
void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState);
void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState);
/* PWC WKTM Function */
void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal);
void PWC_WKT_SetCompareValue(uint16_t u16CmpVal);
uint16_t PWC_WKT_GetCompareValue(void);
void PWC_WKT_Cmd(en_functional_state_t enNewState);
en_flag_status_t PWC_WKT_GetStatus(void);
void PWC_WKT_ClearStatus(void);
void PWC_RamModeConfig(uint16_t u16Mode);
/* PWC Sleep Function */
void PWC_SLEEP_Enter(void);
/* PWC Stop Function */
void PWC_STOP_Enter(void);
int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig);
int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig);
void PWC_STOP_ClockSelect(uint8_t u8Clock);
void PWC_STOP_SetDrv(uint8_t u8StopDrv);
void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState);
void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold);
/* PWC Speed Switch Function */
int32_t PWC_HighSpeedToLowSpeed(void);
int32_t PWC_LowSpeedToHighSpeed(void);
/* PWC LDO Function */
void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState);
/* PWC LVD Function, LVD for PVD while HC32F460, HC32F451, HC32F452 and HC32F4A0 */
int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit);
int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit);
void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState);
void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState);
void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState);
void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState);
void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock);
void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage);
void PWC_LVD_ClearStatus(uint8_t u8Flag);
en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag);
/* PWC Power Monitor Function */
void PWC_PowerMonitorCmd(en_functional_state_t enNewState);
void PWC_SetPowerMonitorVoltageSrc(uint8_t u8VoltageSrc);
/* PWC VBAT Function */
void PWC_VBAT_SetMonitorVoltage(uint8_t u8RefVoltage);
void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState);
en_flag_status_t PWC_VBAT_GetVoltageStatus(void);
void PWC_VBAT_VoltageDivMonitorCmd(en_functional_state_t enNewState);
void PWC_VBAT_Reset(void);
void PWC_VBAT_PowerCmd(en_functional_state_t enNewState);
/* PWC Backup RAM Function */
void PWC_BKR_PowerCmd(en_functional_state_t enNewState);
en_flag_status_t PWC_BKR_GetStatus(uint8_t u8Flag);
void PWC_BKR_Write(uint8_t u8RegNum, uint8_t u8RegVal);
uint8_t PWC_BKR_Read(uint8_t u8RegNum);
/* PWC RAM Function */
/**
* @}
*/
#endif /* LL_PWC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_PWC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,445 @@
/**
*******************************************************************************
* @file hc32_ll_qspi.h
* @brief This file contains all the functions prototypes of the QSPI driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_QSPI_H__
#define __HC32_LL_QSPI_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_QSPI
* @{
*/
#if (LL_QSPI_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup QSPI_Global_Types QSPI Global Types
* @{
*/
/**
* @brief QSPI initialization structure definition
*/
typedef struct {
uint32_t u32ClockDiv; /*!< Specifies the clock division.
This parameter can be a value of @ref QSPI_Clock_Division */
uint32_t u32SpiMode; /*!< Specifies the SPI mode.
This parameter can be a value of @ref QSPI_SPI_Mode */
uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode.
This parameter can be a value of @ref QSPI_Prefetch_Mode */
uint32_t u32ReadMode; /*!< Specifies the read mode.
This parameter can be a value of @ref QSPI_Read_Mode */
uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles.
This parameter can be a value of @ref QSPI_Dummy_Cycle */
uint32_t u32AddrWidth; /*!< Specifies the address width.
This parameter can be a value of @ref QSPI_Addr_Width */
uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup.
This parameter can be a value of @ref QSPI_QSSN_Setup_Time */
uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release.
This parameter can be a value of @ref QSPI_QSSN_Release_Time */
uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN.
This parameter can be a value of @ref QSPI_QSSN_Interval_Time */
} stc_qspi_init_t;
/**
* @brief QSPI Custom read mode structure definition
*/
typedef struct {
uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol.
This parameter can be a value of @ref QSPI_Instruction_Protocol */
uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol.
This parameter can be a value of @ref QSPI_Addr_Protocol */
uint32_t u32DataProtocol; /*!< Specifies the data stage protocol.
This parameter can be a value of @ref QSPI_Data_Protocol */
uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */
} stc_qspi_custom_mode_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup QSPI_Global_Macros QSPI Global Macros
* @{
*/
/* QSPI memory mapping base and end address */
#define QSPI_ROM_BASE (0x98000000UL)
#define QSPI_ROM_END (0x9BFFFFFFUL)
/**
* @defgroup QSPI_Clock_Division QSPI Clock Division
* @{
*/
#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */
#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */
#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */
#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */
#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */
#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */
#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */
#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */
#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */
#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */
#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */
#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */
#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */
#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */
#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */
#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */
#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */
#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */
#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */
#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */
#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */
#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */
#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */
#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */
#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */
#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */
#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */
#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */
#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */
#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */
#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */
#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */
#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */
#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */
#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */
#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */
#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */
#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */
#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */
#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */
#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */
#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */
#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */
#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */
#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */
#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */
#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */
#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */
#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */
#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */
#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */
#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */
#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */
#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */
#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */
#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */
#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */
#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */
#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */
#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */
#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */
#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */
#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */
/**
* @}
*/
/**
* @defgroup QSPI_SPI_Mode QSPI SPI Mode
* @{
*/
#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */
#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */
/**
* @}
*/
/**
* @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode
* @{
*/
#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */
#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */
#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */
/**
* @}
*/
/**
* @defgroup QSPI_Read_Mode QSPI Read Mode
* @{
*/
#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */
#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */
#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */
#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */
#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */
#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */
#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */
#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */
/**
* @}
*/
/**
* @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle
* @{
*/
#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */
#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */
#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */
#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */
#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */
#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */
#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */
#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */
#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */
#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */
#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */
#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */
#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
/**
* @}
*/
/**
* @defgroup QSPI_Addr_Width QSPI Address Width
* @{
*/
#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */
#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */
#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */
#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */
#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */
/**
* @}
*/
/**
* @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time
* @{
*/
#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */
#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */
/**
* @}
*/
/**
* @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time
* @{
*/
#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */
#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */
#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */
#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */
#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */
/**
* @}
*/
/**
* @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time
* @{
*/
#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */
#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */
/**
* @}
*/
/**
* @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol
* @{
*/
#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */
#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */
#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */
/**
* @}
*/
/**
* @defgroup QSPI_Addr_Protocol QSPI Address Protocol
* @{
*/
#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */
#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */
#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */
/**
* @}
*/
/**
* @defgroup QSPI_Data_Protocol QSPI Data Protocol
* @{
*/
#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */
#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */
#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */
/**
* @}
*/
/**
* @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level
* @{
*/
#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */
#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */
/**
* @}
*/
/**
* @defgroup QSPI_Status_Flag QSPI Status Flag
* @{
*/
#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */
#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */
#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */
#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */
#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */
#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \
QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \
QSPI_FLAG_PREFETCH_STOP)
#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup QSPI_Global_Functions
* @{
*/
/**
* @brief Write data in direct communication mode.
* @param [in] u8Value Byte data.
* @retval None
*/
__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value)
{
WRITE_REG32(CM_QSPI->DCOM, u8Value);
}
/**
* @brief Read data in communication mode.
* @param None
* @retval uint8_t Byte data.
*/
__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void)
{
return (uint8_t)CM_QSPI->DCOM;
}
/* Initialization and configuration functions */
void QSPI_DeInit(void);
int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit);
int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit);
void QSPI_SetWpPinLevel(uint32_t u32Level);
void QSPI_SetPrefetchMode(uint32_t u32Mode);
void QSPI_SelectMemoryBlock(uint8_t u8Block);
void QSPI_SetReadMode(uint32_t u32Mode);
int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode);
void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState);
/* Transfer and receive data functions */
void QSPI_EnterDirectCommMode(void);
void QSPI_ExitDirectCommMode(void);
void QSPI_WriteDirectCommValue(uint8_t u8Value);
uint8_t QSPI_ReadDirectCommValue(void);
/* Interrupt and flag management functions */
uint8_t QSPI_GetPrefetchBufSize(void);
en_flag_status_t QSPI_GetStatus(uint32_t u32Flag);
void QSPI_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_QSPI_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_QSPI_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_rmu.h
* @brief This file contains all the functions prototypes of the RMU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_RMU_H__
#define __HC32_LL_RMU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_RMU
* @{
*/
#if (LL_RMU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup RMU_Global_Macros RMU Global Macros
* @{
*/
/**
* @defgroup RMU_ResetCause Rmu reset cause
* @{
*/
#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */
#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */
#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */
#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */
#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */
#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */
#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */
#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */
#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */
#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */
#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */
#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */
#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */
#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */
#define RMU_FLAG_CPU_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */
#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */
#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \
RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \
RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \
RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_CPU_LOCKUP | RMU_FLAG_MX)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup RMU_Global_Functions
* @{
*/
en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause);
void RMU_ClearStatus(void);
void RMU_CPULockUpCmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_RMU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_RMU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_rtc.h
* @brief This file contains all the functions prototypes of the RTC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_RTC_H__
#define __HC32_LL_RTC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_RTC
* @{
*/
#if (LL_RTC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup RTC_Global_Types RTC Global Types
* @{
*/
/**
* @brief RTC Init structure definition
*/
typedef struct {
uint8_t u8ClockSrc; /*!< Specifies the RTC clock source.
This parameter can be a value of @ref RTC_Clock_Source */
uint8_t u8HourFormat; /*!< Specifies the RTC hour format.
This parameter can be a value of @ref RTC_Hour_Format */
uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period.
This parameter can be a value of @ref RTC_Interrupt_Period */
uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation.
This parameter can be a value of @ref RTC_Clock_Compensation */
uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation.
This parameter can be a value of @ref RTC_Clock_Compensation_Mode */
uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation.
This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */
} stc_rtc_init_t;
/**
* @brief RTC Date structure definition
*/
typedef struct {
uint8_t u8Year; /*!< Specifies the RTC Year.
This parameter can be a number between Min_Data = 0 and Max_Data = 99 */
uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format).
This parameter can be a value of @ref RTC_Month */
uint8_t u8Day; /*!< Specifies the RTC Day.
This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t u8Weekday; /*!< Specifies the RTC Weekday.
This parameter can be a value of @ref RTC_Weekday */
} stc_rtc_date_t;
/**
* @brief RTC Time structure definition
*/
typedef struct {
uint8_t u8Hour; /*!< Specifies the RTC Hour.
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
uint8_t u8Minute; /*!< Specifies the RTC Minute.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8Second; /*!< Specifies the RTC Second.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode).
This parameter can be a value of @ref RTC_Hour12_AM_PM */
} stc_rtc_time_t;
/**
* @brief RTC Alarm structure definition
*/
typedef struct {
uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour.
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday.
This parameter can be a value of @ref RTC_Alarm_Weekday */
uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode).
This parameter can be a value of @ref RTC_Hour12_AM_PM */
} stc_rtc_alarm_t;
/**
* @brief RTC Intrusion structure definition
*/
typedef struct {
uint8_t u8Timestamp; /*!< Specifies the validity of RTC intrusion timestemp.
This parameter can be a value of @ref RTC_Intrusion_Timestamp */
uint8_t u8ResetBackupReg; /*!< Specifies the validity of RTC intrusion event that trigger backup registers reset.
This parameter can be a value of @ref RTC_Intrusion_Reset_Backup_Register */
uint8_t u8Filter; /*!< Specifies the RTC intrusion pin filter.
This parameter can be a value of @ref RTC_Intrusion_Filter */
uint8_t u8TriggerEdge; /*!< Specifies the RTC intrusion trigger edge.
This parameter can be a value of @ref RTC_Intrusion_Trigger_Edge */
} stc_rtc_intrusion_t;
/**
* @brief RTC Timestamp structure definition
*/
typedef struct {
stc_rtc_time_t stcTime; /*!< Specifies the RTC Intrusion Timestamp Time members */
uint8_t u8Month; /*!< Specifies the Month of RTC timestamp (in Decimal format).
This parameter can be a value of @ref RTC_Month */
uint8_t u8Day; /*!< Specifies the Day of RTC timestamp.
This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
} stc_rtc_timestamp_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup RTC_Global_Macros RTC Global Macros
* @{
*/
/**
* @defgroup RTC_Data_Format RTC Data Format
* @{
*/
#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */
#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */
/**
* @}
*/
/**
* @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion
* @{
*/
#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U))
#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU))
/**
* @}
*/
/**
* @defgroup RTC_Clock_Source RTC Clock Source
* @{
*/
#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */
#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */
/**
* @}
*/
/**
* @defgroup RTC_Hour_Format RTC Hour Format
* @{
*/
#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */
#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */
/**
* @}
*/
/**
* @defgroup RTC_Interrupt_Period RTC Interrupt Period
* @{
*/
#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */
#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */
#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */
#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */
#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */
#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */
#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */
/**
* @}
*/
/**
* @defgroup RTC_Clock_Compensation RTC Clock Compensation
* @{
*/
#define RTC_CLK_COMPEN_DISABLE (0U)
#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN)
/**
* @}
*/
/**
* @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode
* @{
*/
#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */
#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */
/**
* @}
*/
/**
* @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM
* @{
*/
#define RTC_HOUR_24H (0U) /*!< 24-hour format */
#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */
#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */
/**
* @}
*/
/**
* @defgroup RTC_Month RTC Month
* @{
*/
#define RTC_MONTH_JANUARY (0x01U)
#define RTC_MONTH_FEBRUARY (0x02U)
#define RTC_MONTH_MARCH (0x03U)
#define RTC_MONTH_APRIL (0x04U)
#define RTC_MONTH_MAY (0x05U)
#define RTC_MONTH_JUNE (0x06U)
#define RTC_MONTH_JULY (0x07U)
#define RTC_MONTH_AUGUST (0x08U)
#define RTC_MONTH_SEPTEMBER (0x09U)
#define RTC_MONTH_OCTOBER (0x0AU)
#define RTC_MONTH_NOVEMBER (0x0BU)
#define RTC_MONTH_DECEMBER (0x0CU)
/**
* @}
*/
/**
* @defgroup RTC_Weekday RTC Weekday
* @{
*/
#define RTC_WEEKDAY_SUNDAY (0x00U)
#define RTC_WEEKDAY_MONDAY (0x01U)
#define RTC_WEEKDAY_TUESDAY (0x02U)
#define RTC_WEEKDAY_WEDNESDAY (0x03U)
#define RTC_WEEKDAY_THURSDAY (0x04U)
#define RTC_WEEKDAY_FRIDAY (0x05U)
#define RTC_WEEKDAY_SATURDAY (0x06U)
/**
* @}
*/
/**
* @defgroup RTC_Alarm_Weekday RTC Alarm Weekday
* @{
*/
#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U)
#define RTC_ALARM_WEEKDAY_MONDAY (0x02U)
#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U)
#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U)
#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U)
#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U)
#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U)
#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Channel RTC Intrustion Channel
* @{
*/
#define RTC_INTRU_CH0 (0x00U)
#define RTC_INTRU_CH1 (0x04U)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Timestamp RTC Intrustion Timestamp
* @{
*/
#define RTC_INTRU_TS_DISABLE (0U)
#define RTC_INTRU_TS_ENABLE (RTC_TPCR0_TSTPE0)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Reset_Backup_Register RTC Intrusion Reset Backup Register
* @{
*/
#define RTC_INTRU_RST_BACKUP_REG_DISABLE (0U)
#define RTC_INTRU_RST_BACKUP_REG_ENABLE (RTC_TPCR0_TPRSTE0)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Filter RTC Intrusion Filter
* @{
*/
#define RTC_INTRU_FILTER_INVD (0U) /*!< Invalid filter function */
#define RTC_INTRU_FILTER_THREE_TIME (RTC_TPCR0_TPNF0_1) /*!< The filter detection is consistent with the timing clock for 3 times */
#define RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32 (RTC_TPCR0_TPNF0) /*!< The filter detection is consistent with the 32 frequency division of the timing clock for 3 times */
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Trigger_Edge RTC Intrusion Trigger Edge
* @{
*/
#define RTC_INTRU_TRIG_EDGE_NONE (0U) /*!< No detect */
#define RTC_INTRU_TRIG_EDGE_RISING (RTC_TPCR0_TPCT0_0) /*!< Detect rising edge */
#define RTC_INTRU_TRIG_EDGE_FALLING (RTC_TPCR0_TPCT0_1) /*!< Detect falling edge */
#define RTC_INTRU_TRIG_EDGE_RISING_FALLING (RTC_TPCR0_TPCT0) /*!< Detect rising and falling edge */
/**
* @}
*/
/**
* @defgroup RTC_Flag RTC Flag
* @{
*/
#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */
#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */
#define RTC_FLAG_PERIOD (RTC_CR2_PRDF) /*!< Period flag */
#define RTC_FLAG_INTRU_OVF ((uint32_t)RTC_TPSR_TPOVF << 16U) /*!< Intrusion overflow flag */
#define RTC_FLAG_INTRU_CH0 ((uint32_t)RTC_TPSR_TPF0 << 16U) /*!< RTCIC0 intrusion flag */
#define RTC_FLAG_INTRU_CH1 ((uint32_t)RTC_TPSR_TPF1 << 16U) /*!< RTCIC1 intrusion flag */
#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM | RTC_FLAG_PERIOD | \
RTC_FLAG_INTRU_OVF | RTC_FLAG_INTRU_CH0 | RTC_FLAG_INTRU_CH1)
#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM | RTC_FLAG_PERIOD | \
RTC_FLAG_INTRU_OVF | RTC_FLAG_INTRU_CH0 | RTC_FLAG_INTRU_CH1)
/**
* @}
*/
/**
* @defgroup RTC_Interrupt RTC Interrupt
* @{
*/
#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */
#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */
#define RTC_INT_INTRU_CH0 ((uint32_t)RTC_TPCR0_TPIE0 << 8U) /*!< RTCIC0 intrusion interrupt */
#define RTC_INT_INTRU_CH1 ((uint32_t)RTC_TPCR1_TPIE1 << 16U) /*!< RTCIC1 intrusion interrupt */
#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM | RTC_INT_INTRU_CH0 | RTC_INT_INTRU_CH1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup RTC_Global_Functions
* @{
*/
/* Initialization and configuration functions */
int32_t RTC_DeInit(void);
int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit);
int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit);
int32_t RTC_EnterRwMode(void);
int32_t RTC_ExitRwMode(void);
/* Control configuration */
int32_t RTC_ConfirmLPMCond(void);
void RTC_SetIntPeriod(uint8_t u8Period);
void RTC_SetClockSrc(uint8_t u8Src);
void RTC_SetClockCompenValue(uint16_t u16Value);
en_functional_state_t RTC_GetCounterState(void);
void RTC_Cmd(en_functional_state_t enNewState);
void RTC_LrcCmd(en_functional_state_t enNewState);
void RTC_OneHzOutputCmd(en_functional_state_t enNewState);
void RTC_ClockCompenCmd(en_functional_state_t enNewState);
/* Date and time functions */
int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
/* Alarm configuration functions */
int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
void RTC_AlarmCmd(en_functional_state_t enNewState);
/* Intrusion timestamp functions */
void RTC_INTRU_DeInit(uint8_t u8Ch);
int32_t RTC_INTRU_Init(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru);
int32_t RTC_INTRU_StructInit(stc_rtc_intrusion_t *pstcIntru);
int32_t RTC_INTRU_GetTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp);
void RTC_INTRU_Cmd(uint8_t u8Ch, en_functional_state_t enNewState);
/* Interrupt and flag management functions */
void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t RTC_GetStatus(uint32_t u32Flag);
void RTC_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_RTC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_RTC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_sdioc.h
* @brief This file contains all the functions prototypes of the SDIOC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_SDIOC_H__
#define __HC32_LL_SDIOC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_SDIOC
* @{
*/
#if (LL_SDIOC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SDIOC_Global_Types SDIOC Global Types
* @{
*/
/**
* @brief SDIOC Init structure definition
*/
typedef struct {
uint32_t u32Mode; /*!< Specifies the SDIOC work mode.
This parameter can be a value of @ref SDIOC_Mode */
uint8_t u8CardDetect; /*!< Specifies the SDIOC card detect way.
This parameter can be a value of @ref SDIOC_Card_Detect_Way */
uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode.
This parameter can be a value of @ref SDIOC_Speed_Mode */
uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width.
This parameter can be a value of @ref SDIOC_Bus_Width */
uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division.
This parameter can be a value of @ref SDIOC_Clock_Division */
} stc_sdioc_init_t;
/**
* @brief SDIOC Command Configuration structure definition
*/
typedef struct {
uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */
uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
uint16_t u16CmdType; /*!< Specifies the SDIOC command type.
This parameter can be a value of @ref SDIOC_Command_Type */
uint16_t u16DataLine; /*!< Specifies whether SDIOC uses data lines in current command.
This parameter can be a value of @ref SDIOC_Data_Line_Valid */
uint16_t u16ResponseType; /*!< Specifies the SDIOC response type.
This parameter can be a value of @ref SDIOC_Response_Type */
} stc_sdioc_cmd_config_t;
/**
* @brief SDIOC Data Configuration structure definition
*/
typedef struct {
uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size.
This parameter must be a number between Min_Data = 1 and Max_Data = 512 */
uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */
uint16_t u16TransDir; /*!< Specifies the SDIOC data transfer direction.
This parameter can be a value of @ref SDIOC_Transfer_Direction */
uint16_t u16AutoCmd12; /*!< Specifies the validity of the SDIOC Auto Send CMD12.
This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */
uint16_t u16TransMode; /*!< Specifies the SDIOC data transfer mode.
This parameter can be a value of @ref SDIOC_Transfer_Mode */
uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time.
This parameter can be a value of @ref SDIOC_Data_Timeout_Time */
} stc_sdioc_data_config_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SDIOC_Global_Macros SDIOC Global Macros
* @{
*/
/**
* @defgroup SDIOC_Mode SDIOC Mode
* @{
*/
#define SDIOC_MD_SD (0x00UL) /*!< SDIOCx selects SD mode */
#define SDIOC_MD_MMC (0x01UL) /*!< SDIOCx selects MMC mode */
/**
* @}
*/
/**
* @defgroup SDIOC_Card_Detect_Way SDIOC Card Detect Way
* @{
*/
#define SDIOC_CARD_DETECT_CD_PIN_LVL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */
#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */
/**
* @}
*/
/**
* @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level
* @{
*/
#define SDIOC_CARD_DETECT_TEST_LVL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */
#define SDIOC_CARD_DETECT_TEST_LVL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */
/**
* @}
*/
/**
* @defgroup SDIOC_Speed_Mode SDIOC Speed Mode
* @{
*/
#define SDIOC_SPEED_MD_NORMAL (0x00U) /*!< Normal speed mode */
#define SDIOC_SPEED_MD_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */
/**
* @}
*/
/**
* @defgroup SDIOC_Bus_Width SDIOC Bus Width
* @{
*/
#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */
#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */
#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */
/**
* @}
*/
/**
* @defgroup SDIOC_Clock_Division SDIOC Clock Division
* @{
*/
#define SDIOC_CLK_DIV1 (0x00U) /*!< CLK1/1 */
#define SDIOC_CLK_DIV2 (SDIOC_CLKCON_FS_0) /*!< CLK1/2 */
#define SDIOC_CLK_DIV4 (SDIOC_CLKCON_FS_1) /*!< CLK1/4 */
#define SDIOC_CLK_DIV8 (SDIOC_CLKCON_FS_2) /*!< CLK1/8 */
#define SDIOC_CLK_DIV16 (SDIOC_CLKCON_FS_3) /*!< CLK1/16 */
#define SDIOC_CLK_DIV32 (SDIOC_CLKCON_FS_4) /*!< CLK1/32 */
#define SDIOC_CLK_DIV64 (SDIOC_CLKCON_FS_5) /*!< CLK1/64 */
#define SDIOC_CLK_DIV128 (SDIOC_CLKCON_FS_6) /*!< CLK1/128 */
#define SDIOC_CLK_DIV256 (SDIOC_CLKCON_FS_7) /*!< CLK1/256 */
/**
* @}
*/
/**
* @defgroup SDIOC_Command_Type SDIOC Command Type
* @{
*/
#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */
#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */
#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */
#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */
/**
* @}
*/
/**
* @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid
* @{
*/
#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */
#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */
/**
* @}
*/
/**
* @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction
* @{
*/
#define SDIOC_TRANS_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */
#define SDIOC_TRANS_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */
/**
* @}
*/
/**
* @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12
* @{
*/
#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */
#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */
/**
* @}
*/
/**
* @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode
* @{
*/
#define SDIOC_TRANS_MD_SINGLE (0x00U) /*!< Single Block transfer */
#define SDIOC_TRANS_MD_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */
#define SDIOC_TRANS_MD_MULTI (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */
#define SDIOC_TRANS_MD_STOP_MULTI (0x8000U | SDIOC_TRANS_MD_MULTI) /*!< Stop Multiple Block transfer */
/**
* @}
*/
/**
* @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time
* @{
*/
#define SDIOC_DATA_TIMEOUT_CLK_2E13 (0x00U) /*!< Timeout time: CLK1*2^13 */
#define SDIOC_DATA_TIMEOUT_CLK_2E14 (0x01U) /*!< Timeout time: CLK1*2^14 */
#define SDIOC_DATA_TIMEOUT_CLK_2E15 (0x02U) /*!< Timeout time: CLK1*2^15 */
#define SDIOC_DATA_TIMEOUT_CLK_2E16 (0x03U) /*!< Timeout time: CLK1*2^16 */
#define SDIOC_DATA_TIMEOUT_CLK_2E17 (0x04U) /*!< Timeout time: CLK1*2^17 */
#define SDIOC_DATA_TIMEOUT_CLK_2E18 (0x05U) /*!< Timeout time: CLK1*2^18 */
#define SDIOC_DATA_TIMEOUT_CLK_2E19 (0x06U) /*!< Timeout time: CLK1*2^19 */
#define SDIOC_DATA_TIMEOUT_CLK_2E20 (0x07U) /*!< Timeout time: CLK1*2^20 */
#define SDIOC_DATA_TIMEOUT_CLK_2E21 (0x08U) /*!< Timeout time: CLK1*2^21 */
#define SDIOC_DATA_TIMEOUT_CLK_2E22 (0x09U) /*!< Timeout time: CLK1*2^22 */
#define SDIOC_DATA_TIMEOUT_CLK_2E23 (0x0AU) /*!< Timeout time: CLK1*2^23 */
#define SDIOC_DATA_TIMEOUT_CLK_2E24 (0x0BU) /*!< Timeout time: CLK1*2^24 */
#define SDIOC_DATA_TIMEOUT_CLK_2E25 (0x0CU) /*!< Timeout time: CLK1*2^25 */
#define SDIOC_DATA_TIMEOUT_CLK_2E26 (0x0DU) /*!< Timeout time: CLK1*2^26 */
#define SDIOC_DATA_TIMEOUT_CLK_2E27 (0x0EU) /*!< Timeout time: CLK1*2^27 */
/**
* @}
*/
/**
* @defgroup SDIOC_Response_Register SDIOC Response Register
* @{
*/
#define SDIOC_RESP_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */
#define SDIOC_RESP_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */
#define SDIOC_RESP_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */
#define SDIOC_RESP_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */
/**
* @}
*/
/**
* @defgroup SDIOC_Software_Reset_Type SDIOC Software Reset Type
* @{
*/
#define SDIOC_SW_RST_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */
#define SDIOC_SW_RST_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */
#define SDIOC_SW_RST_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */
/**
* @}
*/
/**
* @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency
* @{
*/
#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */
#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */
#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */
#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */
#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */
/**
* @}
*/
/**
* @defgroup SDIOC_Host_Flag SDIOC Host Flag
* @{
*/
#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */
#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */
#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */
#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */
#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */
#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */
#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */
#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */
#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */
#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */
#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */
#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */
#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */
#define SDIOC_HOST_FLAG_ALL (SDIOC_HOST_FLAG_CMDL | SDIOC_HOST_FLAG_DATL | SDIOC_HOST_FLAG_WPL | \
SDIOC_HOST_FLAG_CDL | SDIOC_HOST_FLAG_CSS | SDIOC_HOST_FLAG_CIN | \
SDIOC_HOST_FLAG_BRE | SDIOC_HOST_FLAG_BWE | SDIOC_HOST_FLAG_RTA | \
SDIOC_HOST_FLAG_WTA | SDIOC_HOST_FLAG_DA | SDIOC_HOST_FLAG_CID | \
SDIOC_HOST_FLAG_CIC)
/**
* @}
*/
/**
* @defgroup SDIOC_Interrupt_Flag SDIOC Interrupt Flag
* @{
*/
#define SDIOC_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */
#define SDIOC_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */
#define SDIOC_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */
#define SDIOC_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */
#define SDIOC_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */
#define SDIOC_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */
#define SDIOC_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */
#define SDIOC_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */
#define SDIOC_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */
#define SDIOC_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */
#define SDIOC_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */
#define SDIOC_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */
#define SDIOC_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */
#define SDIOC_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */
#define SDIOC_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */
#define SDIOC_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */
#define SDIOC_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */
#define SDIOC_INT_STATIC_FLAGS (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \
SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \
SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE | SDIOC_INT_FLAG_TC | \
SDIOC_INT_FLAG_CC)
#define SDIOC_NORMAL_INT_FLAG_ALL (SDIOC_INT_FLAG_EI | SDIOC_INT_FLAG_CINT | SDIOC_INT_FLAG_CRM | \
SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | SDIOC_INT_FLAG_BWR | \
SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | SDIOC_INT_FLAG_CC)
#define SDIOC_ERR_INT_FLAG_ALL (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \
SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \
SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE)
#define SDIOC_INT_FLAG_ALL (SDIOC_NORMAL_INT_FLAG_ALL | SDIOC_ERR_INT_FLAG_ALL)
#define SDIOC_INT_FLAG_CLR_ALL (SDIOC_INT_FLAG_CRM | SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | \
SDIOC_INT_FLAG_BWR | SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | \
SDIOC_INT_FLAG_CC | SDIOC_ERR_INT_FLAG_ALL)
/**
* @}
*/
/**
* @defgroup SDIOC_Interrupt SDIOC Interrupt
* @{
*/
#define SDIOC_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */
#define SDIOC_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */
#define SDIOC_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */
#define SDIOC_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */
#define SDIOC_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */
#define SDIOC_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */
#define SDIOC_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */
#define SDIOC_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */
#define SDIOC_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */
#define SDIOC_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */
#define SDIOC_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */
#define SDIOC_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */
#define SDIOC_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */
#define SDIOC_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */
#define SDIOC_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */
#define SDIOC_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */
#define SDIOC_NORMAL_INT_ALL (SDIOC_INT_CINTSEN | SDIOC_INT_CRMSEN | SDIOC_INT_CISTSEN | \
SDIOC_INT_BRRSEN | SDIOC_INT_BWRSEN | SDIOC_INT_BGESEN | \
SDIOC_INT_TCSEN | SDIOC_INT_CCSEN)
#define SDIOC_ERR_INT_ALL (SDIOC_INT_ACESEN | SDIOC_INT_DEBESEN | SDIOC_INT_DCESEN | \
SDIOC_INT_DTOESEN | SDIOC_INT_CIESEN | SDIOC_INT_CEBESEN | \
SDIOC_INT_CCESEN | SDIOC_INT_CTOESEN)
#define SDIOC_INT_ALL (SDIOC_NORMAL_INT_ALL | SDIOC_ERR_INT_ALL)
/**
* @}
*/
/**
* @defgroup SDIOC_Auto_CMD_Error_Flag SDIOC Auto CMD Error Flag
* @{
*/
#define SDIOC_AUTO_CMD_ERR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */
#define SDIOC_AUTO_CMD_ERR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */
#define SDIOC_AUTO_CMD_ERR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */
#define SDIOC_AUTO_CMD_ERR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */
#define SDIOC_AUTO_CMD_ERR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */
#define SDIOC_AUTO_CMD_ERR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */
#define SDIOC_AUTO_CMD_ERR_FLAG_ALL (SDIOC_AUTO_CMD_ERR_FLAG_CMDE | SDIOC_AUTO_CMD_ERR_FLAG_IE | \
SDIOC_AUTO_CMD_ERR_FLAG_EBE | SDIOC_AUTO_CMD_ERR_FLAG_CE | \
SDIOC_AUTO_CMD_ERR_FLAG_TOE | SDIOC_AUTO_CMD_ERR_FLAG_NE)
/**
* @}
*/
/**
* @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error
* @{
*/
#define SDIOC_FORCE_AUTO_CMD_ERR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */
#define SDIOC_FORCE_AUTO_CMD_ERR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */
#define SDIOC_FORCE_AUTO_CMD_ERR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */
#define SDIOC_FORCE_AUTO_CMD_ERR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */
#define SDIOC_FORCE_AUTO_CMD_ERR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */
#define SDIOC_FORCE_AUTO_CMD_ERR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */
#define SDIOC_FORCE_AUTO_CMD_ERR_ALL (SDIOC_FORCE_AUTO_CMD_ERR_FCMDE | SDIOC_FORCE_AUTO_CMD_ERR_FIE | \
SDIOC_FORCE_AUTO_CMD_ERR_FEBE | SDIOC_FORCE_AUTO_CMD_ERR_FCE | \
SDIOC_FORCE_AUTO_CMD_ERR_FTOE | SDIOC_FORCE_AUTO_CMD_ERR_FNE)
/**
* @}
*/
/**
* @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt
* @{
*/
#define SDIOC_FORCE_ERR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */
#define SDIOC_FORCE_ERR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */
#define SDIOC_FORCE_ERR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */
#define SDIOC_FORCE_ERR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */
#define SDIOC_FORCE_ERR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */
#define SDIOC_FORCE_ERR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */
#define SDIOC_FORCE_ERR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */
#define SDIOC_FORCE_ERR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */
#define SDIOC_FORCE_ERR_INT_ALL (SDIOC_FORCE_ERR_INT_FACE | SDIOC_FORCE_ERR_INT_FDEBE | \
SDIOC_FORCE_ERR_INT_FDCE | SDIOC_FORCE_ERR_INT_FDTOE | \
SDIOC_FORCE_ERR_INT_FCIE | SDIOC_FORCE_ERR_INT_FCEBE | \
SDIOC_FORCE_ERR_INT_FCCE | SDIOC_FORCE_ERR_INT_FCTOE)
/**
* @}
*/
/**
* @defgroup SDIOC_Response_Type SDIOC Response Type
* @{
*/
#define SDIOC_RESP_TYPE_NO (0x00U) /*!< No Response */
#define SDIOC_RESP_TYPE_R2 (SDIOC_CMD_RESTYP_0) /*!< Command Response 2 */
#define SDIOC_RESP_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */
#define SDIOC_RESP_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */
#define SDIOC_RESP_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */
/**
* @}
*/
#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */
#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */
#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \
operating condition register (OCR) content in the response on the CMD line. */
#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \
and asks the card whether card supports voltage. */
#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */
#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */
#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */
#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */
#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */
#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \
Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */
#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \
512 bytes in case of SDHC and SDXC. */
#define SDIOC_CMD18_READ_MULTI_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \
STOP_TRANSMISSION command. */
#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */
#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */
#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\
512 bytes in case of SDHC and SDXC. */
#define SDIOC_CMD25_WRITE_MULTI_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */
#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */
#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */
#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */
#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDIOC_CMD35_ERASE_GROUP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \
set by switch function command (CMD6). */
#define SDIOC_CMD36_ERASE_GROUP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \
Reserved for each command system set by switch function command (CMD6). */
#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */
#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */
#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */
#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \
the SET_BLOCK_LEN command. */
#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \
than a standard command. */
#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \
for general purpose/application specific commands. */
#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* @note SDIOC_CMD55_APP_CMD should be sent before sending these commands.
*/
#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \
widths are given in SCR register. */
#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */
#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \
32bit+CRC data block. */
#define SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT (23U) /*!< Set the number of write blocks to be pre-erased before writing (to be used for faster \
Multiple Block WR com-mand). */
#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \
send its operating condition register (OCR) content in the response on the CMD line. */
#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDIOC_ACMD52_RW_DIRECT (52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDIOC_ACMD53_RW_EXTENDED (53U) /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* @note SDIOC_CMD55_APP_CMD should be sent before sending these commands.
*/
#define SDIOC_ACMD43_GET_MKB (43U)
#define SDIOC_ACMD44_GET_MID (44U)
#define SDIOC_ACMD45_SET_CER_RN1 (45U)
#define SDIOC_ACMD46_GET_CER_RN2 (46U)
#define SDIOC_ACMD47_SET_CER_RES2 (47U)
#define SDIOC_ACMD48_GET_CER_RES1 (48U)
#define SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK (18U)
#define SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK (25U)
#define SDIOC_ACMD38_SECURE_ERASE (38U)
#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U)
#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U)
/**
* @defgroup SDMMC_Error_Code SDMMC Error Code
* @{
*/
#define SDMMC_ERR_NONE (0x00000000UL) /*!< No error */
#define SDMMC_ERR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */
#define SDMMC_ERR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */
#define SDMMC_ERR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \
number of transferred bytes does not match the block length */
#define SDMMC_ERR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */
#define SDMMC_ERR_WR_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */
#define SDMMC_ERR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \
or if there was an attempt to access a locked card */
#define SDMMC_ERR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */
#define SDMMC_ERR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */
#define SDMMC_ERR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERR_CC_ERR (0x00100000UL) /*!< Internal card controller error */
#define SDMMC_ERR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */
#define SDMMC_ERR_STREAM_RD_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERR_STREAM_WR_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */
#define SDMMC_ERR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */
#define SDMMC_ERR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */
#define SDMMC_ERR_ERASE_RST (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \
erase sequence command was received */
#define SDMMC_ERR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */
#define SDMMC_ERR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */
#define SDMMC_ERR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */
#define SDMMC_ERR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */
#define SDMMC_ERR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */
#define SDMMC_ERR_SWITCH_ERR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \
the SWITCH command */
#define SDMMC_ERR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */
#define SDMMC_ERR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */
#define SDMMC_ERR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */
#define SDMMC_ERR_INVD_VOLT (0x00000004UL) /*!< Error in case of invalid voltage range */
#define SDMMC_ERR_REQ_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */
#define SDMMC_ERR_UNSUPPORT_FEATURE (0x00000001UL) /*!< Error when feature is not insupported */
#define SDMMC_ERR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */
/**
* @}
*/
/**
* @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit
* @{
*/
#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U)
#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */
#define SDMMC_STATUS_CURR_STATE_POS (9U)
#define SDMMC_STATUS_CURR_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */
#define SDMMC_STATUS_RDY_FOR_DATA_POS (8U)
#define SDMMC_STATUS_RDY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */
#define SDMMC_STATUS_APP_CMD_POS (5U)
#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */
/**
* @}
*/
/**
* @defgroup SDMMC_SCR_Register SDMMC SCR Register
* @{
*/
#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL)
#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL)
#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL)
#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL)
#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL)
/**
* @}
*/
/**
* @defgroup SDMMC_OCR_Register SDMMC OCR Register
* @{
*/
#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL)
#define SDMMC_OCR_STD_CAPACITY (0x00000000UL)
/**
* @}
*/
/**
* @defgroup SDMMC_CSD_Register SDMMC CSD Register
* @{
*/
/* Command Class supported */
#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL)
/**
* @}
*/
/**
* @defgroup SDMMC_Common_Parameter SDMMC Common Parameter
* @{
*/
#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL)
#define SDMMC_MAX_VOLT_TRIAL (0x0000FFFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SDIOC_Global_Functions
* @{
*/
int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx);
int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit);
int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit);
int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type);
void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx);
uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx);
void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div);
int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div);
int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv);
en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx);
void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode);
void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth);
void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src);
void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level);
int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig);
int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig);
int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value);
int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig);
int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig);
int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len);
int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len);
void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx);
void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState);
en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType);
void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag);
void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event);
void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event);
/* SDMMC Commands management functions */
int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus);
int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_ACMD41_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD1_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus);
int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus);
/**
* @}
*/
#endif /* LL_SDIOC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_SDIOC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,396 @@
/**
*******************************************************************************
* @file hc32_ll_smc.h
* @brief This file contains all the functions prototypes of the EXMC_SMC
* (External Memory Controller: Static Memory Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_SMC_H__
#define __HC32_LL_SMC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_EXMC
* @{
*/
/**
* @addtogroup LL_SMC
* @{
*/
#if (LL_SMC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_SMC_Global_Types EXMC_SMC Global Types
* @{
*/
/**
* @brief EXMC_SMC Chip Configuration Structure definition
*/
typedef struct {
uint32_t u32ReadMode; /*!< Defines the read sync enable.
This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */
uint32_t u32WriteMode; /*!< Defines the write sync enable.
This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */
uint32_t u32ReadBurstLen; /*!< Defines the number of read data access.
This parameter can be a value of @ref EXMC_SMC_Memory_Read_Burst_Length. */
uint32_t u32WriteBurstLen; /*!< Defines the number of write data access.
This parameter can be a value of @ref EXMC_SMC_Memory_Write_Burst_Length. */
uint32_t u32MemoryWidth; /*!< Defines the SMC memory width.
This parameter can be a value of @ref EXMC_SMC_Memory_Width. */
uint32_t u32BAA; /*!< Defines the SMC BAA signal enable.
This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */
uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable.
This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */
uint32_t u32BLS; /*!< Defines the SMC BLS signal selection.
This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */
uint32_t u32AddrMatch; /*!< Defines the address match.
This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */
uint32_t u32AddrMask; /*!< Defines the address mask.
This parameter can be a value of @ref EXMC_SMC_Mask_Address. */
} stc_exmc_smc_chip_config_t;
/**
* @brief EXMC_SMC Timing Configuration Structure definition
*/
typedef struct {
uint8_t u8RC; /*!< Defines the RC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint8_t u8WC; /*!< Defines the WC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint8_t u8CEOE; /*!< Defines the CEOE in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8WP; /*!< Defines the WP in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8PC; /*!< Defines the PC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint8_t u8TR; /*!< Defines the TR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
} stc_exmc_smc_timing_config_t;
/**
* @brief EXMC_SMC Initialization Structure definition
*/
typedef struct {
stc_exmc_smc_chip_config_t stcChipConfig; /*!< SMC memory chip configure.
This structure details refer @ref stc_exmc_smc_chip_config_t. */
stc_exmc_smc_timing_config_t stcTimingConfig; /*!< SMC memory timing configure.
This structure details refer @ref stc_exmc_smc_timing_config_t. */
} stc_exmc_smc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_SMC_Global_Macros EXMC_SMC Global Macros
* @{
*/
/**
* @defgroup EXMC_SMC_Chip EXMC_SMC Chip
* @{
*/
#define EXMC_SMC_CHIP0 (0UL) /*!< Chip 0 */
#define EXMC_SMC_CHIP1 (1UL) /*!< Chip 1 */
#define EXMC_SMC_CHIP2 (2UL) /*!< Chip 2 */
#define EXMC_SMC_CHIP3 (3UL) /*!< Chip 3 */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Read_Mode EXMC_SMC Memory Read Mode
* @{
*/
#define EXMC_SMC_READ_ASYNC (0UL)
#define EXMC_SMC_READ_SYNC (SMC_CPCR_RSYN)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Write_Mode EXMC_SMC Memory Write Mode
* @{
*/
#define EXMC_SMC_WRITE_ASYNC (0UL)
#define EXMC_SMC_WRITE_SYNC (SMC_CPCR_WSYN)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Read_Burst_Length EXMC_SMC Memory Read Burst Length
* @{
*/
#define EXMC_SMC_READ_BURST_1BEAT (0UL)
#define EXMC_SMC_READ_BURST_4BEAT (1UL << SMC_CPCR_RBL_POS)
#define EXMC_SMC_READ_BURST_8BEAT (2UL << SMC_CPCR_RBL_POS)
#define EXMC_SMC_READ_BURST_16BEAT (3UL << SMC_CPCR_RBL_POS)
#define EXMC_SMC_READ_BURST_32BEAT (4UL << SMC_CPCR_RBL_POS)
#define EXMC_SMC_READ_BURST_CONTINUOUS (5UL << SMC_CPCR_RBL_POS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Write_Burst_Length EXMC_SMC Memory Write Burst Length
* @{
*/
#define EXMC_SMC_WRITE_BURST_1BEAT (0UL)
#define EXMC_SMC_WRITE_BURST_4BEAT (1UL << SMC_CPCR_WBL_POS)
#define EXMC_SMC_WRITE_BURST_8BEAT (2UL << SMC_CPCR_WBL_POS)
#define EXMC_SMC_WRITE_BURST_16BEAT (3UL << SMC_CPCR_WBL_POS)
#define EXMC_SMC_WRITE_BURST_32BEAT (4UL << SMC_CPCR_WBL_POS)
#define EXMC_SMC_WRITE_BURST_CONTINUOUS (5UL << SMC_CPCR_WBL_POS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Width EXMC_SMC Memory Width
* @{
*/
#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0)
#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_BAA_Port_Selection EXMC_SMC BAA Port Selection
* @{
*/
#define EXMC_SMC_BAA_PORT_DISABLE (0UL)
#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_ADV_Port_Selection EXMC_SMC ADV Port Selection
* @{
*/
#define EXMC_SMC_ADV_PORT_DISABLE (0UL)
#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC_SMC BLS Synchronization Selection
* @{
*/
#define EXMC_SMC_BLS_SYNC_CS (0UL)
#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Command EXMC_SMC Command
* @{
*/
#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */
#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */
#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_CRE_Polarity EXMC_SMC CRE Polarity
* @{
*/
#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */
#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Status EXMC_SMC Status
* @{
*/
#define EXMC_SMC_READY (0UL) /*!< SMC is ready */
#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Sample_Clock EXMC_SMC Sample Clock
* @{
*/
#define EXMC_SMC_SAMPLE_CLK_INTERNCLK (0UL) /*!< Internal EXCLK */
#define EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT (SMC_BACR_CKSEL_0) /*!< Invert internal EXCLK */
#define EXMC_SMC_SAMPLE_CLK_EXTCLK (SMC_BACR_CKSEL_1) /*!< External clock from EXMC_CLK port */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Mask_Address EXMC_SMC Mask Address
* @{
*/
#define EXMC_SMC_ADDR_MASK_16MB (0xFFUL)
#define EXMC_SMC_ADDR_MASK_32MB (0xFEUL)
#define EXMC_SMC_ADDR_MASK_64MB (0xFCUL)
#define EXMC_SMC_ADDR_MASK_128MB (0xF8UL)
#define EXMC_SMC_ADDR_MASK_256MB (0xF0UL)
#define EXMC_SMC_ADDR_MASK_512MB (0xE0UL)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Address_Space EXMC_SMC Address Space
* @{
*/
#define EXMC_SMC_ADDR_MIN (0x60000000UL)
#define EXMC_SMC_ADDR_MAX (0x7FFFFFFFUL)
/**
* @}
*/
/**
* @brief SMC device memory address shifting.
* @param [in] mem_base_addr SMC base address
* @param [in] mem_width SMC memory width
* @param [in] addr SMC device memory address
* @retval SMC device shifted address value
*/
#define SMC_ADDR_SHIFT(mem_base_addr, mem_width, addr) \
( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_addr) + ((addr) << 1U))) : \
(((mem_base_addr) + ((addr) << 2U)))))
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_SMC_Global_Functions
* @{
*/
/**
* @brief SMC entry low power state
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_SMC_EntryLowPower(void)
{
WRITE_REG32(CM_SMC->STCR0, SMC_STCR0_LPWIR);
}
/**
* @brief SMC exit low power state
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_SMC_ExitLowPower(void)
{
WRITE_REG32(CM_SMC->STCR1, SMC_STCR1_LPWOR);
}
/**
* @brief Get SMC status
* @param None
* @retval Returned value can be one of the macros group @ref EXMC_SMC_Status
* - EXMC_SMC_READY: SMC is ready
* - EXMC_SMC_LOWPOWER: SMC is low power
*/
__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void)
{
return READ_REG32_BIT(CM_SMC->STSR, SMC_STSR_STATUS);
}
/* Initialization and configuration EXMC_SMC functions */
int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit);
int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit);
void EXMC_SMC_DeInit(void);
void EXMC_SMC_Cmd(en_functional_state_t enNewState);
void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState);
void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock);
void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal);
void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr);
uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip);
uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip);
int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig);
int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig);
/**
* @}
*/
#endif /* LL_SMC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_SMC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_spi.h
* @brief This file contains all the functions prototypes of the SPI driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_SPI_H__
#define __HC32_LL_SPI_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_SPI
* @{
*/
#if (LL_SPI_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SPI_Global_Types SPI Global Types
* @{
*/
/**
* @brief Structure definition of SPI initialization.
*/
typedef struct {
uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode.
This parameter can be a value of @ref SPI_Wire_Mode_Define */
uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex.
This parameter can be a value of @ref SPI_Trans_Mode_Define */
uint32_t u32MasterSlave; /*!< SPI master/slave mode.
This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */
uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command.
This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */
uint32_t u32Parity; /*!< SPI parity check selection.
This parameter can be a value of @ref SPI_Parity_Check_Define */
uint32_t u32SpiMode; /*!< SPI mode.
This parameter can be a value of @ref SPI_Mode_Define */
uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler.
This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */
uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits.
This parameter can be a value of @ref SPI_Data_Size_Define */
uint32_t u32FirstBit; /*!< MSB first or LSB first.
This parameter can be a value of @ref SPI_First_Bit_Define */
uint32_t u32SuspendMode; /*!< SPI communication suspend function.
This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */
uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME.
This parameter can be a value of @ref SPI_Frame_Level_Define */
} stc_spi_init_t;
/**
* @brief Structure definition of SPI delay time configuration.
*/
typedef struct {
uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time)
This parameter can be a value of @ref SPI_Interval_Delay_Time_define */
uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time)
This parameter can be a value of @ref SPI_Release_Delay_Time_define */
uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define
This parameter can be a value of @ref SPI_Setup_Delay_Time_define */
} stc_spi_delay_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SPI_Global_Macros SPI Global Macros
* @{
*/
/**
* @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define
* @{
*/
#define SPI_4_WIRE (0UL)
#define SPI_3_WIRE (SPI_CR1_SPIMDS)
/**
* @}
*/
/**
* @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define
* @{
*/
#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */
#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */
/**
* @}
*/
/**
* @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define
* @{
*/
#define SPI_SLAVE (0UL)
#define SPI_MASTER (SPI_CR1_MSTR)
/**
* @}
*/
/**
* @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define
* @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode.
* @{
*/
#define SPI_LOOPBACK_INVD (0UL)
#define SPI_LOOPBACK_MOSI_INVT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */
#define SPI_LOOPBACK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */
/**
* @}
*/
/**
* @defgroup SPI_Int_Type_Define SPI Interrupt Type Define
* @{
*/
#define SPI_INT_ERR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */
#define SPI_INT_TX_BUF_EMPTY (SPI_CR1_TXIE)
#define SPI_INT_RX_BUF_FULL (SPI_CR1_RXIE)
#define SPI_INT_IDLE (SPI_CR1_IDIE)
#define SPI_IRQ_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE )
/**
* @}
*/
/**
* @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define
* @{
*/
#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */
#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */
/**
* @}
*/
/**
* @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define
* @{
*/
#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */
#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */
#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */
/**
* @}
*/
/**
* @defgroup SPI_SS_Pin_Define SPI SSx Define
* @{
*/
#define SPI_PIN_SS0 (SPI_CFG1_SS0PV)
#define SPI_PIN_SS1 (SPI_CFG1_SS1PV)
#define SPI_PIN_SS2 (SPI_CFG1_SS2PV)
#define SPI_PIN_SS3 (SPI_CFG1_SS3PV)
/**
* @}
*/
/**
* @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define
* @{
*/
#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */
#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */
/**
* @}
*/
/**
* @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF
* after enough data frame write to the SPI_DR
* @{
*/
#define SPI_1_FRAME (0UL) /*!< Data 1 frame */
#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/
#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/
#define SPI_4_FRAME (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/
/**
* @}
*/
/**
* @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define
* @{
*/
#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */
#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */
/**
* @}
*/
/**
* @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define
* @{
*/
#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS)
#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS)
/**
* @}
*/
/**
* @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define
* @{
*/
#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS)
#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS)
/**
* @}
*/
/**
* @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define
* @{
*/
#define SPI_COM_SUSP_FUNC_OFF (0UL)
#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE)
/**
* @}
*/
/**
* @defgroup SPI_Mode_Define SPI Mode Define
* @{
*/
#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \
MOSI/MISO pin data valid in odd edge, \
MOSI/MISO pin data change in even edge */
#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \
MOSI/MISO pin data valid in even edge, \
MOSI/MISO pin data change in odd edge */
#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \
MOSI/MISO pin data valid in odd edge, \
MOSI/MISO pin data change in even edge */
#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \
MOSI/MISO pin data valid in even edge, \
MOSI/MISO pin data change in odd edge */
/**
* @}
*/
/**
* @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define
* @{
*/
#define SPI_BR_CLK_DIV2 (0UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 2. */
#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 4. */
#define SPI_BR_CLK_DIV8 (2UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 8. */
#define SPI_BR_CLK_DIV16 (3UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 16. */
#define SPI_BR_CLK_DIV32 (4UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 32. */
#define SPI_BR_CLK_DIV64 (5UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 64. */
#define SPI_BR_CLK_DIV128 (6UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 128. */
#define SPI_BR_CLK_DIV256 (7UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 256. */
/**
* @}
*/
/**
* @defgroup SPI_Data_Size_Define SPI Data Size Define
* @{
*/
#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS)
#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS)
/**
* @}
*/
/**
* @defgroup SPI_First_Bit_Define SPI First Bit Define
* @{
*/
#define SPI_FIRST_MSB (0UL)
#define SPI_FIRST_LSB (SPI_CFG2_LSBF)
/**
* @}
*/
/**
* @defgroup SPI_State_Flag_Define SPI State Flag Define
* @{
*/
#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF)
#define SPI_FLAG_IDLE (SPI_SR_IDLNF)
#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF)
#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF)
#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF)
#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \
is copied into the shift register, but the transmission \
of the data bit may not have been completed. */
#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */
#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERLOAD)
#define SPI_FLAG_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \
SPI_FLAG_UNDERLOAD | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SPI_Global_Functions
* @{
*/
int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit);
int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit);
void SPI_DeInit(CM_SPI_TypeDef *SPIx);
void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState);
void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data);
uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx);
en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode);
void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState);
int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig);
void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin);
void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf);
int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig);
int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout);
int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout);
int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
/**
* @}
*/
#endif /* LL_SPI_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_SPI_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_sram.h
* @brief This file contains all the functions prototypes of the SRAM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_SRAM_H__
#define __HC32_LL_SRAM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_SRAM
* @{
*/
#if (LL_SRAM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SRAM_Global_Macros SRAM Global Macros
* @{
*/
/**
* @defgroup SRAM_Sel SRAM Selection
* @{
*/
/* SRAM selection */
#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFE0000~0x1FFFFFFF, 128KB */
#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB
SRAM2: 0x20020000~0x2003FFFF, 128KB
SRAM3: 0x20040000~0x20057FFF, 96KB */
#define SRAM_SRAM4 (1UL << 1U) /*!< SRAM4: 0x20058000~0x2005FFFF, 32KB */
#define SRAM_SRAMB (1UL << 3U) /*!< SRAMB: 0x200F0000~0x200F0FFF, 4KB */
#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB)
#define SRAM_ECC_SRAM4 (SRAM_SRAM4)
#define SRAM_ECC_SRAMB (SRAM_SRAMB)
/**
* @}
*/
/**
* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
* @{
*/
#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */
#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */
#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */
#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */
#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */
#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */
#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */
#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */
/**
* @}
*/
/**
* @defgroup SRAM_Err_Mode SRAM Error Mode
* @note Even-parity check error, ECC check error.
* @{
*/
#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurres while check error occurres. */
#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurres while check error occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_ECC_Mode SRAM ECC Mode
* @{
*/
#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */
#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres:
ECC error corrects.
No 1-bit-error status flag setting, no interrupt or reset.
When 2-bit error occurres:
ECC error detects.
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres:
ECC error corrects.
1-bit-error status flag sets, no interrupt or reset.
When 2-bit error occurres:
ECC error detects.
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurres:
ECC error corrects.
1-bit-error status flag sets and interrupt or reset occurres.
When 2-bit error occurres:
ECC error detects.
2-bit-error status flag sets and interrupt or reset occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag
* @{
*/
#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */
#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */
#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */
#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */
#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */
#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */
#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */
#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */
#define SRAM_FLAG_ALL (0x1FFUL)
/**
* @}
*/
/**
* @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key
* @{
*/
#define SRAM_REG_LOCK_KEY (0x76U)
#define SRAM_REG_UNLOCK_KEY (0x77U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SRAM_Global_Functions
* @{
*/
/**
* @brief Lock SRAM registers, write protect.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_REG_Lock(void)
{
WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY);
WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY);
}
/**
* @brief Unlock SRAM registers, write enable.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_REG_Unlock(void)
{
WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY);
WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY);
}
void SRAM_Init(void);
void SRAM_DeInit(void);
void SRAM_REG_Lock(void);
void SRAM_REG_Unlock(void);
void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode);
void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode);
en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
void SRAM_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_SRAM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_SRAM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_swdt.h
* @brief This file contains all the functions prototypes of the SWDT driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_SWDT_H__
#define __HC32_LL_SWDT_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_SWDT
* @{
*/
#if (LL_SWDT_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SWDT_Global_Types SWDT Global Types
* @{
*/
/**
* @brief SWDT Init structure definition
*/
typedef struct {
uint32_t u32CountPeriod; /*!< Specifies the counting period of SWDT.
This parameter can be a value of @ref SWDT_Count_Period */
uint32_t u32ClockDiv; /*!< Specifies the clock division factor of SWDT.
This parameter can be a value of @ref SWDT_Clock_Division */
uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of SWDT.
This parameter can be a value of @ref SWDT_Refresh_Range */
uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep/Stop Mode).
This parameter can be a value of @ref SWDT_LPM_Count */
uint32_t u32ExceptionType; /*!< Specifies the type of exception response for SWDT.
This parameter can be a value of @ref SWDT_Exception_Type */
} stc_swdt_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SWDT_Global_Macros SWDT Global Macros
* @{
*/
/**
* @defgroup SWDT_Count_Period SWDT Count Period
* @{
*/
#define SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
#define SWDT_CNT_PERIOD4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */
#define SWDT_CNT_PERIOD16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */
#define SWDT_CNT_PERIOD65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup SWDT_Clock_Division SWDT Clock Division
* @{
*/
#define SWDT_CLK_DIV1 (0UL) /*!< SWDTCLK/1 */
#define SWDT_CLK_DIV16 (0x04UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/16 */
#define SWDT_CLK_DIV32 (0x05UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/32 */
#define SWDT_CLK_DIV64 (0x06UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/64 */
#define SWDT_CLK_DIV128 (0x07UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/128 */
#define SWDT_CLK_DIV256 (0x08UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/256 */
#define SWDT_CLK_DIV2048 (0x0BUL << SWDT_CR_CKS_POS) /*!< SWDTCLK/2048 */
/**
* @}
*/
/**
* @defgroup SWDT_Refresh_Range SWDT Refresh Range
* @{
*/
#define SWDT_RANGE_0TO25PCT (0x01UL << SWDT_CR_WDPT_POS) /*!< 0%~25% */
#define SWDT_RANGE_25TO50PCT (0x02UL << SWDT_CR_WDPT_POS) /*!< 25%~50% */
#define SWDT_RANGE_0TO50PCT (0x03UL << SWDT_CR_WDPT_POS) /*!< 0%~50% */
#define SWDT_RANGE_50TO75PCT (0x04UL << SWDT_CR_WDPT_POS) /*!< 50%~75% */
#define SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */
#define SWDT_RANGE_25TO75PCT (0x06UL << SWDT_CR_WDPT_POS) /*!< 25%~75% */
#define SWDT_RANGE_0TO75PCT (0x07UL << SWDT_CR_WDPT_POS) /*!< 0%~75% */
#define SWDT_RANGE_75TO100PCT (0x08UL << SWDT_CR_WDPT_POS) /*!< 75%~100% */
#define SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */
#define SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << SWDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */
#define SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << SWDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */
#define SWDT_RANGE_50TO100PCT (0x0CUL << SWDT_CR_WDPT_POS) /*!< 50%~100% */
#define SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */
#define SWDT_RANGE_25TO100PCT (0x0EUL << SWDT_CR_WDPT_POS) /*!< 25%~100% */
#define SWDT_RANGE_0TO100PCT (0x0FUL << SWDT_CR_WDPT_POS) /*!< 0%~100% */
/**
* @}
*/
/**
* @defgroup SWDT_LPM_Count SWDT Low Power Mode Count
* @brief Counting control of SWDT in sleep/stop mode.
* @{
*/
#define SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */
#define SWDT_LPM_CNT_STOP (SWDT_CR_SLPOFF) /*!< Stop counting in sleep/stop mode */
/**
* @}
*/
/**
* @defgroup SWDT_Exception_Type SWDT Exception Type
* @brief Specifies the exception response when a refresh error or count overflow occurs.
* @{
*/
#define SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */
#define SWDT_EXP_TYPE_RST (SWDT_CR_ITS) /*!< SWDT trigger reset */
/**
* @}
*/
/**
* @defgroup SWDT_Flag SWDT Flag
* @{
*/
#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */
#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */
#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SWDT_Global_Functions
* @{
*/
/**
* @brief Get SWDT count value.
* @param None
* @retval uint16_t Count value
*/
__STATIC_INLINE uint16_t SWDT_GetCountValue(void)
{
return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT);
}
/* Initialization and configuration functions */
int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit);
void SWDT_FeedDog(void);
uint16_t SWDT_GetCountValue(void);
/* Flags management functions */
en_flag_status_t SWDT_GetStatus(uint32_t u32Flag);
int32_t SWDT_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_SWDT_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_SWDT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_tmr0.h
* @brief This file contains all the functions prototypes of the TMR0 driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TMR0_H__
#define __HC32_LL_TMR0_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TMR0
* @{
*/
#if (LL_TMR0_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR0_Global_Types TMR0 Global Types
* @{
*/
/**
* @brief TMR0 initialization structure definition
* @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT".
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel.
This parameter can be a value of @ref TMR0_Clock_Source */
uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel.
This parameter can be a value of @ref TMR0_Clock_Division */
uint32_t u32Func; /*!< Specifies the function of TMR0 channel.
This parameter can be a value of @ref TMR0_Function */
uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel.
This parameter can be a value of half-word */
} stc_tmr0_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR0_Global_Macros TMR0 Global Macros
* @{
*/
/**
* @defgroup TMR0_Channel TMR0 Channel
* @note TMR0 on the HC32F120,HC32F160 and HC32M120 chips is only "TMR0_CH_A".
* @{
*/
#define TMR0_CH_A (0UL)
#define TMR0_CH_B (1UL)
/**
* @}
*/
/**
* @defgroup TMR0_Clock_Source TMR0 Clock Source
* @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks.
* @{
*/
#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */
#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */
#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */
#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */
/**
* @}
*/
/**
* @defgroup TMR0_Clock_Division TMR0 Clock Division
* @{
*/
#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */
#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */
#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */
#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */
#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */
#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */
#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */
#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */
#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */
#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */
#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */
/**
* @}
*/
/**
* @defgroup TMR0_Function TMR0 Function
* @{
*/
#define TMR0_FUNC_CMP (0UL) /*!< Output comare function */
#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */
/**
* @}
*/
/**
* @defgroup TMR0_Interrupt TMR0 Interrupt
* @{
*/
#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA)
#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB)
#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B)
/**
* @}
*/
/**
* @defgroup TMR0_FLAG TMR0 Flag
* @{
*/
#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA)
#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB)
#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR0_Global_Functions
* @{
*/
/* Initialization functions */
void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x);
int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init);
int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init);
void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
/* Control configuration functions */
void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src);
void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div);
void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func);
/* Hardware trigger Functions */
void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
/* Interrupt and flag management functions */
void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_TMR0_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TMR0_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_tmr2.h
* @brief This file contains all the functions prototypes of the TMR2(Timer2)
* driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TMR2_H__
#define __HC32_LL_TMR2_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TMR2
* @{
*/
#if (LL_TMR2_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR2_Global_Types TMR2 Global Types
* @{
*/
/**
* @brief TMR2 PWM configuration structure.
*/
typedef struct {
uint32_t u32StartPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting start.
This parameter can be a value of @ref TMR2_PWM_Polarity */
uint32_t u32StopPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting stop.
This parameter can be a value of @ref TMR2_PWM_Polarity */
uint32_t u32CompareMatchPolarity; /*!< Specifies the polarity of PWM output when TMR2 counter matches the compare value.
This parameter can be a value of @ref TMR2_PWM_Polarity */
} stc_tmr2_pwm_init_t;
/**
* @brief TMR2 initialization structure.
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Specifies the clock source for TMR2 channel.
This parameter can be a value of @ref TMR2_Clock_Source */
uint32_t u32ClockDiv; /*!< Specifies the division of the clock source.
This parameter can be a value of @ref TMR2_Clock_Divider */
uint32_t u32Func; /*!< Specifies the function mode for TMR2 channel.
This parameter can be a value of @ref TMR2_Function */
uint32_t u32CompareValue; /*!< Specifies the compare value.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
} stc_tmr2_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR2_Global_Macros TMR2 Global Macros
* @{
*/
/**
* @defgroup TMR2_Channel TMR2 Channel
* @{
*/
#define TMR2_CH_A (0U) /*!< Channel A of TMR2. */
#define TMR2_CH_B (1U) /*!< Channel B of TMR2. */
/**
* @}
*/
/**
* @defgroup TMR2_Function TMR2 Function
* @{
*/
#define TMR2_FUNC_CMP (0x0U) /*!< The function of TMR2 channel is ouput compare. */
#define TMR2_FUNC_CAPT (TMR2_BCONR_CAPMDA) /*!< The function of TMR2 channel is input capture. */
/**
* @}
*/
/**
* @defgroup TMR2_Clock_Source TMR2 Clock Source
* @{
*/
#define TMR2_CLK_PCLK1 (0x0U) /*!< Synchronous clock source, PCLK1. */
#define TMR2_CLK_TRIG_RISING (TMR2_BCONR_SYNCLKA_0) /*!< Synchronous clock source, rising edge of TIM2_<t>_TRIGA/B.
One rising edge causes one count. */
#define TMR2_CLK_TRIG_FALLING (TMR2_BCONR_SYNCLKA_1) /*!< Synchronous clock source, falling edge of TIM2_<t>_TRIGA/B.
One falling edge causes one count. */
#define TMR2_CLK_EVT (TMR2_BCONR_SYNCLKA) /*!< Synchronous clock source, peripheral event. The event is specified by register TMR2_HTSSR.
One event causes one count. */
#define TMR2_CLK_TMR6_OVF (TMR2_BCONR_SYNCLKAT_0) /*!< Synchronous clock source, the event of counting overflow of TIMER6.
It is NOT need to set register TMR2_HTSSR. */
#define TMR2_CLK_TMR6_UDF (TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, the event of counting underflow of TIMER6.
It is NOT need to set register TMR2_HTSSR. */
#define TMR2_CLK_TMR6_OVF_UDF (TMR2_BCONR_SYNCLKAT_0 | \
TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, both overflow and underflow of TIMER6. */
#define TMR2_CLK_LRC (TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, LRC(32.768KHz). */
#define TMR2_CLK_XTAL32 (TMR2_BCONR_ASYNCLKA_0 | \
TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, XTAL32(32.768KHz). */
#define TMR2_CLK_PIN_CLK (TMR2_BCONR_ASYNCLKA_1 | \
TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, input from pin TIM2_<t>_CLKA/B. */
/**
* @}
*/
/**
* @defgroup TMR2_Clock_Divider TMR2 Clock Divider
* @{
*/
#define TMR2_CLK_DIV1 (0x0U) /*!< Clock source. */
#define TMR2_CLK_DIV2 (0x1UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 2. */
#define TMR2_CLK_DIV4 (0x2UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 4. */
#define TMR2_CLK_DIV8 (0x3UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 8. */
#define TMR2_CLK_DIV16 (0x4UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 16. */
#define TMR2_CLK_DIV32 (0x5UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 32. */
#define TMR2_CLK_DIV64 (0x6UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 64. */
#define TMR2_CLK_DIV128 (0x7UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 128. */
#define TMR2_CLK_DIV256 (0x8UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 256. */
#define TMR2_CLK_DIV512 (0x9UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 512. */
#define TMR2_CLK_DIV1024 (0xAUL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 1024. */
/**
* @}
*/
/**
* @defgroup TMR2_Interrupt_Type TMR2 Interrupt Type
* @{
*/
#define TMR2_INT_MATCH_CH_A (TMR2_ICONR_CMENA) /*!< TMR2 count match interrupt. */
#define TMR2_INT_OVF_CH_A (TMR2_ICONR_OVENA) /*!< TMR2 count overflow interrupt. */
#define TMR2_INT_MATCH_CH_B (TMR2_ICONR_CMENB) /*!< TMR2 count match interrupt. */
#define TMR2_INT_OVF_CH_B (TMR2_ICONR_OVENB) /*!< TMR2 count overflow interrupt. */
#define TMR2_INT_ALL (TMR2_INT_MATCH_CH_A | TMR2_INT_OVF_CH_A | \
TMR2_INT_MATCH_CH_B | TMR2_INT_OVF_CH_B)
/**
* @}
*/
/**
* @defgroup TMR2_Status_Flag TMR2 Status Flag
* @{
*/
#define TMR2_FLAG_MATCH_CH_A (TMR2_STFLR_CMFA) /*!< Counter match flag of channel A. */
#define TMR2_FLAG_OVF_CH_A (TMR2_STFLR_OVFA) /*!< Counter overflow flag channel A. */
#define TMR2_FLAG_MATCH_CH_B (TMR2_STFLR_CMFB) /*!< Counter match flag channel B. */
#define TMR2_FLAG_OVF_CH_B (TMR2_STFLR_OVFB) /*!< Counter overflow flag channel B. */
#define TMR2_FLAG_ALL (TMR2_FLAG_MATCH_CH_A | TMR2_FLAG_OVF_CH_A | \
TMR2_FLAG_MATCH_CH_B | TMR2_FLAG_OVF_CH_B)
/**
* @}
*/
/**
* @defgroup TMR2_Counter_State TMR2 Counter State
* @{
*/
#define TMR2_CNT_STAT_START (0U) /*!< Counter start counting. */
#define TMR2_CNT_STAT_STOP (1U) /*!< Counter stop counting. */
#define TMR2_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matchs the compare value. */
/**
* @}
*/
/**
* @defgroup TMR2_PWM_Polarity TMR2 PWM Polarity
* @{
*/
#define TMR2_PWM_LOW (0x0U) /*!< PWM output low. */
#define TMR2_PWM_HIGH (0x1U) /*!< PWM output high. */
#define TMR2_PWM_HOLD (0x2U) /*!< PWM output keeps the current polarity. */
#define TMR2_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */
/**
* @}
*/
/**
* @defgroup TMR2_Start_Condition TMR2 Start Condition
* @{
*/
#define TMR2_START_COND_INVD (0x0U) /*!< The start condition of TMR2 is INVALID. */
#define TMR2_START_COND_TRIG_RISING (TMR2_HCONR_HSTAA0) /*!< The start condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_START_COND_TRIG_FALLING (TMR2_HCONR_HSTAA1) /*!< The start condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_START_COND_EVT (TMR2_HCONR_HSTAA2) /*!< The start condition of TMR2 is the specified event occurred. */
#define TMR2_START_COND_ALL (TMR2_START_COND_TRIG_RISING | TMR2_START_COND_TRIG_FALLING | \
TMR2_START_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMR2_Stop_Condition TMR2 Stop Condition
* @{
*/
#define TMR2_STOP_COND_INVD (0x0U) /*!< The stop condition of TMR2 is INVALID. */
#define TMR2_STOP_COND_TRIG_RISING (TMR2_HCONR_HSTPA0) /*!< The stop condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_STOP_COND_TRIG_FALLING (TMR2_HCONR_HSTPA1) /*!< The stop condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_STOP_COND_EVT (TMR2_HCONR_HSTPA2) /*!< The stop condition of TMR2 is the specified event occurred. */
#define TMR2_STOP_COND_ALL (TMR2_STOP_COND_TRIG_RISING | TMR2_STOP_COND_TRIG_FALLING | \
TMR2_STOP_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMR2_Clear_Condition TMR2 Clear Condition
* @{
*/
#define TMR2_CLR_COND_INVD (0x0U) /*!< The clear condition of TMR2 is INVALID. */
#define TMR2_CLR_COND_TRIG_RISING (TMR2_HCONR_HCLEA0) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_CLR_COND_TRIG_FALLING (TMR2_HCONR_HCLEA1) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_CLR_COND_EVT (TMR2_HCONR_HCLEA2) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the specified event occurred. */
#define TMR2_CLR_COND_ALL (TMR2_CLR_COND_TRIG_RISING | TMR2_CLR_COND_TRIG_FALLING | \
TMR2_CLR_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMR2_Capture_Condition TMR2 Capture Condition
* @{
*/
#define TMR2_CAPT_COND_INVD (0x0U) /*!< The capture condition of TMR2 is INVALID. */
#define TMR2_CAPT_COND_TRIG_RISING (TMR2_HCONR_HICPA0) /*!< The capture condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_CAPT_COND_TRIG_FALLING (TMR2_HCONR_HICPA1) /*!< The capture condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_CAPT_COND_EVT (TMR2_HCONR_HICPA2) /*!< The capture condition of TMR2 is the specified event occurred. */
#define TMR2_CAPT_COND_ALL (TMR2_CAPT_COND_TRIG_RISING | TMR2_CAPT_COND_TRIG_FALLING | \
TMR2_CAPT_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMR2_Filter_Clock_Divider TMR2 Filter Clock Divider
* @{
*/
#define TMR2_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timer2 / 1 */
#define TMR2_FILTER_CLK_DIV4 (TMR2_PCONR_NOFICKA_0) /*!< The filter clock is the clock of timer2 / 4 */
#define TMR2_FILTER_CLK_DIV16 (TMR2_PCONR_NOFICKA_1) /*!< The filter clock is the clock of timer2 / 16 */
#define TMR2_FILTER_CLK_DIV64 (TMR2_PCONR_NOFICKA) /*!< The filter clock is the clock of timer2 / 64 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR2_Global_Functions
* @{
*/
int32_t TMR2_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_init_t *pstcTmr2Init);
int32_t TMR2_StructInit(stc_tmr2_init_t *pstcTmr2Init);
void TMR2_DeInit(CM_TMR2_TypeDef *TMR2x);
void TMR2_SetFunc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Func);
void TMR2_SetClockSrc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Src);
void TMR2_SetClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div);
int32_t TMR2_PWM_StructInit(stc_tmr2_pwm_init_t *pstPwmInit);
int32_t TMR2_PWM_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_pwm_init_t *pstPwmInit);
void TMR2_PWM_OutputCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR2_HWCaptureCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR2_HWStartCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR2_HWStopCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR2_HWClearCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR2_SetFilterClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div);
void TMR2_FilterCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR2_IntCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32IntType, en_functional_state_t enNewState);
void TMR2_Start(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
void TMR2_Stop(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
en_flag_status_t TMR2_GetStatus(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag);
void TMR2_ClearStatus(CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag);
void TMR2_SetCompareValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value);
uint32_t TMR2_GetCompareValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
void TMR2_SetCountValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value);
uint32_t TMR2_GetCountValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
void TMR2_PWM_SetPolarity(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint8_t u8CountState, uint32_t u32Polarity);
/**
* @}
*/
#endif /* LL_TMR2_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TMR2_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_tmr4.h
* @brief This file contains all the functions prototypes of the TMR4
* driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TMR4_H__
#define __HC32_LL_TMR4_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TMR4
* @{
*/
#if (LL_TMR4_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR4_Global_Types TMR4 Global Types
* @{
*/
/**
* @brief TMR4 Counter function initialization configuration
* @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock.
*/
typedef struct {
uint16_t u16ClockSrc; /*!< TMR4 counter clock source.
This parameter can be a value of @ref TMR4_Count_Clock_Source */
uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division.
This parameter can be a value of @ref TMR4_Count_Clock_Division. */
uint16_t u16CountMode; /*!< TMR4 counter mode.
This parameter can be a value of @ref TMR4_Count_Mode */
uint16_t u16PeriodValue; /*!< TMR4 counter period value.
This parameter can be a value of half-word */
} stc_tmr4_init_t;
/**
* @brief The configuration of Output-Compare high channel(OUH/OVH/OWH)
*/
typedef union {
uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */
struct { /*!< OCMRxH(x=U/V/W) register struct field bit */
uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
} OCMRx_f;
} un_tmr4_oc_ocmrh_t;
/**
* @brief The configuration of Output-Compare low channel(OUL/OVL/OWL)
*/
typedef union {
uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */
struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/
uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is coutning down
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
} OCMRx_f;
} un_tmr4_oc_ocmrl_t;
/**
* @brief TMR4 Output-Compare(OC) initialization configuration
*/
typedef struct {
uint16_t u16CompareValue; /*!< TMR4 OC compare match value.
This parameter can be a value of half-word. */
uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled.
This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */
uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition.
This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition.
This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask.
This parameter can be a value of @ref TMR4_OC_Buffer_Object. */
} stc_tmr4_oc_init_t;
/**
* @brief TMR4 PWM initialization configuration
* @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock.
*/
typedef struct {
uint16_t u16Mode; /*!< Select PWM mode
This parameter can be a value of @ref TMR4_PWM_Mode */
uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer.
This parameter can be a value of @ref TMR4_PWM_Clock_Division. */
uint16_t u16Polarity; /*!< TMR4 PWM polarity
This parameter can be a value of @ref TMR4_PWM_Polarity */
} stc_tmr4_pwm_init_t;
/**
* @brief TMR4 Special-Event(EVT) initialization configuration
*/
typedef struct {
uint16_t u16Mode; /*!< TMR4 event mode
This parameter can be a value of @ref TMR4_Event_Mode */
uint16_t u16CompareValue; /*!< TMR4 event compare match value.
This parameter can be a value of half-word */
uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition.
This parameter can be a value of @ref TMR4_Event_Output_Event */
uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event.
This parameter can be a value of @ref TMR4_Event_Match_Condition */
} stc_tmr4_evt_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR4_Global_Macros TMR4 Global Macros
* @{
*/
/**
* @defgroup TMR4_Counter_Macros TMR4 Counter Macros
* @{
*/
/**
* @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source
* @{
*/
#define TMR4_CLK_SRC_INTERNCLK (0U)
#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN)
/**
* @}
*/
/**
* @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division
* @{
*/
#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */
#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */
#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */
#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */
#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */
#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */
#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */
#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */
#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */
#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */
#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */
/**
* @}
*/
/**
* @defgroup TMR4_Count_Mode TMR4 Count Mode
* @{
*/
#define TMR4_MD_SAWTOOTH (0U)
#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE)
/**
* @}
*/
/**
* @defgroup TMR4_Flag TMR4 Flag
* @{
*/
#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */
#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */
#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */
#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */
#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */
#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */
#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */
#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */
#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */
#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */
#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */
#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \
TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \
TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \
TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)
/**
* @}
*/
/**
* @defgroup TMR4_Interrupt TMR4 Interrupt
* @{
*/
#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */
#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */
#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */
#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */
#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */
#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */
#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */
#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */
#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */
#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */
#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */
#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \
TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \
TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \
TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)
/**
* @}
*/
/**
* @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time
* @{
*/
#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */
#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) */
#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) */
#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) */
#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) */
#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) */
#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) */
#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) */
#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) */
#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) */
#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) */
#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) */
#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) */
#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) */
#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) */
#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros
* @{
*/
/**
* @defgroup TMR4_OC_Channel TMR4 OC Channel
* @{
*/
#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */
#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */
#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */
#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */
#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */
#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */
/**
* @}
*/
/**
* @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity
* @{
*/
#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */
#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */
/**
* @}
*/
/**
* @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object
* @{
*/
#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function index */
#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function index */
/**
* @}
*/
/**
* @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition
* @{
*/
#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */
#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */
#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */
#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */
/**
* @}
*/
/**
* @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State
* @{
*/
#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */
#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */
/**
* @}
*/
/**
* @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity
* @{
*/
#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */
#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */
#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */
#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Macros TMR4 PWM Macros
* @{
*/
/**
* @defgroup TMR4_PWM_Channel TMR4 PWM Channel
* @{
*/
#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */
#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */
#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Pin TMR4 PWM Pin
* @{
*/
#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4_<t>_OUH */
#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4_<t>_OUL */
#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4_<t>_OVH */
#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4_<t>_OVL */
#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4_<t>_OWH */
#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4_<t>_OWL */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division
* @{
*/
#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */
#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */
#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */
#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */
#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */
#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Mode TMR4 PWM Mode
* @{
*/
#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */
#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */
#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity
* @{
*/
#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */
#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */
#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */
#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index
* @{
*/
#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */
#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status
* @{
*/
#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output normal */
#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) to Hi-z */
#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output low level */
#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output high level */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_Pin_Output_Mode TMR4 PWM Pin Mode
* @{
*/
#define TMR4_PWM_PIN_OUTPUT_OS (0UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output polarity by specified register TMR4_PSCR.OSxy */
#define TMR4_PWM_PIN_OUTPUT_NORMAL (TMR4_PSCR_OEUH) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output normal PWM */
/**
* @}
*/
/**
* @defgroup TMR4_PWM_OE_Bit_Effect_Time TMR4 PWM Register TMR4_PSCR.OE Bit Effect Time
* @{
*/
#define TMR4_PWM_OE_EFFECT_IMMED (TMR4_PSCR_ODT_0) /*!< TMR4 PWM reister TMR4_PSCR.OE bit immediate effect. */
#define TMR4_PWM_OE_EFFECT_COUNT_PEAK (TMR4_PSCR_ODT) /*!< TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count peak. */
#define TMR4_PWM_OE_EFFECT_COUNT_VALLEY (TMR4_PSCR_ODT_1) /*!< TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count valley. */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup TMR4_Event_Macros TMR4 Event Macros
* @{
*/
/**
* @defgroup TMR4_Event_Channel TMR4 Event Channel
* @{
*/
#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */
#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */
#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */
#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */
#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */
#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition
* @{
*/
#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */
#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */
#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */
#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count vallay */
#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \
TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY)
/**
* @}
*/
/**
* @defgroup TMR4_Event_Mask TMR4 Event Mask
* @{
*/
#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */
#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */
#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY)
/**
* @}
*/
/**
* @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition
* @{
*/
#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */
#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */
#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */
#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Mode TMR4 Event Mode
* @{
*/
#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */
#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object
* @{
*/
#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */
#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times
* @{
*/
#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */
#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */
#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */
#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */
#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */
#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */
#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */
#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */
#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */
#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */
#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */
#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */
#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */
#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */
#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */
#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Output_Event TMR4 Event Output Event
* @{
*/
#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */
#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */
#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */
#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */
#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */
#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */
/**
* @}
*/
/**
* @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal
* @{
*/
#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */
#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR4_Global_Functions
* @{
*/
/**
* @addtogroup TMR4_Counter_Global_Functions
* @{
*/
/* Initialization and configuration TMR4 counter functions */
int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init);
int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init);
void TMR4_DeInit(CM_TMR4_TypeDef *TMR4x);
void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src);
void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div);
void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode);
uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x);
void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x);
void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x);
void TMR4_Start(CM_TMR4_TypeDef *TMR4x);
void TMR4_Stop(CM_TMR4_TypeDef *TMR4x);
void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState);
void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType);
void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime);
uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType);
void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
/**
* @}
*/
/**
* @addtogroup TMR4_Output_Compare_Global_Functions
* @{
*/
/* Initialization and configuration TMR4 Output-Compare functions */
int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit);
int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit);
void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR4_OC_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
uint16_t u16Object, en_functional_state_t enNewState);
uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond);
uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh);
uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl);
/**
* @}
*/
/**
* @addtogroup TMR4_PWM_Global_Functions
* @{
*/
/* Initialization and configuration TMR4 PWM functions */
int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div);
void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value);
uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex);
void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus);
void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time);
void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode);
/**
* @}
*/
/**
* @addtogroup TMR4_Event_Global_Functions
* @{
*/
/* Initialization and configuration TMR4 event functions */
int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit);
int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit);
void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object);
void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime);
uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event);
void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond);
void TMR4_EVT_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR4_EVT_EventIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
uint16_t u16MaskType, en_functional_state_t enNewState);
void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal);
/**
* @}
*/
/**
* @}
*/
#endif /* LL_TMR4_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TMR4_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,917 @@
/**
*******************************************************************************
* @file hc32_ll_tmr6.h
* @brief Head file for TMR6 module.
*
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TMR6_H__
#define __HC32_LL_TMR6_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TMR6
* @{
*/
#if (LL_TMR6_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR6_Global_Types TMR6 Global Types
* @{
*/
/**
* @brief Timer6 count function structure definition
*/
typedef struct {
uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */
union {
struct {
uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */
uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */
uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */
} sw_count;
struct {
uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */
uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */
uint32_t u32Reserved; /*!< Reserved */
} hw_count;
};
uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */
uint32_t u32CountReload; /*!< Count reload after overflow @ref TMR6_Count_Reload_Define */
} stc_timer6_init_t;
/**
* @brief Timer6 pwm output function structure definition
*/
typedef struct {
uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */
uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */
uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */
uint32_t u32CountUpMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-up mode \
@ref TMR6_Pin_Polarity_Define */
uint32_t u32CountDownMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-down mode \
@ref TMR6_Pin_Polarity_Define */
uint32_t u32CountUpMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-up mode \
@ref TMR6_Pin_Polarity_Define*/
uint32_t u32CountDownMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-down mode\
@ref TMR6_Pin_Polarity_Define */
uint32_t u32UdfPolarity; /*!< Pin polarity when underflow @ref TMR6_Pin_Polarity_Define */
uint32_t u32OvfPolarity; /*!< Pin polarity when overflow @ref TMR6_Pin_Polarity_Define */
} stc_tmr6_pwm_init_t;
/**
* @brief Timer6 buffer function configuration structure definition
*/
typedef struct {
uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \
@ref TMR6_Buf_Num_Define */
uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \
@ref TMR6_Buf_Trans_Cond_Define */
} stc_tmr6_buf_config_t;
/**
* @brief Timer6 Valid period function configuration structure definition
*/
typedef struct {
uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \
@ref TMR6_Valid_Period_Count_Cond_Define */
uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */
} stc_tmr6_valid_period_config_t;
/**
* @brief Timer6 EMB configuration structure definition
*/
typedef struct {
uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_Ch_Define */
uint32_t u32ReleaseMode; /*!< Pin release mode when EMB event invalid @ref TMR6_Emb_Release_Mode_Define */
uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */
} stc_tmr6_emb_config_t;
/**
* @brief Timer6 Dead time function configuration structure definition
*/
typedef struct {
uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \
@ref TMR6_Deadtime_Reg_Equal_Func_Define */
uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \
@ref TMR6_Deadtime_CountUp_Buf_Func_Define*/
uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \
@ref TMR6_Deadtime_CountDown_Buf_Func_Define*/
uint32_t u32UpdateCond; /*!< Buffer transfer condition for triangular wave mode \
@ref TMR6_Deadtime_Buf_Trans_Cond_Define */
} stc_tmr6_deadtime_config_t;
/**
* @brief Timer6 Dead time function configuration structure definition
*/
typedef struct {
uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */
uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \
the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */
uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \
during the time of Z phase input mask \
@ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/
} stc_tmr6_zmask_config_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR6_Global_Macros TMR6 Global Macros
* @{
*/
/**
* @defgroup TMR6_Count_Src_Define TMR6 Count Source Define
* @{
*/
#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */
#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */
/**
* @}
*/
/**
* @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define
* @{
*/
#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */
#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */
#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */
#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */
#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */
#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */
#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \
Triangular wave peak point */
#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \
Triangular wave valley point */
#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */
#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */
#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */
#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */
#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */
#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */
#define TMR6_FLAG_CLR_ALL (0x00001EFFUL) /*!< Clear all flag */
#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \
TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \
TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \
TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \
TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \
TMR6_FLAG_CNT_DIR)
/**
* @}
*/
/**
* @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define
* @{
*/
#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */
#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */
#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */
#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */
#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */
#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */
#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */
#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */
#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */
#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */
#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */
#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */
#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */
#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\
TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \
TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \
TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \
TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B)
/**
* @}
*/
/**
* @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define
* @{
*/
#define TMR6_PERIOD_REG_A (0x00UL)
#define TMR6_PERIOD_REG_B (0x01UL)
#define TMR6_PERIOD_REG_C (0x02UL)
/**
* @}
*/
/**
* @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define
* @{
*/
#define TMR6_CMP_REG_A (0x00UL)
#define TMR6_CMP_REG_B (0x01UL)
#define TMR6_CMP_REG_C (0x02UL)
#define TMR6_CMP_REG_D (0x03UL)
#define TMR6_CMP_REG_E (0x04UL)
#define TMR6_CMP_REG_F (0x05UL)
/**
* @}
*/
/**
* @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define
* @{
*/
#define TMR6_CH_A (0x00UL)
#define TMR6_CH_B (0x01UL)
/**
* @}
*/
/**
* @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define
* @{
*/
#define TMR6_BUF_SINGLE (0x00000000UL)
#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA)
/**
* @}
*/
/**
* @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define
* @{
*/
#define TMR6_BUF_TRANS_INVD (0x00000000UL)
#define TMR6_BUF_TRANS_OVF (0x00000004UL)
#define TMR6_BUF_TRANS_UDF (0x00000008UL)
#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL)
/**
* @}
*/
/**
* @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define
* @{
*/
#define TMR6_VALID_PERIOD_INVD (0x00000000UL) /*!< Valid period function off */
#define TMR6_VALID_PERIOD_CNT_COND_UDF (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \
triangular wave underflow */
#define TMR6_VALID_PERIOD_CNT_COND_OVF (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \
triangular wave overflow */
#define TMR6_VALID_PERIOD_CNT_COND_OVF_UDF (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \
triangular wave overflow and underflow */
/**
* @}
*/
/**
* @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define
* @{
*/
#define TMR6_VALID_PERIOD_CNT_INVD (0x00000000UL)
#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS)
#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS)
/**
* @}
*/
/**
* @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define
* @{
*/
#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */
#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */
#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */
#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */
/**
* @}
*/
/**
* @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define
* @{
*/
#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6_<t>_PWMA */
#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6_<t>_PWMB */
#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */
#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */
#define TMR6_INPUT_TRIGC (0x04U) /*!< Input pin TIM6_TRIGC */
#define TMR6_INPUT_TRIGD (0x05U) /*!< Input pin TIM6_TRIGD */
/**
* @}
*/
/**
* @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define
* @{
*/
#define TMR6_FILTER_CLK_DIV1 (0x00U)
#define TMR6_FILTER_CLK_DIV4 (0x01U)
#define TMR6_FILTER_CLK_DIV16 (0x02U)
#define TMR6_FILTER_CLK_DIV64 (0x03U)
/**
* @}
*/
/**
* @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection
* @{
*/
#define TMR6_PIN_CMP_OUTPUT (0x00U)
#define TMR6_PIN_CAPT_INPUT (TMR6_PCNAR_CAPMDA)
/**
* @}
*/
/**
* @defgroup TMR6_Count_State_Define TMR6 Count State
* @{
*/
#define TMR6_STAT_START (0U) /*!< Count start */
#define TMR6_STAT_STOP (1U) /*!< Count stop */
#define TMR6_STAT_OVF (2U) /*!< Count overflow */
#define TMR6_STAT_UDF (3U) /*!< Count underflow */
#define TMR6_STAT_UP_CNT_MATCH_A (4U) /*!< Count up match compare register A */
#define TMR6_STAT_DOWN_CNT_MATCH_A (5U) /*!< Count down match compare register A */
#define TMR6_STAT_UP_CNT_MATCH_B (6U) /*!< Count up match compare register B */
#define TMR6_STAT_DOWN_CNT_MATCH_B (7U) /*!< Count down match compare register B */
/**
* @}
*/
/**
* @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity
* @{
*/
#define TMR6_PWM_LOW (0x00U)
#define TMR6_PWM_HIGH (0x01U)
#define TMR6_PWM_HOLD (0x02U)
#define TMR6_PWM_INVT (0x03U)
/**
* @}
*/
/**
* @defgroup TMR6_Force_Output_Polarity_Define TMR6 Force Output Polarity Next Period
* @{
*/
#define TMR6_PWM_FORCE_INVD (0x00U)
#define TMR6_PWM_FORCE_LOW (0x02U)
#define TMR6_PWM_FORCE_HIGH (0x03U)
/**
* @}
*/
/**
* @defgroup TMR6_Emb_Ch_Define TMR6 EMB Event Channel
* @{
*/
#define TMR6_EMB_EVT_CH0 (0x00U)
#define TMR6_EMB_EVT_CH1 (TMR6_PCNAR_EMBSA_0)
#define TMR6_EMB_EVT_CH2 (TMR6_PCNAR_EMBSA_1)
#define TMR6_EMB_EVT_CH3 (TMR6_PCNAR_EMBSA)
/**
* @}
*/
/**
* @defgroup TMR6_Emb_Release_Mode_Define TMR6 EMB Function Release Mode When EMB Event Invalid
* @{
*/
#define TMR6_EMB_RELEASE_IMMED (0x00U)
#define TMR6_EMB_RELEASE_OVF (TMR6_PCNAR_EMBRA_0)
#define TMR6_EMB_RELEASE_UDF (TMR6_PCNAR_EMBRA_1)
#define TMR6_EMB_RELEASE_OVF_UDF (TMR6_PCNAR_EMBRA)
/**
* @}
*/
/**
* @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid
* @{
*/
#define TMR6_EMB_PIN_NORMAL (0x00U)
#define TMR6_EMB_PIN_HIZ (TMR6_PCNAR_EMBCA_0)
#define TMR6_EMB_PIN_LOW (TMR6_PCNAR_EMBCA_1)
#define TMR6_EMB_PIN_HIGH (TMR6_PCNAR_EMBCA)
/**
* @}
*/
/**
* @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage
* @{
*/
#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00U)
#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU)
/**
* @}
*/
/**
* @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage
* @{
*/
#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00U)
#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND)
/**
* @}
*/
/**
* @defgroup TMR6_Deadtime_Buf_Trans_Cond_Define TMR6 Dead Time Buffer Transfer Condition Define For Triangular Count Mode
* @{
*/
#define TMR6_DEADTIME_BUF_COND_INVD (0x00U)
#define TMR6_DEADTIME_BUF_COND_OVF (TMR6_DCONR_DTBTRU)
#define TMR6_DEADTIME_BUF_COND_UDF (TMR6_DCONR_DTBTRD)
#define TMR6_DEADTIME_BUF_COND_OVF_UDF (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD)
/**
* @}
*/
/**
* @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR
* @{
*/
#define TMR6_DEADTIME_EQUAL_OFF (0x00U)
#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA)
/**
* @}
*/
/**
* @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define
* @{
*/
#define TMR6_SW_SYNC_U1 (TMR6CR_SSTAR_SSTA1)
#define TMR6_SW_SYNC_U2 (TMR6CR_SSTAR_SSTA2)
#define TMR6_SW_SYNC_U3 (TMR6CR_SSTAR_SSTA3)
#define TMR6_SW_SYNC_U4 (TMR6CR_SSTAR_SSTA4)
#define TMR6_SW_SYNC_U5 (TMR6CR_SSTAR_SSTA5)
#define TMR6_SW_SYNC_U6 (TMR6CR_SSTAR_SSTA6)
#define TMR6_SW_SYNC_U7 (TMR6CR_SSTAR_SSTA7)
#define TMR6_SW_SYNC_U8 (TMR6CR_SSTAR_SSTA8)
#define TMR6_SW_SYNC_ALL (0xFFU)
/**
* @}
*/
/**
* @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define
* @{
*/
#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA0)
#define TMR6_START_COND_PWMA_FAILLING (TMR6_HSTAR_HSTA1)
#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA2)
#define TMR6_START_COND_PWMB_FAILLING (TMR6_HSTAR_HSTA3)
#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA8)
#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA9)
#define TMR6_START_COND_EVT2 (TMR6_HSTAR_HSTA10)
#define TMR6_START_COND_EVT3 (TMR6_HSTAR_HSTA11)
#define TMR6_START_COND_TRIGEA_RISING (TMR6_HSTAR_HSTA16)
#define TMR6_START_COND_TRIGEA_FAILLING (TMR6_HSTAR_HSTA17)
#define TMR6_START_COND_TRIGEB_RISING (TMR6_HSTAR_HSTA18)
#define TMR6_START_COND_TRIGEB_FAILLING (TMR6_HSTAR_HSTA19)
#define TMR6_START_COND_TRIGEC_RISING (TMR6_HSTAR_HSTA20)
#define TMR6_START_COND_TRIGEC_FAILLING (TMR6_HSTAR_HSTA21)
#define TMR6_START_COND_TRIGED_RISING (TMR6_HSTAR_HSTA22)
#define TMR6_START_COND_TRIGED_FAILLING (TMR6_HSTAR_HSTA23)
#define TMR6_START_COND_ALL (0x00FF0F0FUL)
/**
* @}
*/
/**
* @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define
* @{
*/
#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP0)
#define TMR6_STOP_COND_PWMA_FAILLING (TMR6_HSTPR_HSTP1)
#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP2)
#define TMR6_STOP_COND_PWMB_FAILLING (TMR6_HSTPR_HSTP3)
#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP8)
#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP9)
#define TMR6_STOP_COND_EVT2 (TMR6_HSTPR_HSTP10)
#define TMR6_STOP_COND_EVT3 (TMR6_HSTPR_HSTP11)
#define TMR6_STOP_COND_TRIGEA_RISING (TMR6_HSTPR_HSTP16)
#define TMR6_STOP_COND_TRIGEA_FAILLING (TMR6_HSTPR_HSTP17)
#define TMR6_STOP_COND_TRIGEB_RISING (TMR6_HSTPR_HSTP18)
#define TMR6_STOP_COND_TRIGEB_FAILLING (TMR6_HSTPR_HSTP19)
#define TMR6_STOP_COND_TRIGEC_RISING (TMR6_HSTPR_HSTP20)
#define TMR6_STOP_COND_TRIGEC_FAILLING (TMR6_HSTPR_HSTP21)
#define TMR6_STOP_COND_TRIGED_RISING (TMR6_HSTPR_HSTP22)
#define TMR6_STOP_COND_TRIGED_FAILLING (TMR6_HSTPR_HSTP23)
#define TMR6_STOP_COND_ALL (0x00FF0F0FUL)
/**
* @}
*/
/**
* @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define
* @{
*/
#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE0)
#define TMR6_CLR_COND_PWMA_FAILLING (TMR6_HCLRR_HCLE1)
#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE2)
#define TMR6_CLR_COND_PWMB_FAILLING (TMR6_HCLRR_HCLE3)
#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE8)
#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE9)
#define TMR6_CLR_COND_EVT2 (TMR6_HCLRR_HCLE10)
#define TMR6_CLR_COND_EVT3 (TMR6_HCLRR_HCLE11)
#define TMR6_CLR_COND_TRIGEA_RISING (TMR6_HCLRR_HCLE16)
#define TMR6_CLR_COND_TRIGEA_FAILLING (TMR6_HCLRR_HCLE17)
#define TMR6_CLR_COND_TRIGEB_RISING (TMR6_HCLRR_HCLE18)
#define TMR6_CLR_COND_TRIGEB_FAILLING (TMR6_HCLRR_HCLE19)
#define TMR6_CLR_COND_TRIGEC_RISING (TMR6_HCLRR_HCLE20)
#define TMR6_CLR_COND_TRIGEC_FAILLING (TMR6_HCLRR_HCLE21)
#define TMR6_CLR_COND_TRIGED_RISING (TMR6_HCLRR_HCLE22)
#define TMR6_CLR_COND_TRIGED_FAILLING (TMR6_HCLRR_HCLE23)
#define TMR6_CLR_COND_ALL (0x00FF0F0FUL)
/**
* @}
*/
/**
* @defgroup TMR6_hardware_update_condition_Define TMR6 Hardware Update Condition Define
* @{
*/
#define TMR6_UPD_COND_PWMA_RISING (TMR6_HUPDR_HUPD0)
#define TMR6_UPD_COND_PWMA_FAILLING (TMR6_HUPDR_HUPD1)
#define TMR6_UPD_COND_PWMB_RISING (TMR6_HUPDR_HUPD2)
#define TMR6_UPD_COND_PWMB_FAILLING (TMR6_HUPDR_HUPD3)
#define TMR6_UPD_COND_EVT0 (TMR6_HUPDR_HUPD8)
#define TMR6_UPD_COND_EVT1 (TMR6_HUPDR_HUPD9)
#define TMR6_UPD_COND_EVT2 (TMR6_HUPDR_HUPD10)
#define TMR6_UPD_COND_EVT3 (TMR6_HUPDR_HUPD11)
#define TMR6_UPD_COND_TRIGEA_RISING (TMR6_HUPDR_HUPD16)
#define TMR6_UPD_COND_TRIGEA_FAILLING (TMR6_HUPDR_HUPD17)
#define TMR6_UPD_COND_TRIGEB_RISING (TMR6_HUPDR_HUPD18)
#define TMR6_UPD_COND_TRIGEB_FAILLING (TMR6_HUPDR_HUPD19)
#define TMR6_UPD_COND_TRIGEC_RISING (TMR6_HUPDR_HUPD20)
#define TMR6_UPD_COND_TRIGEC_FAILLING (TMR6_HUPDR_HUPD21)
#define TMR6_UPD_COND_TRIGED_RISING (TMR6_HUPDR_HUPD22)
#define TMR6_UPD_COND_TRIGED_FAILLING (TMR6_HUPDR_HUPD23)
#define TMR6_UPD_COND_ALL (0x00FF0F0FUL)
/**
* @}
*/
/**
* @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define
* @{
*/
#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA0)
#define TMR6_CAPT_COND_PWMA_FAILLING (TMR6_HCPAR_HCPA1)
#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA2)
#define TMR6_CAPT_COND_PWMB_FAILLING (TMR6_HCPAR_HCPA3)
#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA8)
#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA9)
#define TMR6_CAPT_COND_EVT2 (TMR6_HCPAR_HCPA10)
#define TMR6_CAPT_COND_EVT3 (TMR6_HCPAR_HCPA11)
#define TMR6_CAPT_COND_TRIGEA_RISING (TMR6_HCPAR_HCPA16)
#define TMR6_CAPT_COND_TRIGEA_FAILLING (TMR6_HCPAR_HCPA17)
#define TMR6_CAPT_COND_TRIGEB_RISING (TMR6_HCPAR_HCPA18)
#define TMR6_CAPT_COND_TRIGEB_FAILLING (TMR6_HCPAR_HCPA19)
#define TMR6_CAPT_COND_TRIGEC_RISING (TMR6_HCPAR_HCPA20)
#define TMR6_CAPT_COND_TRIGEC_FAILLING (TMR6_HCPAR_HCPA21)
#define TMR6_CAPT_COND_TRIGED_RISING (TMR6_HCPAR_HCPA22)
#define TMR6_CAPT_COND_TRIGED_FAILLING (TMR6_HCPAR_HCPA23)
#define TMR6_CAPT_COND_ALL (0x00FF0F0FUL)
/**
* @}
*/
/**
* @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define
* @{
*/
#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0)
#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCUPR_HCUP1)
#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2)
#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCUPR_HCUP3)
#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4)
#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCUPR_HCUP5)
#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6)
#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCUPR_HCUP7)
#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP8)
#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP9)
#define TMR6_CNT_UP_COND_EVT2 (TMR6_HCUPR_HCUP10)
#define TMR6_CNT_UP_COND_EVT3 (TMR6_HCUPR_HCUP11)
#define TMR6_CNT_UP_COND_TRIGEA_RISING (TMR6_HCUPR_HCUP16)
#define TMR6_CNT_UP_COND_TRIGEA_FAILLING (TMR6_HCUPR_HCUP17)
#define TMR6_CNT_UP_COND_TRIGEB_RISING (TMR6_HCUPR_HCUP18)
#define TMR6_CNT_UP_COND_TRIGEB_FAILLING (TMR6_HCUPR_HCUP19)
#define TMR6_CNT_UP_COND_TRIGEC_RISING (TMR6_HCUPR_HCUP20)
#define TMR6_CNT_UP_COND_TRIGEC_FAILLING (TMR6_HCUPR_HCUP21)
#define TMR6_CNT_UP_COND_TRIGED_RISING (TMR6_HCUPR_HCUP22)
#define TMR6_CNT_UP_COND_TRIGED_FAILLING (TMR6_HCUPR_HCUP23)
#define TMR6_CNT_UP_COND_ALL (0x00FF0FFFUL)
/**
* @}
*/
/**
* @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define
* @{
*/
#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0)
#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCDOR_HCDO1)
#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2)
#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCDOR_HCDO3)
#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4)
#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCDOR_HCDO5)
#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6)
#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCDOR_HCDO7)
#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO8)
#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO9)
#define TMR6_CNT_DOWN_COND_EVT2 (TMR6_HCDOR_HCDO10)
#define TMR6_CNT_DOWN_COND_EVT3 (TMR6_HCDOR_HCDO11)
#define TMR6_CNT_DOWN_COND_TRIGEA_RISING (TMR6_HCDOR_HCDO16)
#define TMR6_CNT_DOWN_COND_TRIGEA_FAILLING (TMR6_HCDOR_HCDO17)
#define TMR6_CNT_DOWN_COND_TRIGEB_RISING (TMR6_HCDOR_HCDO18)
#define TMR6_CNT_DOWN_COND_TRIGEB_FAILLING (TMR6_HCDOR_HCDO19)
#define TMR6_CNT_DOWN_COND_TRIGEC_RISING (TMR6_HCDOR_HCDO20)
#define TMR6_CNT_DOWN_COND_TRIGEC_FAILLING (TMR6_HCDOR_HCDO21)
#define TMR6_CNT_DOWN_COND_TRIGED_RISING (TMR6_HCDOR_HCDO22)
#define TMR6_CNT_DOWN_COND_TRIGED_FAILLING (TMR6_HCDOR_HCDO23)
#define TMR6_CNT_DOWN_COND_ALL (0x00FF0FFFUL)
/**
* @}
*/
/**
* @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define
* @{
*/
#define TMR6_CNT_UP (TMR6_GCONR_DIR)
#define TMR6_CNT_DOWN (0x00U)
/**
* @}
*/
/**
* @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define
* @{
*/
#define TMR6_MD_SAWTOOTH (0x00U)
#define TMR6_MD_TRIANGLE (TMR6_GCONR_MODE)
/**
* @}
*/
/**
* @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define
* @{
*/
#define TMR6_CLK_DIV1 (0x00UL)
#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS)
/**
* @}
*/
/**
* @defgroup TMR6_Count_Reload_Define TMR6 Count Stop After Overflow Function Define
* @{
*/
#define TMR6_CNT_RELOAD_ON (0x00U)
#define TMR6_CNT_RELOAD_OFF (TMR6_GCONR_OVSTP)
/**
* @}
*/
/**
* @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define
* @{
*/
#define TMR6_ZMASK_FUNC_INVD (0x00U)
#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0)
#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1)
#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL)
/**
* @}
*/
/**
* @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action
* @{
*/
#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00U)
#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS)
/**
* @}
*/
/**
* @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action
* @{
*/
#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00U)
#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR6_Global_Functions
* @{
*/
/**
* @brief Get Software Sync start status
* @param None
* @retval uint32_t Data indicate the read status.
*/
__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void)
{
return READ_REG32(CM_TMR6CR->SSTAR);
}
/* Base count */
int32_t TMR6_StructInit(stc_timer6_init_t *pstcTmr6Init);
int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_timer6_init_t *pstcTmr6Init);
void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode);
void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir);
uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x);
void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div);
void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Hardware count */
void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
/* PWM output */
int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit);
int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit);
void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity);
void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity);
/* Input capture */
void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
/* Pin config */
int32_t TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div);
void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState);
void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func);
/* Universal */
void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x);
void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x);
void TMR6_Start(CM_TMR6_TypeDef *TMR6x);
void TMR6_Stop(CM_TMR6_TypeDef *TMR6x);
/* Register write */
void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value);
void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value);
void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
/* Register read */
uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x);
uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x);
uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
/* Buffer function */
int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig);
int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig);
int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig);
void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Extend function */
int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig);
int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig);
int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig);
int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig);
int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig);
/* Software synchronous control */
void TMR6_SWSyncStart(uint32_t u32Unit);
void TMR6_SWSyncStop(uint32_t u32Unit);
void TMR6_SWSyncClear(uint32_t u32Unit);
void TMR6_SWSyncUpdate(uint32_t u32Unit);
/* Hardware control */
void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* LL_TMR6_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TMR6_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_tmra.h
* @brief This file contains all the functions prototypes of the TMRA(TimerA)
* driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TMRA_H__
#define __HC32_LL_TMRA_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TMRA
* @{
*/
#if (LL_TMRA_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMRA_Global_Types TMRA Global Types
* @{
*/
/**
* @brief TMRA initialization structure.
*/
typedef struct {
uint8_t u8CountSrc; /*!< Specifies the count source of TMRA.
This parameter can be a value of @ref TMRA_Count_Src */
union {
struct {
uint16_t u16ClockDiv; /*!< Specifies the divider of software clock source.
This parameter can be a value of @ref TMRA_Clock_Divider */
uint16_t u16CountMode; /*!< Specifies count mode.
This parameter can be a value of @ref TMRA_Count_Mode */
uint16_t u16CountDir; /*!< Specifies count direction.
This parameter can be a value of @ref TMRA_Count_Dir */
} sw_count;
struct {
uint16_t u16CountUpCond; /*!< Hardware count up condition.
This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */
uint16_t u16CountDownCond; /*!< Hardware count down condition.
This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */
uint16_t u16Reserved; /*!< Reserved, for future use. */
} hw_count;
};
uint32_t u32PeriodValue; /*!< Specifies the period reference value.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
uint16_t u16CountReload; /*!< Continue counting or stop when counter overflow/underflow.
This parameter can be a value of @ref TMRA_Count_Reload_En */
} stc_tmra_init_t;
/**
* @brief TMRA PWM configuration structure.
*/
typedef struct {
uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel.
This parameter can be a number between:
0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472.
0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. */
uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting.
This parameter can be a value of @ref TMRA_PWM_Polarity
NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when
sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified
as @ref TMRA_CLK_DIV1 */
uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting.
This parameter can be a value of @ref TMRA_PWM_Polarity */
uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register.
This parameter can be a value of @ref TMRA_PWM_Polarity */
uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register.
This parameter can be a value of @ref TMRA_PWM_Polarity */
} stc_tmra_pwm_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMRA_Global_Macros TMRA Global Macros
* @{
*/
/**
* @defgroup TMRA_Count_Src TMRA Count Source
* @{
*/
#define TMRA_CNT_SRC_SW (0U)
#define TMRA_CNT_SRC_HW (1U)
/**
* @}
*/
/**
* @defgroup TMRA_Channel TMRA Channel
* @note TMRA_1 and TMRA_2 of HC32M423 contain only one channel TMRA_CH1.
* @{
*/
#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */
#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */
#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */
#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */
/**
* @}
*/
/**
* @defgroup TMRA_Count_Dir TMRA Count Direction
* @{
*/
#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */
#define TMRA_DIR_UP (TMRA_BCSTR_DIR) /*!< TMRA count up. */
/**
* @}
*/
/**
* @defgroup TMRA_Count_Mode TMRA Count Mode
* @{
*/
#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */
#define TMRA_MD_TRIANGLE (TMRA_BCSTR_MODE) /*!< Count mode is triangle wave. */
/**
* @}
*/
/**
* @defgroup TMRA_Function_Mode TMRA TMRA Function Mode
* @{
*/
#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */
#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */
/**
* @}
*/
/* Counter reload */
/**
* @defgroup TMRA_Count_Reload_En TMRA Count Reload
* @{
*/
#define TMRA_CNT_RELOAD_DISABLE (TMRA_BCSTR_OVSTP) /*!< Stop when counter overflow/underflow. */
#define TMRA_CNT_RELOAD_ENABLE (0U) /*!< When counter overflow/underflow, counter reload to continue counting. */
/**
* @}
*/
/**
* @defgroup TMRA_Clock_Divider TMRA Clock Divider
* @{
*/
#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */
#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */
#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */
#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */
#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */
#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */
#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */
#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */
#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */
#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */
#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */
/**
* @}
*/
/**
* @defgroup TMRA_Filter_Pin TMRA Pin With Filter
* @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain pin TMRA_PIN_PWM2.
* @{
*/
#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA_<t>_TRIG. */
#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA_<t>_CLKA. */
#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA_<t>_CLKB. */
#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA_<t>_PWM1. */
#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA_<t>_PWM2. */
#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA_<t>_PWM3. */
#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA_<t>_PWM4. */
/**
* @}
*/
/**
* @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
* @{
*/
#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */
#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */
#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */
#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts up. */
/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */
#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */
#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */
#define TMRA_CNT_UP_COND_ALL (0x1FFFU)
/**
* @}
*/
/**
* @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
* @{
*/
#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */
#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts down. */
/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */
#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */
#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU)
/**
* @}
*/
/**
* @defgroup TMRA_Interrupt_Type TMRA Interrupt Type
* @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain interrupt TMRA_INT_CMP_CH2.
* @{
*/
#define TMRA_INT_OVF (1UL << 12U) /*!< The interrupt of counting overflow. */
#define TMRA_INT_UDF (1UL << 13U) /*!< The interrupt of counting underflow. */
#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */
#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */
#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */
#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */
#define TMRA_INT_ALL (0xF3000UL)
/**
* @}
*/
/**
* @defgroup TMRA_Event_Type TMRA Event Type
* @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain event TMRA_EVT_CMP_CH2.
* @{
*/
#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */
#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */
#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */
#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */
#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | \
TMRA_EVT_CMP_CH3 | TMRA_EVT_CMP_CH4)
/**
* @}
*/
/**
* @defgroup TMRA_Status_Flag TMRA Status Flag
* @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain flag TMRA_FLAG_CMP_CH2.
* @{
*/
#define TMRA_FLAG_OVF (1UL << 14U) /*!< The flag of counting overflow. */
#define TMRA_FLAG_UDF (1UL << 15U) /*!< The flag of counting underflow. */
#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */
#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */
#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */
#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */
#define TMRA_FLAG_ALL (0xFC000UL)
/**
* @}
*/
/**
* @defgroup TMRA_Capture_Cond TMRA Capture Condition
* @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4.
* @{
*/
#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */
#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_PWMn. */
#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_PWMn. */
#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */
#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_TRIG.
This condition is only valid for channel 4. */
#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_TRIG.
This condition is only valid for channel 4. */
#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \
TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \
TMRA_CAPT_COND_TRIG_FALLING)
/**
* @}
*/
/**
* @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition
* @{
*/
#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode.
When counting overflow or underflow or counting register was cleared,
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak,
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley,
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */
#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \
TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley,
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
/**
* @}
*/
/**
* @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider
* @{
*/
#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timerA / 1 */
#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of timerA / 4 */
#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of timerA / 16 */
#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of timerA / 64 */
/**
* @}
*/
/**
* @defgroup TMRA_Counter_State TMRA Counter State
* @{
*/
#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */
#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */
#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matchs the compare value. */
#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matchs the period value. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Polarity TMRA PWM Polarity
* @{
*/
#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */
#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */
#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */
#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity
* @{
*/
#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */
#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle.
The beginning of the next cycle: overflow position or underflow position
of sawtooth wave; valley position of triangle wave. */
#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle.
The beginning of the next cycle: overflow position or underflow position
of sawtooth wave; valley position of triangle wave. */
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition
* @{
*/
#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */
#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit.
2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */
#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit.
2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */
#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \
TMRA_START_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition
* @{
*/
#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */
#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */
#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */
#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \
TMRA_STOP_COND_EVT)
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12.
* @{
*/
#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */
#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */
#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */
#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */
#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */
#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */
#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */
#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \
TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \
TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \
TMRA_CLR_COND_PWM3_FALLING)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMRA_Global_Functions
* @{
*/
/* Base count(use software clock PCLK/HCLK) */
int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit);
int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit);
void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint16_t u16Mode);
void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint16_t u16Dir);
void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint16_t u16Div);
/* Hardware count */
void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
/* Set function mode */
void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func);
/* Ouput compare */
int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit);
int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit);
void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity);
void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity);
/* Input capture */
void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
/* Trigger: hardware trigger to start/stop/clear the counter */
void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
/* Filter */
void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div);
void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState);
/* Global */
void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx);
/* Counting direction, period value, counter value, compare value */
uint16_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx);
void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx);
void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx);
void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value);
uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch);
/* Sync start. */
void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
/* Reload and continue counting when overflow/underflow? */
void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond);
void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState);
void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState);
void TMRA_Start(CM_TMRA_TypeDef *TMRAx);
void TMRA_Stop(CM_TMRA_TypeDef *TMRAx);
/**
* @}
*/
#endif /* LL_TMRA_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TMRA_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_trng.h
* @brief This file contains all the functions prototypes of the TRNG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_TRNG_H__
#define __HC32_LL_TRNG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_TRNG
* @{
*/
#if (LL_TRNG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TRNG_Global_Macros TRNG Global Macros
* @{
*/
/**
* @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value
* @{
*/
#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */
#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */
/**
* @}
*/
/**
* @defgroup TRNG_Shift_Ctrl TRNG Shift Control
* @{
*/
#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */
#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */
#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */
#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TRNG_Global_Functions
* @{
*/
void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn);
/* For polling mode. */
int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint8_t u8RandomLen);
/* For interrupt mode. */
void TRNG_Start(void);
int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen);
/**
* @}
*/
#endif /* LL_TRNG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_TRNG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_usart.h
* @brief This file contains all the functions prototypes of the USART(Universal
* Synchronous/Asynchronous Receiver Transmitter) driver library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_USART_H__
#define __HC32_LL_USART_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_USART
* @{
*/
#if (LL_USART_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup USART_Global_Types USART Global Types
* @{
*/
/**
* @brief clock synchronization mode initialization structure definition
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Clock Source.
This parameter can be a value of @ref USART_Clock_Source */
uint32_t u32ClockDiv; /*!< Clock division.
This parameter can be a value of @ref USART_Clock_Division. */
uint32_t u32Baudrate; /*!< USART baudrate.
This parameter is valid when clock source is the internal clock. */
uint32_t u32FirstBit; /*!< Significant bit.
This parameter can be a value of @ref USART_First_Bit */
uint32_t u32HWFlowControl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_clocksync_init_t;
/**
* @brief UART multiple-processor initialization structure definition
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Clock Source.
This parameter can be a value of @ref USART_Clock_Source */
uint32_t u32ClockDiv; /*!< Clock division.
This parameter can be a value of @ref USART_Clock_Division. */
uint32_t u32CKOutput; /*!< USART_CK output selection.
This parameter can be a value of @ref USART_CK_Output_Selection. */
uint32_t u32Baudrate; /*!< USART baudrate.
This parameter is valid when clock source is the internal clock. */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Width_Bit */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bit */
uint32_t u32OverSampleBit; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Over_Sample_Bit */
uint32_t u32FirstBit; /*!< Significant bit.
This parameter can be a value of @ref USART_First_Bit */
uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Polarity */
uint32_t u32HWFlowControl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_multiprocessor_init_t;
/**
* @brief UART mode initialization structure definition
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Clock Source.
This parameter can be a value of @ref USART_Clock_Source */
uint32_t u32ClockDiv; /*!< Clock division.
This parameter can be a value of @ref USART_Clock_Division. */
uint32_t u32CKOutput; /*!< USART_CK output selection.
This parameter can be a value of @ref USART_CK_Output_Selection. */
uint32_t u32Baudrate; /*!< USART baudrate.
This parameter is valid when clock source is the internal clock. */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Width_Bit */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bit */
uint32_t u32Parity; /*!< Parity format.
This parameter can be a value of @ref USART_Parity_Control */
uint32_t u32OverSampleBit; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Over_Sample_Bit */
uint32_t u32FirstBit; /*!< Significant bit.
This parameter can be a value of @ref USART_First_Bit */
uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Polarity */
uint32_t u32HWFlowControl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_uart_init_t;
/**
* @brief LIN mode initialization structure definition
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
*/
typedef struct {
uint32_t u32ClockSrc; /*!< Clock Source.
This parameter can be a value of @ref USART_Clock_Source */
uint32_t u32ClockDiv; /*!< Clock division.
This parameter can be a value of @ref USART_Clock_Division. */
uint32_t u32CKOutput; /*!< USART_CK output selection.
This parameter can be a value of @ref USART_CK_Output_Selection. */
uint32_t u32Baudrate; /*!< USART baudrate.
This parameter is valid when clock source is the internal clock. */
uint32_t u32OverSampleBit; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Over_Sample_Bit */
uint32_t u32BmcClockDiv; /*!< BMC clock division.
This parameter can be a value of @ref USART_LIN_BMC_Clock_Division.
@note The clock division is valid when clock source is the internal clock. */
uint32_t u32DetectBreakLen; /*!< Detect break length.
This parameter can be a value of @ref USART_LIN_Detect_Break_Length */
uint32_t u32SendBreakLen; /*!< Send break length.
This parameter can be a value of @ref USART_LIN_Send_Break_Length */
uint32_t u32SendBreakMode; /*!< Send break mode.
This parameter can be a value of @ref USART_LIN_Send_Break_Mode */
} stc_usart_lin_init_t;
/**
* @brief Smartcard mode initialization structure definition
*/
typedef struct {
uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division.
@note This parameter is valid when clock source is the internal clock. */
uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection.
@note This parameter is valid when clock source is the internal clock. */
uint32_t u32Baudrate; /*!< USART baudrate.
This parameter is calculated according with smartcard default ETU and clock. */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bit */
uint32_t u32FirstBit; /*!< Significant bit.
This parameter can be a value of @ref USART_First_Bit */
} stc_usart_smartcard_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup USART_Global_Macros USART Global Macros
* @{
*/
/**
* @defgroup USART_Flag USART Flag
* @{
*/
#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */
#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */
#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */
#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */
#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */
#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */
#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */
#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */
#define USART_FLAG_LIN_ERR (USART_SR_BE) /*!< LIN bus error flag */
#define USART_FLAG_LIN_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */
#define USART_FLAG_LIN_BREAK (USART_SR_LBD) /*!< LIN break signal detection flag */
#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \
USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \
USART_FLAG_TX_CPLT | USART_FLAG_LIN_BREAK | USART_FLAG_LIN_WKUP | \
USART_FLAG_LIN_ERR | USART_FLAG_MX_PROCESSOR)
/**
* @}
*/
/**
* @defgroup USART_Transmission_Type USART Transmission Type
* @{
*/
#define USART_TRANS_DATA (0UL)
#define USART_TRANS_ID (USART_DR_MPID)
/**
* @}
*/
/**
* @defgroup USART_Function USART Function
* @{
*/
#define USART_TX (USART_CR1_TE) /*!< USART TX function */
#define USART_RX (USART_CR1_RE) /*!< USART RX function */
#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */
#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */
#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */
#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timerout function */
#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */
#define USART_LIN (USART_CR2_LINEN << 16UL) /*!< USART LIN function */
#define USART_LIN_WKUP (USART_CR2_WKUPE << 16UL) /*!< USART LIN wakeup signal detect function */
#define USART_LIN_ERR (USART_CR2_BEE << 16UL) /*!< USART LIN bus error detect function */
#define USART_LIN_BREAK (USART_CR2_LBDL << 16UL) /*!< USART LIN bus break field detect function */
#define USART_LIN_INT_ERR (USART_CR2_BEIE << 16UL) /*!< USART LIN bus error detect interrupt function */
#define USART_LIN_INT_BREAK (USART_CR2_LBDIE << 16UL) /*!< USART LIN bus break field detect interrupt function */
#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE << 16UL) /*!< USART LIN bus wakeup signal detect interrupt function */
#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \
USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY | USART_LIN | USART_LIN_WKUP | \
USART_LIN_ERR | USART_LIN_BREAK | USART_LIN_INT_ERR | USART_LIN_INT_BREAK | \
USART_LIN_INT_WKUP)
/**
* @}
*/
/**
* @defgroup USART_Parity_Control USART Parity Control
* @{
*/
#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */
#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */
#define USART_PARITY_ODD (USART_CR1_PCE | \
USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/**
* @defgroup USART_Data_Width_Bit USART Data Width Bit
* @{
*/
#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */
#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */
/**
* @}
*/
/**
* @defgroup USART_Over_Sample_Bit USART Over Sample Bit
* @{
*/
#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */
#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */
/**
* @}
*/
/**
* @defgroup USART_First_Bit USART First Bit
* @{
*/
#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */
#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */
/**
* @}
*/
/**
* @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity
* @{
*/
#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */
#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */
/**
* @}
*/
/**
* @defgroup USART_Clock_Source USART Clock Source
* @{
*/
#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */
#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */
/**
* @}
*/
/**
* @defgroup USART_CK_Output_Selection USART_CK Output Selection
* @{
*/
#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */
#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */
/**
* @}
*/
/**
* @defgroup USART_Stop_Bit USART Stop Bit
* @{
*/
#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */
#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */
/**
* @}
*/
/**
* @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control
* @{
*/
#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */
#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */
#define USART_HW_FLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow controle */
#define USART_HW_FLOWCTRL_RTS_CTS (USART_HW_FLOWCTRL_CTS | \
USART_HW_FLOWCTRL_RTS) /*!< USART hardware flow control RTS and CTS mode */
/**
* @}
*/
/**
* @defgroup USART_Clock_Division USART Clock Division
* @{
*/
#define USART_CLK_DIV1 (0UL) /*!< CLK */
#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */
#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */
#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */
/**
* @}
*/
/**
* @defgroup USART_Max_Timeout USART Max Timeout
* @{
*/
#define USART_MAX_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock
* @{
*/
#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */
#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */
#define USART_SC_ETU_CLK128 (2UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */
#define USART_SC_ETU_CLK256 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */
#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */
/**
* @}
*/
/**
* @defgroup USART_Stop_Mode_Noise_Filter_Width_Level USART Stop Mode Noise Filter Width Level
* @{
*/
#define USART_STOP_MD_FILTER_LVL1 (0UL) /*!< Filter width level 1 */
#define USART_STOP_MD_FILTER_LVL2 (PERIC_USART1_NFC_USASRT1_NFS_0) /*!< Filter width level 2 */
#define USART_STOP_MD_FILTER_LVL3 (PERIC_USART1_NFC_USASRT1_NFS_1) /*!< Filter width level 3 */
#define USART_STOP_MD_FILTER_LVL4 (PERIC_USART1_NFC_USASRT1_NFS) /*!< Filter width level 4 */
/**
* @}
*/
/**
* @defgroup USART_LIN_BMC_Clock_Division USART LIN Baudrate Measure Counter Clock Division
* @{
*/
#define USART_LIN_BMC_CLK_DIV1 (0UL) /*!< CLK */
#define USART_LIN_BMC_CLK_DIV2 (USART_PR_LBMPSC_0) /*!< CLK/2 */
#define USART_LIN_BMC_CLK_DIV4 (USART_PR_LBMPSC_1) /*!< CLK/4 */
#define USART_LIN_BMC_CLK_DIV8 (USART_PR_LBMPSC) /*!< CLK/8 */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode
* @{
*/
#define USART_LIN_SEND_BREAK_MD_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */
#define USART_LIN_SEND_BREAK_MD_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */
/**
* @}
*/
/**
* @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length
* @{
*/
#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */
#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length
* @{
*/
#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */
#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */
#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */
#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup USART_Global_Functions
* @{
*/
int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit);
int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx,
const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error);
int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit);
int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx,
const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error);
int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit);
int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error);
int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx,
const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error);
int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit);
int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error);
int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit);
int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx,
const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error);
void USART_DeInit(CM_USART_TypeDef *USARTx);
void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState);
en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag);
void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag);
void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity);
void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit);
void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit);
void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth);
void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit);
void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity);
void USART_SetTransType(CM_USART_TypeDef *USARTx, uint32_t u32Type);
void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv);
uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx);
void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc);
uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx);
void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl);
uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx);
void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data);
void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID);
int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error);
/* Smartcard function */
void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock);
void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level);
void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv);
void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx);
en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx);
void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode);
uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx);
uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx);
uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx);
void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len);
void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len);
int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[],
uint32_t u32Len, uint32_t u32Timeout);
/**
* @}
*/
#endif /* LL_USART_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_USART_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32_ll_usb.h Normal file
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@ -0,0 +1,671 @@
/**
*******************************************************************************
* @file hc32_ll_usb.h
* @brief A detailed description is available at hardware registers
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_USB_H__
#define __HC32_LL_USB_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
#include "usb_app_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_USB
* @{
*/
#if (LL_USB_ENABLE == DDL_ON)
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
#define USB_MAX_TX_FIFOS (16U)
#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS)
#define USB_MAX_EP_NUM (16U)
#define USB_MAX_EP0_SIZE (64U)
/* working mode of the USB core */
#define DEVICE_MODE (0U)
#define HOST_MODE (1U)
/* Macro definations for device mode*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS)
/* EP type */
#define EP_TYPE_CTRL (0U)
#define EP_TYPE_ISOC (1U)
#define EP_TYPE_BULK (2U)
#define EP_TYPE_INTR (3U)
#define EP_TYPE_MSK (3U)
/* USB port speed */
#define PRTSPD_FULL_SPEED (1U)
#define PRTSPD_LOW_SPEED (2U)
/* PHY clock */
#define HCFG_30_60_MHZ (0U)
#define HCFG_48_MHZ (1U)
#define HCFG_6_MHZ (2U)
#define USB_EP_TX_DIS (0x0000U)
#define USB_EP_TX_STALL (0x0010U)
#define USB_EP_TX_NAK (0x0020U)
#define USB_EP_TX_VALID (0x0030U)
#define USB_EP_RX_DIS (0x0000U)
#define USB_EP_RX_STALL (0x1000U)
#define USB_EP_RX_NAK (0x2000U)
#define USB_EP_RX_VALID (0x3000U)
#define USB_OK (0U)
#define USB_ERROR (1U)
#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS)
#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS)
#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS)
#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS)
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU))
#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U))
#ifdef USB_INTERNAL_DMA_ENABLED
#define __USB_ALIGN_END
#if defined (__GNUC__) /* GNU Compiler */
#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4)))
#elif defined (__CC_ARM) /* ARM Compiler */
#define __USB_ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __USB_ALIGN_BEGIN
#elif defined (__TASKING__) /* TASKING Compiler */
#define __USB_ALIGN_BEGIN __align(4)
#endif
#else
#define __USB_ALIGN_BEGIN
#define __USB_ALIGN_END
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
typedef struct {
__IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */
uint32_t Reserved04; /* Reserved 004h */
__IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /* Reset Register 010h */
__IO uint32_t GINTSTS; /* Interrupt Register 014h */
__IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
__IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h */
/* DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */
__IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */
uint32_t Reserved30[3]; /* Reserved 030h-038h */
__IO uint32_t CID; /* User ID Register 03Ch */
uint32_t Reserved40[5]; /* Reserved 040h-050h */
__IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */
uint32_t Reserved58[42]; /* Reserved 058h-0FCh */
__IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */
__IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */
} USB_CORE_GREGS;
typedef struct {
__IO uint32_t DCFG; /* Device Configuration Register 800h */
__IO uint32_t DCTL; /* Device Control Register 804h */
__IO uint32_t DSTS; /* Device Status Register (RO) 808h */
uint32_t Reserved0C; /* Reserved 80Ch */
__IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */
__IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */
__IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */
__IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */
uint32_t Reserved20[4]; /* Reserved 820h-82Ch */
__IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */
__IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */
__IO uint32_t DEACHINT; /* Deivce Each EP Interrupt Register 838h */
__IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */
uint32_t Reserved40; /* Reserved 840h */
__IO uint32_t DIEPEACHMSK1; /* Deveice IN EP1 Interrupt Mask Register 844h */
uint32_t Reserved48[15]; /* Reserved 848-880h */
__IO uint32_t DOEPEACHMSK1; /* Deveice OUT EP1 Interrupt Mask Register 884h */
} USB_CORE_DREGS;
typedef struct {
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
} USB_CORE_INEPREGS;
typedef struct {
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} USB_CORE_OUTEPREGS;
typedef struct {
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
} USB_CORE_HREGS;
typedef struct {
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
__IO uint32_t HCDMA;
uint32_t Reserved[2];
} USB_CORE_HC_REGS;
typedef struct { /* 000h */
USB_CORE_GREGS *GREGS;
USB_CORE_DREGS *DREGS;
USB_CORE_HREGS *HREGS;
USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS];
USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS];
USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS];
__IO uint32_t *HPRT;
__IO uint32_t *DFIFO[USB_MAX_TX_FIFOS];
__IO uint32_t *GCCTL;
} LL_USB_TypeDef;
typedef struct {
uint8_t host_chnum;
uint8_t dev_epnum;
uint8_t dmaen;
uint8_t low_power;
uint8_t phy_type;
uint8_t core_type;
} USB_CORE_BASIC_CFGS;
typedef struct {
uint8_t dev_addr;
uint8_t ep_idx;
uint8_t is_epin;
uint8_t ch_speed;
uint8_t do_ping;
uint8_t ep_type;
uint16_t max_packet;
uint8_t pid_type;
uint8_t in_toggle;
uint8_t out_toggle;
/* transaction level variables*/
uint32_t dma_addr;
uint32_t xfer_len;
uint32_t xfer_count;
uint8_t *xfer_buff;
} USB_HOST_CH;
typedef struct {
uint8_t epidx;
uint8_t ep_dir;
uint8_t trans_type;
uint8_t ep_stall;
uint8_t data_pid_start;
uint8_t datax_pid;
uint16_t tx_fifo_num;
uint32_t maxpacket;
/* Transfer level variables */
uint32_t rem_data_len;
uint32_t total_data_len;
uint32_t ctl_data_len;
/* transaction level variables*/
uint32_t dma_addr;
uint32_t xfer_len;
uint32_t xfer_count;
uint8_t *xfer_buff;
} USB_DEV_EP;
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup USB_Global_Functions
* @{
*/
/**
* @brief get the current mode of the usb core from the corresponding register
* @param [in] USBx usb instance
* @retval current mode 1: host mode 0: device mode
*/
__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx)
{
if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) {
return 1U;
} else {
return 0U;
}
}
/**
* @brief Initializes the normal interrupts
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx)
{
WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL);
WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM);
}
/**
* @brief clear all the pending device interrupt bits and mask the IN and OUT
* endpoint interrupts.
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx)
{
WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL);
WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL);
WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL);
WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL);
}
/**
* @brief generate a device connect signal to the USB host
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx)
{
CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS);
}
/**
* @brief test of mode processing
* @param [in] USBx usb instance
* @param [in] reg Register write
* @retval None
*/
__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg)
{
WRITE_REG32(USBx->DREGS->DCTL, reg);
}
/**
* @brief Enables the controller's Global interrupts in the AHB Configuration
* registers.
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx)
{
SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
}
/**
* @brief Disable the controller's Global interrupt in the AHB Configuration
* register.
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx)
{
CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
}
/**
* @brief Get the Core Interrupt bits from the interrupt register not including
* the bits that are masked.
* @param [in] USBx usb instance
* @retval status[32bits]
*/
__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx)
{
uint32_t v;
v = READ_REG32(USBx->GREGS->GINTSTS);
v &= READ_REG32(USBx->GREGS->GINTMSK);
return v;
}
/**
* @brief Get the out endpoint interrupt bits from the all endpoint interrupt
* register not including the bits masked.
* @param [in] USBx usb instance
* @retval The status that shows which OUT EP have interrupted.
*/
__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx)
{
uint32_t v;
v = READ_REG32(USBx->DREGS->DAINT);
v &= READ_REG32(USBx->DREGS->DAINTMSK);
return ((v & 0xFFFF0000UL) >> 16U);
}
/**
* @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the
* interrupt bits that are masked.
* @param [in] USBx usb instance
* @param [in] epnum end point index
* @retval all the interrupt bits on DOEPINTn while n = epnum
*/
__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum)
{
uint32_t v;
v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT);
v &= READ_REG32(USBx->DREGS->DOEPMSK);
return v;
}
/**
* @brief Get the IN endpoint interrupt bits from the all endpoint interrupt
* register not including the bits masked.
* @param [in] USBx usb instance
* @retval The status that shows which IN EP have interrupted.
*/
__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx)
{
uint32_t v;
v = READ_REG32(USBx->DREGS->DAINT);
v &= READ_REG32(USBx->DREGS->DAINTMSK);
return (v & 0xFFFFUL);
}
/**
* @brief Set the device a new address.
* @param [in] USBx usb instance
* @param [in] address device address which will be set to the corresponding register.
* @retval None
*/
__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address)
{
MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS);
}
/**
* @brief Select the USB PHY.
* @param [in] USBx usb instance
* @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
* @retval None
*/
__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
{
if (1U == PhyType) {
CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
//SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4); //todo 手册上没有该bit
} else {
SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
}
}
/**
* @brief Select the USB device PHY.
* @param [in] USBx usb instance
* @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
* @retval None
*/
__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
{
if (1U == PhyType) {
CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
} else {
SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
}
}
/**
* @brief USB DMA function command.
* @param [in] USBx usb instance
* @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable
* @retval None
*/
__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd)
{
MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS);
}
/**
* @brief USB burst length config.
* @param [in] USBx usb instance
* @param [in] len Burst length
* @retval None
*/
__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len)
{
MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS);
}
/**
* @brief USB frame interval config
* @param [in] USBx usb instance
* @param [in] interval Frame interval
* @retval None
*/
__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval)
{
MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval);
}
#ifdef USE_HOST_MODE
/**
* @brief Read the register HPRT and reset the following bits.
* @param [in] USBx usb instance
* @retval value of HPRT
*/
//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL)
__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx)
{
//todo don't have prtovrcurrchng bit
return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG));
}
/**
* @brief Issues a ping token
* @param [in] USBx usb instance
* @param [in] hc_num the host channel index
* @retval None
*/
//#define USBFS_HCTSIZ_DOPNG (0x80000000UL)
__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num)
{
//todo don't have dopng bit
WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS);
MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA);
}
/**
* @brief This function returns the frame number for sof packet
* @param [in] USBx usb instance
* @retval Frame number
*/
__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx)
{
return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL);
}
/**
* @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type
* @param [in] USBx usb instance
* @param [in] freq clock frequency
* @retval None
*/
__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq)
{
MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS);
}
/**
* @brief suspend the port
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx)
{
uint32_t u32hprt;
u32hprt = usb_rdhprt(USBx);
u32hprt |= USBFS_HPRT_PSUSP;
u32hprt &= ~USBFS_HPRT_PRES;
WRITE_REG32(*USBx->HPRT, u32hprt);
}
/**
* @brief control the enumeration speed of the core, this function make sure that
* the maximum speed supperted by the connected device.
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx)
{
CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS);
}
/**
* @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size
* @param [in] USBx usb instance
* @retval None
*/
__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx)
{
#ifdef USB_FS_MODE
/* USBFS Core*/
WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */
/* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */
WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
(RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
| (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
/* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */
WRITE_REG32(USBx->GREGS->HPTXFSIZ,
((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
| (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
#else
/* USBHS Core */
WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
(RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
| (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
WRITE_REG32(USBx->GREGS->HPTXFSIZ,
((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
| (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
#endif
}
/**
* @brief reset the channel whose channel number is ch_idx
* @param [in] USBx usb instance
* @param [in] ch_idx channel number
* @retval None
*/
__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx)
{
MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR,
USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR,
USBFS_HCCHAR_CHDIS);
}
#endif /* end of USE_HOST_MODE */
extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
extern void usb_setregaddr(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn);
extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num);
extern void usb_rxfifoflush(LL_USB_TypeDef *USBx);
extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode);
extern void usb_coresoftrst(LL_USB_TypeDef *USBx);
#ifdef USE_HOST_MODE
extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num);
extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
extern void usb_hprtrst(LL_USB_TypeDef *USBx);
extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State);
#endif
#ifdef USE_DEVICE_MODE
extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
extern void usb_ep0activate(LL_USB_TypeDef *USBx);
extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf);
extern void usb_remotewakeupen(LL_USB_TypeDef *USBx);
extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status);
extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum);
extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link);
#endif
/**
* @}
*/
#endif /* LL_USB_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_USB_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_utility.h
* @brief This file contains all the functions prototypes of the DDL utility.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_UTILITY_H__
#define __HC32_LL_UTILITY_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_UTILITY
* @{
*/
#if (LL_UTILITY_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup UTILITY_Global_Functions
* @{
*/
/* Imprecise delay */
void DDL_DelayMS(uint32_t u32Count);
void DDL_DelayUS(uint32_t u32Count);
/* Systick functions */
int32_t SysTick_Init(uint32_t u32Freq);
void SysTick_Delay(uint32_t u32Delay);
void SysTick_IncTick(void);
uint32_t SysTick_GetTick(void);
void SysTick_Suspend(void);
void SysTick_Resume(void);
#if (LL_PRINT_ENABLE == DDL_ON)
int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param));
#endif
/* You can add your own assert functions by implement the function DDL_AssertHandler
definition follow the function DDL_AssertHandler declaration */
#ifdef __DEBUG
#define DDL_ASSERT(x) \
do { \
((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \
} while (0)
/* Exported function */
void DDL_AssertHandler(const char *file, int line);
#else
#define DDL_ASSERT(x) ((void)0U)
#endif /* __DEBUG */
#if (LL_PRINT_ENABLE == DDL_ON)
#include <stdio.h>
__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData);
#define DDL_PrintfInit (void)LL_PrintfInit
#define DDL_Printf (void)printf
#else
#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit)
#define DDL_Printf(...)
#endif
/**
* @}
*/
#endif /* LL_UTILITY_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_UTILITY_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ll_wdt.h
* @brief This file contains all the functions prototypes of the WDT driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_LL_WDT_H__
#define __HC32_LL_WDT_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_WDT
* @{
*/
#if (LL_WDT_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup WDT_Global_Types WDT Global Types
* @{
*/
/**
* @brief WDT Init structure definition
*/
typedef struct {
uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT.
This parameter can be a value of @ref WDT_Count_Period */
uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT.
This parameter can be a value of @ref WDT_Clock_Division */
uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT.
This parameter can be a value of @ref WDT_Refresh_Range */
uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode).
This parameter can be a value of @ref WDT_LPM_Count */
uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT.
This parameter can be a value of @ref WDT_Exception_Type */
} stc_wdt_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup WDT_Global_Macros WDT Global Macros
* @{
*/
/**
* @defgroup WDT_Count_Period WDT Count Period
* @{
*/
#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */
#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */
#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup WDT_Clock_Division WDT Clock Division
* @{
*/
#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */
#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */
#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */
#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */
#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */
#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */
#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */
#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */
/**
* @}
*/
/**
* @defgroup WDT_Refresh_Range WDT Refresh Range
* @{
*/
#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */
#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */
#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */
#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */
#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */
#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */
#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */
#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */
#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */
#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */
#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */
#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */
#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */
#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */
#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */
/**
* @}
*/
/**
* @defgroup WDT_LPM_Count WDT Low Power Mode Count
* @brief Counting control of WDT in sleep mode.
* @{
*/
#define WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */
#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */
/**
* @}
*/
/**
* @defgroup WDT_Exception_Type WDT Exception Type
* @brief Specifies the exception response when a refresh error or count overflow occurs.
* @{
*/
#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */
/**
* @}
*/
/**
* @defgroup WDT_Flag WDT Flag
* @{
*/
#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */
#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */
#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup WDT_Global_Functions
* @{
*/
/**
* @brief Get WDT count value.
* @param None
* @retval uint16_t Count value
*/
__STATIC_INLINE uint16_t WDT_GetCountValue(void)
{
return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT);
}
/* Initialization and configuration functions */
int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
void WDT_FeedDog(void);
uint16_t WDT_GetCountValue(void);
/* Flags management functions */
en_flag_status_t WDT_GetStatus(uint32_t u32Flag);
int32_t WDT_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* LL_WDT_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_LL_WDT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32f4a0_ll_interrupts_share.h Normal file
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@ -0,0 +1,583 @@
/**
*******************************************************************************
* @file hc32f4a0_ll_interrupts_share.h
* @brief This file contains all the functions prototypes of the interrupt driver
* library.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_LL_SHARE_INTERRUPTS_H__
#define __HC32F4A0_LL_SHARE_INTERRUPTS_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @addtogroup LL_HC32F4A0_SHARE_INTERRUPTS
* @{
*/
#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup Share_Interrupts_Global_Functions
* @{
*/
int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState);
void IRQ128_Handler(void);
void IRQ129_Handler(void);
void IRQ130_Handler(void);
void IRQ131_Handler(void);
void IRQ132_Handler(void);
void IRQ133_Handler(void);
void IRQ134_Handler(void);
void IRQ135_Handler(void);
void IRQ136_Handler(void);
void IRQ137_Handler(void);
void IRQ138_Handler(void);
void IRQ139_Handler(void);
void IRQ140_Handler(void);
void IRQ141_Handler(void);
void IRQ142_Handler(void);
void IRQ143_Handler(void);
void EXTINT00_IrqHandler(void);
void EXTINT01_IrqHandler(void);
void EXTINT02_IrqHandler(void);
void EXTINT03_IrqHandler(void);
void EXTINT04_IrqHandler(void);
void EXTINT05_IrqHandler(void);
void EXTINT06_IrqHandler(void);
void EXTINT07_IrqHandler(void);
void EXTINT08_IrqHandler(void);
void EXTINT09_IrqHandler(void);
void EXTINT10_IrqHandler(void);
void EXTINT11_IrqHandler(void);
void EXTINT12_IrqHandler(void);
void EXTINT13_IrqHandler(void);
void EXTINT14_IrqHandler(void);
void EXTINT15_IrqHandler(void);
void DMA1_TC0_IrqHandler(void);
void DMA1_TC1_IrqHandler(void);
void DMA1_TC2_IrqHandler(void);
void DMA1_TC3_IrqHandler(void);
void DMA1_TC4_IrqHandler(void);
void DMA1_TC5_IrqHandler(void);
void DMA1_TC6_IrqHandler(void);
void DMA1_TC7_IrqHandler(void);
void DMA1_BTC0_IrqHandler(void);
void DMA1_BTC1_IrqHandler(void);
void DMA1_BTC2_IrqHandler(void);
void DMA1_BTC3_IrqHandler(void);
void DMA1_BTC4_IrqHandler(void);
void DMA1_BTC5_IrqHandler(void);
void DMA1_BTC6_IrqHandler(void);
void DMA1_BTC7_IrqHandler(void);
void DMA1_Error0_IrqHandler(void);
void DMA1_Error1_IrqHandler(void);
void DMA1_Error2_IrqHandler(void);
void DMA1_Error3_IrqHandler(void);
void DMA1_Error4_IrqHandler(void);
void DMA1_Error5_IrqHandler(void);
void DMA1_Error6_IrqHandler(void);
void DMA1_Error7_IrqHandler(void);
void DMA2_TC0_IrqHandler(void);
void DMA2_TC1_IrqHandler(void);
void DMA2_TC2_IrqHandler(void);
void DMA2_TC3_IrqHandler(void);
void DMA2_TC4_IrqHandler(void);
void DMA2_TC5_IrqHandler(void);
void DMA2_TC6_IrqHandler(void);
void DMA2_TC7_IrqHandler(void);
void DMA2_BTC0_IrqHandler(void);
void DMA2_BTC1_IrqHandler(void);
void DMA2_BTC2_IrqHandler(void);
void DMA2_BTC3_IrqHandler(void);
void DMA2_BTC4_IrqHandler(void);
void DMA2_BTC5_IrqHandler(void);
void DMA2_BTC6_IrqHandler(void);
void DMA2_BTC7_IrqHandler(void);
void DMA2_Error0_IrqHandler(void);
void DMA2_Error1_IrqHandler(void);
void DMA2_Error2_IrqHandler(void);
void DMA2_Error3_IrqHandler(void);
void DMA2_Error4_IrqHandler(void);
void DMA2_Error5_IrqHandler(void);
void DMA2_Error6_IrqHandler(void);
void DMA2_Error7_IrqHandler(void);
void EFM_ProgramEraseError_IrqHandler(void);
void EFM_ColError_IrqHandler(void);
void EFM_OpEnd_IrqHandler(void);
void QSPI_Error_IrqHandler(void);
void MAU_Sqrt_IrqHandler(void);
void DVP_FrameStart_IrqHandler(void);
void DVP_FrameEnd_IrqHandler(void);
void DVP_LineStart_IrqHandler(void);
void DVP_LineEnd_IrqHandler(void);
void DVP_SWSyncError_IrqHandler(void);
void DVP_FifoError_IrqHandler(void);
void FMAC1_IrqHandler(void);
void FMAC2_IrqHandler(void);
void FMAC3_IrqHandler(void);
void FMAC4_IrqHandler(void);
void DCU1_IrqHandler(void);
void DCU2_IrqHandler(void);
void DCU3_IrqHandler(void);
void DCU4_IrqHandler(void);
void DCU5_IrqHandler(void);
void DCU6_IrqHandler(void);
void DCU7_IrqHandler(void);
void DCU8_IrqHandler(void);
void TMR0_1_CmpA_IrqHandler(void);
void TMR0_1_CmpB_IrqHandler(void);
void TMR0_2_CmpA_IrqHandler(void);
void TMR0_2_CmpB_IrqHandler(void);
void TMR2_1_CmpA_IrqHandler(void);
void TMR2_1_CmpB_IrqHandler(void);
void TMR2_1_OvfA_IrqHandler(void);
void TMR2_1_OvfB_IrqHandler(void);
void TMR2_2_CmpA_IrqHandler(void);
void TMR2_2_CmpB_IrqHandler(void);
void TMR2_2_OvfA_IrqHandler(void);
void TMR2_2_OvfB_IrqHandler(void);
void TMR2_3_CmpA_IrqHandler(void);
void TMR2_3_CmpB_IrqHandler(void);
void TMR2_3_OvfA_IrqHandler(void);
void TMR2_3_OvfB_IrqHandler(void);
void TMR2_4_CmpA_IrqHandler(void);
void TMR2_4_CmpB_IrqHandler(void);
void TMR2_4_OvfA_IrqHandler(void);
void TMR2_4_OvfB_IrqHandler(void);
void RTC_TimeStamp0_IrqHandler(void);
void RTC_TimeStamp1_IrqHandler(void);
void RTC_Alarm_IrqHandler(void);
void RTC_Period_IrqHandler(void);
void CLK_XtalStop_IrqHandler(void);
void SWDT_IrqHandler(void);
void WDT_IrqHandler(void);
void PWC_WakeupTimer_IrqHandler(void);
void TMR6_1_GCmpA_IrqHandler(void);
void TMR6_1_GCmpB_IrqHandler(void);
void TMR6_1_GCmpC_IrqHandler(void);
void TMR6_1_GCmpD_IrqHandler(void);
void TMR6_1_GCmpE_IrqHandler(void);
void TMR6_1_GCmpF_IrqHandler(void);
void TMR6_1_GOvf_IrqHandler(void);
void TMR6_1_GUdf_IrqHandler(void);
void TMR6_1_GDte_IrqHandler(void);
void TMR6_1_SCmpUpA_IrqHandler(void);
void TMR6_1_SCmpDownA_IrqHandler(void);
void TMR6_1_SCmpUpB_IrqHandler(void);
void TMR6_1_SCmpDownB_IrqHandler(void);
void TMR6_2_GCmpA_IrqHandler(void);
void TMR6_2_GCmpB_IrqHandler(void);
void TMR6_2_GCmpC_IrqHandler(void);
void TMR6_2_GCmpD_IrqHandler(void);
void TMR6_2_GCmpE_IrqHandler(void);
void TMR6_2_GCmpF_IrqHandler(void);
void TMR6_2_GOvf_IrqHandler(void);
void TMR6_2_GUdf_IrqHandler(void);
void TMR6_2_GDte_IrqHandler(void);
void TMR6_2_SCmpUpA_IrqHandler(void);
void TMR6_2_SCmpDownA_IrqHandler(void);
void TMR6_2_SCmpUpB_IrqHandler(void);
void TMR6_2_SCmpDownB_IrqHandler(void);
void TMR6_3_GCmpA_IrqHandler(void);
void TMR6_3_GCmpB_IrqHandler(void);
void TMR6_3_GCmpC_IrqHandler(void);
void TMR6_3_GCmpD_IrqHandler(void);
void TMR6_3_GCmpE_IrqHandler(void);
void TMR6_3_GCmpF_IrqHandler(void);
void TMR6_3_GOvf_IrqHandler(void);
void TMR6_3_GUdf_IrqHandler(void);
void TMR6_3_GDte_IrqHandler(void);
void TMR6_3_SCmpUpA_IrqHandler(void);
void TMR6_3_SCmpDownA_IrqHandler(void);
void TMR6_3_SCmpUpB_IrqHandler(void);
void TMR6_3_SCmpDownB_IrqHandler(void);
void TMR6_4_GCmpA_IrqHandler(void);
void TMR6_4_GCmpB_IrqHandler(void);
void TMR6_4_GCmpC_IrqHandler(void);
void TMR6_4_GCmpD_IrqHandler(void);
void TMR6_4_GCmpE_IrqHandler(void);
void TMR6_4_GCmpF_IrqHandler(void);
void TMR6_4_GOvf_IrqHandler(void);
void TMR6_4_GUdf_IrqHandler(void);
void TMR6_4_Gdte_IrqHandler(void);
void TMR6_4_SCmpUpA_IrqHandler(void);
void TMR6_4_SCmpDownA_IrqHandler(void);
void TMR6_4_SCmpUpB_IrqHandler(void);
void TMR6_4_SCmpDownB_IrqHandler(void);
void TMR6_5_GCmpA_IrqHandler(void);
void TMR6_5_GCmpB_IrqHandler(void);
void TMR6_5_GCmpC_IrqHandler(void);
void TMR6_5_GCmpD_IrqHandler(void);
void TMR6_5_GCmpE_IrqHandler(void);
void TMR6_5_GCmpF_IrqHandler(void);
void TMR6_5_GOvf_IrqHandler(void);
void TMR6_5_GUdf_IrqHandler(void);
void TMR6_5_Gdte_IrqHandler(void);
void TMR6_5_SCmpUpA_IrqHandler(void);
void TMR6_5_SCmpDownA_IrqHandler(void);
void TMR6_5_SCmpUpB_IrqHandler(void);
void TMR6_5_SCmpDownB_IrqHandler(void);
void TMR6_6_GCmpA_IrqHandler(void);
void TMR6_6_GCmpB_IrqHandler(void);
void TMR6_6_GCmpC_IrqHandler(void);
void TMR6_6_GCmpD_IrqHandler(void);
void TMR6_6_GCmpE_IrqHandler(void);
void TMR6_6_GCmpF_IrqHandler(void);
void TMR6_6_GOvf_IrqHandler(void);
void TMR6_6_GUdf_IrqHandler(void);
void TMR6_6_Gdte_IrqHandler(void);
void TMR6_6_SCmpUpA_IrqHandler(void);
void TMR6_6_SCmpDownA_IrqHandler(void);
void TMR6_6_SCmpUpB_IrqHandler(void);
void TMR6_6_SCmpDownB_IrqHandler(void);
void TMR6_7_GCmpA_IrqHandler(void);
void TMR6_7_GCmpB_IrqHandler(void);
void TMR6_7_GCmpC_IrqHandler(void);
void TMR6_7_GCmpD_IrqHandler(void);
void TMR6_7_GCmpE_IrqHandler(void);
void TMR6_7_GCmpF_IrqHandler(void);
void TMR6_7_GOvf_IrqHandler(void);
void TMR6_7_GUdf_IrqHandler(void);
void TMR6_7_Gdte_IrqHandler(void);
void TMR6_7_SCmpUpA_IrqHandler(void);
void TMR6_7_SCmpDownA_IrqHandler(void);
void TMR6_7_SCmpUpB_IrqHandler(void);
void TMR6_7_SCmpDownB_IrqHandler(void);
void TMR6_8_GCmpA_IrqHandler(void);
void TMR6_8_GCmpB_IrqHandler(void);
void TMR6_8_GCmpC_IrqHandler(void);
void TMR6_8_GCmpD_IrqHandler(void);
void TMR6_8_GCmpE_IrqHandler(void);
void TMR6_8_GCmpF_IrqHandler(void);
void TMR6_8_GOvf_IrqHandler(void);
void TMR6_8_GUdf_IrqHandler(void);
void TMR6_8_Gdte_IrqHandler(void);
void TMR6_8_SCmpUpA_IrqHandler(void);
void TMR6_8_SCmpDownA_IrqHandler(void);
void TMR6_8_SCmpUpB_IrqHandler(void);
void TMR6_8_SCmpDownB_IrqHandler(void);
void TMR4_1_GCmpUH_IrqHandler(void);
void TMR4_1_GCmpUL_IrqHandler(void);
void TMR4_1_GCmpVH_IrqHandler(void);
void TMR4_1_GCmpVL_IrqHandler(void);
void TMR4_1_GCmpWH_IrqHandler(void);
void TMR4_1_GCmpWL_IrqHandler(void);
void TMR4_1_Ovf_IrqHandler(void);
void TMR4_1_Udf_IrqHandler(void);
void TMR4_1_ReloadU_IrqHandler(void);
void TMR4_1_ReloadV_IrqHandler(void);
void TMR4_1_ReloadW_IrqHandler(void);
void TMR4_2_GCmpUH_IrqHandler(void);
void TMR4_2_GCmpUL_IrqHandler(void);
void TMR4_2_GCmpVH_IrqHandler(void);
void TMR4_2_GCmpVL_IrqHandler(void);
void TMR4_2_GCmpWH_IrqHandler(void);
void TMR4_2_GCmpWL_IrqHandler(void);
void TMR4_2_Ovf_IrqHandler(void);
void TMR4_2_Udf_IrqHandler(void);
void TMR4_2_ReloadU_IrqHandler(void);
void TMR4_2_ReloadV_IrqHandler(void);
void TMR4_2_ReloadW_IrqHandler(void);
void TMR4_3_GCmpUH_IrqHandler(void);
void TMR4_3_GCmpUL_IrqHandler(void);
void TMR4_3_GCmpVH_IrqHandler(void);
void TMR4_3_GCmpVL_IrqHandler(void);
void TMR4_3_GCmpWH_IrqHandler(void);
void TMR4_3_GCmpWL_IrqHandler(void);
void TMR4_3_Ovf_IrqHandler(void);
void TMR4_3_Udf_IrqHandler(void);
void TMR4_3_ReloadU_IrqHandler(void);
void TMR4_3_ReloadV_IrqHandler(void);
void TMR4_3_ReloadW_IrqHandler(void);
void TMRA_1_Ovf_IrqHandler(void);
void TMRA_1_Udf_IrqHandler(void);
void TMRA_1_Cmp1_IrqHandler(void);
void TMRA_1_Cmp2_IrqHandler(void);
void TMRA_1_Cmp3_IrqHandler(void);
void TMRA_1_Cmp4_IrqHandler(void);
void TMRA_2_Ovf_IrqHandler(void);
void TMRA_2_Udf_IrqHandler(void);
void TMRA_2_Cmp1_IrqHandler(void);
void TMRA_2_Cmp2_IrqHandler(void);
void TMRA_2_Cmp3_IrqHandler(void);
void TMRA_2_Cmp4_IrqHandler(void);
void TMRA_3_Ovf_IrqHandler(void);
void TMRA_3_Udf_IrqHandler(void);
void TMRA_3_Cmp1_IrqHandler(void);
void TMRA_3_Cmp2_IrqHandler(void);
void TMRA_3_Cmp3_IrqHandler(void);
void TMRA_3_Cmp4_IrqHandler(void);
void TMRA_4_Ovf_IrqHandler(void);
void TMRA_4_Udf_IrqHandler(void);
void TMRA_4_Cmp1_IrqHandler(void);
void TMRA_4_Cmp2_IrqHandler(void);
void TMRA_4_Cmp3_IrqHandler(void);
void TMRA_4_Cmp4_IrqHandler(void);
void TMRA_5_Ovf_IrqHandler(void);
void TMRA_5_Udf_IrqHandler(void);
void TMRA_5_Cmp1_IrqHandler(void);
void TMRA_5_Cmp2_IrqHandler(void);
void TMRA_5_Cmp3_IrqHandler(void);
void TMRA_5_Cmp4_IrqHandler(void);
void TMRA_6_Ovf_IrqHandler(void);
void TMRA_6_Udf_IrqHandler(void);
void TMRA_6_Cmp1_IrqHandler(void);
void TMRA_6_Cmp2_IrqHandler(void);
void TMRA_6_Cmp3_IrqHandler(void);
void TMRA_6_Cmp4_IrqHandler(void);
void TMRA_7_Ovf_IrqHandler(void);
void TMRA_7_Udf_IrqHandler(void);
void TMRA_7_Cmp1_IrqHandler(void);
void TMRA_7_Cmp2_IrqHandler(void);
void TMRA_7_Cmp3_IrqHandler(void);
void TMRA_7_Cmp4_IrqHandler(void);
void TMRA_8_Ovf_IrqHandler(void);
void TMRA_8_Udf_IrqHandler(void);
void TMRA_8_Cmp1_IrqHandler(void);
void TMRA_8_Cmp2_IrqHandler(void);
void TMRA_8_Cmp3_IrqHandler(void);
void TMRA_8_Cmp4_IrqHandler(void);
void TMRA_9_Ovf_IrqHandler(void);
void TMRA_9_Udf_IrqHandler(void);
void TMRA_9_Cmp1_IrqHandler(void);
void TMRA_9_Cmp2_IrqHandler(void);
void TMRA_9_Cmp3_IrqHandler(void);
void TMRA_9_Cmp4_IrqHandler(void);
void TMRA_10_Ovf_IrqHandler(void);
void TMRA_10_Udf_IrqHandler(void);
void TMRA_10_Cmp1_IrqHandler(void);
void TMRA_10_Cmp2_IrqHandler(void);
void TMRA_10_Cmp3_IrqHandler(void);
void TMRA_10_Cmp4_IrqHandler(void);
void TMRA_11_Ovf_IrqHandler(void);
void TMRA_11_Udf_IrqHandler(void);
void TMRA_11_Cmp1_IrqHandler(void);
void TMRA_11_Cmp2_IrqHandler(void);
void TMRA_11_Cmp3_IrqHandler(void);
void TMRA_11_Cmp4_IrqHandler(void);
void TMRA_12_Ovf_IrqHandler(void);
void TMRA_12_Udf_IrqHandler(void);
void TMRA_12_Cmp1_IrqHandler(void);
void TMRA_12_Cmp2_IrqHandler(void);
void TMRA_12_Cmp3_IrqHandler(void);
void TMRA_12_Cmp4_IrqHandler(void);
void EMB_GR0_IrqHandler(void);
void EMB_GR1_IrqHandler(void);
void EMB_GR2_IrqHandler(void);
void EMB_GR3_IrqHandler(void);
void EMB_GR4_IrqHandler(void);
void EMB_GR5_IrqHandler(void);
void EMB_GR6_IrqHandler(void);
void USART1_RxError_IrqHandler(void);
void USART1_RxFull_IrqHandler(void);
void USART1_TxEmpty_IrqHandler(void);
void USART1_TxComplete_IrqHandler(void);
void USART1_RxTO_IrqHandler(void);
void USART2_RxError_IrqHandler(void);
void USART2_RxFull_IrqHandler(void);
void USART2_TxEmpty_IrqHandler(void);
void USART2_TxComplete_IrqHandler(void);
void USART2_RxTO_IrqHandler(void);
void USART3_RxError_IrqHandler(void);
void USART3_RxFull_IrqHandler(void);
void USART3_TxEmpty_IrqHandler(void);
void USART3_TxComplete_IrqHandler(void);
void USART4_RxError_IrqHandler(void);
void USART4_RxFull_IrqHandler(void);
void USART4_TxEmpty_IrqHandler(void);
void USART4_TxComplete_IrqHandler(void);
void USART5_LinBreakField_IrqHandler(void);
void USART5_LinWakeup_IrqHandler(void);
void USART5_RxError_IrqHandler(void);
void USART5_RxFull_IrqHandler(void);
void USART5_TxEmpty_IrqHandler(void);
void USART5_TxComplete_IrqHandler(void);
void USART6_RxError_IrqHandler(void);
void USART6_RxFull_IrqHandler(void);
void USART6_TxEmpty_IrqHandler(void);
void USART6_TxComplete_IrqHandler(void);
void USART6_RxTO_IrqHandler(void);
void USART7_RxError_IrqHandler(void);
void USART7_RxFull_IrqHandler(void);
void USART7_TxEmpty_IrqHandler(void);
void USART7_TxComplete_IrqHandler(void);
void USART7_RxTO_IrqHandler(void);
void USART8_RxError_IrqHandler(void);
void USART8_RxFull_IrqHandler(void);
void USART8_TxEmpty_IrqHandler(void);
void USART8_TxComplete_IrqHandler(void);
void USART9_RxError_IrqHandler(void);
void USART9_RxFull_IrqHandler(void);
void USART9_TxEmpty_IrqHandler(void);
void USART9_TxComplete_IrqHandler(void);
void USART10_LinBreakField_IrqHandler(void);
void USART10_LinWakeup_IrqHandler(void);
void USART10_RxError_IrqHandler(void);
void USART10_RxFull_IrqHandler(void);
void USART10_TxEmpty_IrqHandler(void);
void USART10_TxComplete_IrqHandler(void);
void SPI1_RxFull_IrqHandler(void);
void SPI1_TxEmpty_IrqHandler(void);
void SPI1_Error_IrqHandler(void);
void SPI1_Idle_IrqHandler(void);
void SPI2_RxFull_IrqHandler(void);
void SPI2_TxEmpty_IrqHandler(void);
void SPI2_Error_IrqHandler(void);
void SPI2_Idle_IrqHandler(void);
void SPI3_RxFull_IrqHandler(void);
void SPI3_TxEmpty_IrqHandler(void);
void SPI3_Error_IrqHandler(void);
void SPI3_Idle_IrqHandler(void);
void SPI4_RxFull_IrqHandler(void);
void SPI4_TxEmpty_IrqHandler(void);
void SPI4_Error_IrqHandler(void);
void SPI4_Idle_IrqHandler(void);
void SPI5_RxFull_IrqHandler(void);
void SPI5_TxEmpty_IrqHandler(void);
void SPI5_Error_IrqHandler(void);
void SPI5_Idle_IrqHandler(void);
void SPI6_RxFull_IrqHandler(void);
void SPI6_TxEmpty_IrqHandler(void);
void SPI6_Error_IrqHandler(void);
void SPI6_Idle_IrqHandler(void);
void CAN1_IrqHandler(void);
void CAN2_IrqHandler(void);
void I2S1_Tx_IrqHandler(void);
void I2S1_Rx_IrqHandler(void);
void I2S1_Error_IrqHandler(void);
void I2S2_Tx_IrqHandler(void);
void I2S2_Rx_IrqHandler(void);
void I2S2_Error_IrqHandler(void);
void I2S3_Tx_IrqHandler(void);
void I2S3_Rx_IrqHandler(void);
void I2S3_Error_IrqHandler(void);
void I2S4_Tx_IrqHandler(void);
void I2S4_Rx_IrqHandler(void);
void I2S4_Error_IrqHandler(void);
void USBFS_Global_IrqHandler(void);
void SDIOC1_Normal_IrqHandler(void);
void SDIOC1_Error_IrqHandler(void);
void SDIOC2_Normal_IrqHandler(void);
void SDIOC2_Error_IrqHandler(void);
void ETH_Global_IrqHandler(void);
void ETH_Wakeup_IrqHandler(void);
void I2C1_RxFull_IrqHandler(void);
void I2C1_TxComplete_IrqHandler(void);
void I2C1_TxEmpty_IrqHandler(void);
void I2C1_Error_IrqHandler(void);
void I2C2_RxFull_IrqHandler(void);
void I2C2_TxComplete_IrqHandler(void);
void I2C2_TxEmpty_IrqHandler(void);
void I2C2_Error_IrqHandler(void);
void I2C3_RxFull_IrqHandler(void);
void I2C3_TxComplete_IrqHandler(void);
void I2C3_TxEmpty_IrqHandler(void);
void I2C3_Error_IrqHandler(void);
void I2C4_RxFull_IrqHandler(void);
void I2C4_TxComplete_IrqHandler(void);
void I2C4_TxEmpty_IrqHandler(void);
void I2C4_Error_IrqHandler(void);
void I2C5_RxFull_IrqHandler(void);
void I2C5_TxComplete_IrqHandler(void);
void I2C5_TxEmpty_IrqHandler(void);
void I2C5_Error_IrqHandler(void);
void I2C6_RxFull_IrqHandler(void);
void I2C6_TxComplete_IrqHandler(void);
void I2C6_TxEmpty_IrqHandler(void);
void I2C6_Error_IrqHandler(void);
void PWC_LVD1_IrqHandler(void);
void PWC_LVD2_IrqHandler(void);
void FCM_Error_IrqHandler(void);
void FCM_End_IrqHandler(void);
void FCM_Ovf_IrqHandler(void);
void CTC_Udf_IrqHandler(void);
void CTC_Ovf_IrqHandler(void);
void ADC1_SeqA_IrqHandler(void);
void ADC1_SeqB_IrqHandler(void);
void ADC1_Cmp0_IrqHandler(void);
void ADC1_Cmp1_IrqHandler(void);
void ADC1_CmpComb_IrqHandler(void);
void ADC2_SeqA_IrqHandler(void);
void ADC2_SeqB_IrqHandler(void);
void ADC2_Cmp0_IrqHandler(void);
void ADC2_Cmp1_IrqHandler(void);
void ADC2_CmpComb_IrqHandler(void);
void ADC3_SeqA_IrqHandler(void);
void ADC3_SeqB_IrqHandler(void);
void ADC3_Cmp0_IrqHandler(void);
void ADC3_Cmp1_IrqHandler(void);
void ADC3_CmpComb_IrqHandler(void);
void NFC_IrqHandler(void);
/**
* @}
*/
#endif /* LL_INTERRUPTS_SHARE_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_LL_SHARE_INTERRUPTS_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

66
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32f4xx.h Normal file
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/**
*******************************************************************************
* @file hc32f4xx.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_H__
#define __HC32F4XX_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
/**
* @brief HC32F4xx Device Include
*/
#if defined(HC32F4A0)
#include <hc32f4a0.h>
#include <system_hc32f4a0.h>
#else
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/inc/hc32f4xx_conf.h Normal file
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/**
*******************************************************************************
* @file template/source/hc32f4xx_conf.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
Date Author Notes
2022-04-28 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_CONF_H__
#define __HC32F4XX_CONF_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @brief This is the list of modules to be used in the Device Driver Library.
* Select the modules you need to use to DDL_ON.
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
* properly.
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
* Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CAN_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_DMC_ENABLE (DDL_ON)
#define LL_DVP_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_ETH_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_FMAC_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_HRPWM_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_I2S_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MAU_ENABLE (DDL_ON)
#define LL_MDIO_ENABLE (DDL_OFF)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_NFC_ENABLE (DDL_ON)
#define LL_OTS_ENABLE (DDL_ON)
#define LL_PLA_ENABLE (DDL_OFF)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SDIOC_ENABLE (DDL_ON)
#define LL_SMC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR2_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_USB_ENABLE (DDL_ON)
#define LL_VREF_ENABLE (DDL_OFF)
#define LL_WDT_ENABLE (DDL_ON)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F4A0_LQFP176 (1U)
#define BSP_EV_HC32F4A0_LQFP176_MEM (2U)
#define BSP_EV_HC32F460_LQFP100_V1 (3U)
#define BSP_EV_HC32F460_LQFP100_V2 (4U)
#define BSP_EV_HC32F451_LQFP100 (5U)
#define BSP_EV_HC32F452_LQFP100 (6U)
#define BSP_EV_HC32F472_LQFP100 (7U)
#define BSP_SK_HC32F4A0_LQFP100 (8U)
/**
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
* in use.
* The value should be set to one of the list of currently supported BSP boards.
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U.
*/
#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON.
*/
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_CY62167EV30LL_ENABLE (DDL_OFF)
#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF)
#define BSP_IS62WV51216_ENABLE (DDL_OFF)
#define BSP_MT29F2G08AB_ENABLE (DDL_OFF)
#define BSP_NT35510_ENABLE (DDL_OFF)
#define BSP_OV5640_ENABLE (DDL_OFF)
#define BSP_S29GL064N90TFI03_ENABLE (DDL_OFF)
#define BSP_TCA9539_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_WM8731_ENABLE (DDL_OFF)
/**
* @brief Ethernet and PHY Configuration.
*/
/* MAC ADDRESS */
#define ETH_MAC_ADDR0 (0x02U)
#define ETH_MAC_ADDR1 (0x00U)
#define ETH_MAC_ADDR2 (0x00U)
#define ETH_MAC_ADDR3 (0x00U)
#define ETH_MAC_ADDR4 (0x00U)
#define ETH_MAC_ADDR5 (0x00U)
/* PHY(RTL8201F) Address*/
#define ETH_PHY_ADDR (0x00U)
/* PHY Configuration delay(ms) */
#define ETH_PHY_RST_DELAY (0x0080UL)
#define ETH_PHY_CONFIG_DELAY (0x0040UL)
#define ETH_PHY_RD_TIMEOUT (0x0005UL)
#define ETH_PHY_WR_TIMEOUT (0x0005UL)
/* Common PHY Registers */
#define PHY_BCR (0x00U) /*!< Basic Control Register */
#define PHY_BSR (0x01U) /*!< Basic Status Register */
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< SET the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< SET the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< SET the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< SET the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
/**
* @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0).
* @note Set value to non-zero if re-define main function.
*/
#define RE_DEFINE_MAIN (0)
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_CONF_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/src/Makefile Normal file
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SRC_FILES := hc32_ll.c hc32_ll_clk.c hc32_ll_icg.c hc32_ll_utility.c hc32_ll_fcg.c hc32_ll_interrupts.c hc32_ll_pwc.c hc32_ll_aos.c hc32_ll_sram.c hc32_ll_efm.c hc32f4a0_ll_interrupts_share.c hc32_ll_gpio.c hc32_ll_rmu.c hc32_ll_tmr0.c hc32_ll_dma.c
ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_FILES += hc32_ll_usart.c
endif
ifeq ($(CONFIG_BSP_USING_ADC),y)
SRC_FILES += hc32_ll_adc.c
endif
ifeq ($(CONFIG_BSP_USING_DAC),y)
SRC_FILES += hc32_ll_dac.c hc32_ll_mau.c
endif
ifeq ($(CONFIG_BSP_USING_SDIO),y)
SRC_FILES += hc32_ll_sdioc.c
endif
ifeq ($(CONFIG_BSP_USING_SPI),y)
SRC_FILES += hc32_ll_spi.c
endif
ifeq ($(CONFIG_BSP_USING_QSPI_FLASH),y)
SRC_FILES += hc32_ll_qspi.c
endif
ifeq ($(CONFIG_BSP_USING_I2C),y)
SRC_FILES += hc32_ll_i2c.c
endif
ifeq ($(CONFIG_BSP_USING_LWIP),y)
SRC_FILES += hc32_ll_eth.c
endif
ifeq ($(CONFIG_BSP_USING_USB),y)
SRC_FILES += hc32_ll_usb.c
endif
ifeq ($(CONFIG_BSP_USING_RTC),y)
SRC_FILES += hc32_ll_rtc.c
endif
ifeq ($(CONFIG_BSP_USING_WDT),y)
SRC_FILES += hc32_ll_wdt.c
endif
ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_FILES += hc32_ll_can.c
endif
include $(KERNEL_ROOT)/compiler.mk

170
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/**
*******************************************************************************
* @file hc32_ll.c
* @brief This file provides firmware functions to low-level drivers (LL).
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll.h"
#include "hc32_ll_utility.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @defgroup LL_Global Global
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup LL_Global_Functions LL Global Functions
* @{
*/
void LL_PERIPH_WE(uint32_t u32Peripheral)
{
#if (LL_EFM_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) {
/* Unlock all EFM registers */
EFM_REG_Unlock();
}
#endif
#if (LL_FCG_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) {
/* Unlock FCG register */
PWC_FCG0_REG_Unlock();
}
#endif
#if (LL_GPIO_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) {
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_REG_Unlock();
}
#endif
#if (LL_MPU_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) {
/* Unlock all MPU registers */
MPU_REG_Unlock();
}
#endif
#if (LL_PWC_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) {
/* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_REG_Unlock(PWC_UNLOCK_CODE2);
}
#endif
#if (LL_PWC_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) {
/* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1);
}
#endif
#if (LL_SRAM_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) {
/* Unlock SRAM register: WTCR, CKCR */
SRAM_REG_Unlock();
}
#endif
}
void LL_PERIPH_WP(uint32_t u32Peripheral)
{
#if (LL_EFM_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) {
/* Lock all EFM registers */
EFM_REG_Lock();
}
#endif
#if (LL_FCG_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) {
/* Lock FCG register */
PWC_FCG0_REG_Lock();
}
#endif
#if (LL_GPIO_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) {
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_REG_Lock();
}
#endif
#if (LL_MPU_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) {
/* Lock all MPU registers */
MPU_REG_Lock();
}
#endif
#if (LL_PWC_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) {
/* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_REG_Lock(PWC_UNLOCK_CODE2);
}
#endif
#if (LL_PWC_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) {
/* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1);
}
#endif
#if (LL_SRAM_ENABLE == DDL_ON)
if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) {
/* Lock SRAM register: WTCR, CKCR */
SRAM_REG_Lock();
}
#endif
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/src/hc32_ll_aes.c Normal file
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/**
*******************************************************************************
* @file hc32_ll_aes.c
* @brief This file provides firmware functions to manage the Advanced Encryption
* Standard(AES).
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_aes.h"
#include "hc32_ll_utility.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @defgroup LL_AES AES
* @brief AES Driver Library
* @{
*/
#if (LL_AES_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AES_Local_Macros AES Local Macros
* @{
*/
/* Delay count for timeout */
#define AES_TIMEOUT (30000UL)
/* AES block size */
#define AES_BLOCK_SIZE (16U)
/**
* @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity
* @{
*/
#define IS_AES_KEY_SIZE(x) \
( ((x) == AES_KEY_SIZE_16BYTE) || \
((x) == AES_KEY_SIZE_24BYTE) || \
((x) == AES_KEY_SIZE_32BYTE))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup AES_Local_Functions AES Local Functions
* @{
*/
/**
* @brief Write the input buffer in data register.
* @param [in] pu8SrcData Point to the source data buffer.
* @retval None
*/
static void AES_WriteData(const uint8_t *pu8SrcData)
{
uint8_t i;
__IO uint32_t *regDR = &CM_AES->DR0;
const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData);
for (i = 0U; i < 4U; i++) {
regDR[i] = pu32Data[i];
}
}
/**
* @brief Read the from data register.
* @param [out] pu8Result Point to the result buffer.
* @retval None
*/
static void AES_ReadData(uint8_t *pu8Result)
{
uint8_t i;
__IO uint32_t *regDR = &CM_AES->DR0;
uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result);
for (i = 0U; i < 4U; i++) {
pu32Result[i] = regDR[i];
}
}
/**
* @brief Write the input buffer in key register.
* @param [in] pu8Key Pointer to the key buffer.
* @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
* @retval None
*/
static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize)
{
uint8_t i;
uint8_t u8KeyWordSize = u8KeySize / 4U;
__IO uint32_t *regKR = &CM_AES->KR0;
const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key);
for (i = 0U; i < u8KeyWordSize; i++) {
regKR[i] = pu32Key[i];
}
switch (u8KeySize) {
case 16U:
u8KeySize = 0U;
break;
case 24U:
u8KeySize = 1U;
break;
case 32U:
u8KeySize = 2U;
break;
default:
break;
}
MODIFY_REG32(CM_AES->CR, AES_CR_KEYSIZE, ((uint32_t)u8KeySize << AES_CR_KEYSIZE_POS));
}
/**
* @brief Wait AES operation done.
* @param None
* @retval None
*/
static int32_t AES_WaitDone(void)
{
__IO uint32_t u32TimeCount = 0UL;
int32_t i32Ret = LL_OK;
while (bCM_AES->CR_b.START != 0UL) {
if (u32TimeCount++ >= AES_TIMEOUT) {
i32Ret = LL_ERR_TIMEOUT;
break;
}
}
return i32Ret;
}
/**
* @}
*/
/**
* @defgroup AES_Global_Functions AES Global Functions
* @{
*/
/**
* @brief AES encryption.
* @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted).
* @param [in] u32PlaintextSize Length of plaintext in bytes.
* @param [in] pu8Key Pointer to the AES key.
* @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
* @param [out] pu8Ciphertext Buffer of the ciphertext.
* @retval int32_t:
* - LL_OK: Encrypt successfully.
* - LL_ERR_INVD_PARAM: Invalid parameter.
* - LL_TIMEOUT: Encrypt timeout.
*/
int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize,
const uint8_t *pu8Key, uint8_t u8KeySize,
uint8_t *pu8Ciphertext)
{
int32_t i32Ret = LL_ERR_INVD_PARAM;
uint32_t u32Index = 0UL;
DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize));
DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U);
if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \
(pu8Key != NULL) && (pu8Ciphertext != NULL)) {
AES_WriteKey(pu8Key, u8KeySize);
/* Set AES encrypt. */
WRITE_REG32(bCM_AES->CR_b.MODE, 0UL);
while (u32Index < u32PlaintextSize) {
AES_WriteData(&pu8Plaintext[u32Index]);
/* Start AES calculating. */
WRITE_REG32(bCM_AES->CR_b.START, 1UL);
/* Wait for AES to stop */
i32Ret = AES_WaitDone();
if (i32Ret != LL_OK) {
break;
}
AES_ReadData(&pu8Ciphertext[u32Index]);
u32Index += AES_BLOCK_SIZE;
}
}
return i32Ret;
}
/**
* @brief AES decryption.
* @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted).
* @param [in] u32CiphertextSize Length of ciphertext in bytes.
* @param [in] pu8Key Pointer to the AES key.
* @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
* @param [out] pu8Plaintext Buffer of the plaintext.
* @retval int32_t:
* - LL_OK: Decrypt successfully.
* - LL_ERR_INVD_PARAM: Invalid parameter.
* - LL_TIMEOUT: Decrypt timeout.
*/
int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize,
const uint8_t *pu8Key, uint8_t u8KeySize,
uint8_t *pu8Plaintext)
{
int32_t i32Ret = LL_ERR_INVD_PARAM;
uint32_t u32Index = 0UL;
DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize));
DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U);
if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \
(pu8Key != NULL) && (pu8Ciphertext != NULL)) {
AES_WriteKey(pu8Key, u8KeySize);
/* Set AES decrypt. */
WRITE_REG32(bCM_AES->CR_b.MODE, 1UL);
while (u32Index < u32CiphertextSize) {
AES_WriteData(&pu8Ciphertext[u32Index]);
/* Start AES calculating. */
WRITE_REG32(bCM_AES->CR_b.START, 1UL);
/* Wait for AES to stop */
i32Ret = AES_WaitDone();
if (i32Ret != LL_OK) {
break;
}
AES_ReadData(&pu8Plaintext[u32Index]);
u32Index += AES_BLOCK_SIZE;
}
}
return i32Ret;
}
/**
* @}
*/
#endif /* LL_AES_ENABLE */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

194
Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/common/hc32_ll_driver/src/hc32_ll_aos.c Normal file
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@ -0,0 +1,194 @@
/**
*******************************************************************************
* @file hc32_ll_aos.c
* @brief This file provides firmware functions to manage the AOS.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_aos.h"
#include "hc32_ll_utility.h"
/**
* @addtogroup LL_Driver
* @{
*/
/**
* @defgroup LL_AOS AOS
* @brief AOS Driver Library
* @{
*/
#if (LL_AOS_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AOS_Local_Macros AOS Local Macros
* @{
*/
/**
* @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity
* @{
*/
#define IS_AOS_COMM_TRIG(x) \
( ((x) != 0UL) && \
((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK)
/**
* @}
*/
/**
* @defgroup AOS_Trigger_Select_Validity AOS Trigger Select Validity
* @{
*/
#define IS_AOS_TRIG_SEL(x) \
( ((x) == AOS_DCU1) || \
((x) == AOS_DCU2) || \
((x) == AOS_DCU3) || \
((x) == AOS_DCU4) || \
((x) == AOS_DMA1_0) || \
((x) == AOS_DMA1_1) || \
((x) == AOS_DMA1_2) || \
((x) == AOS_DMA1_3) || \
((x) == AOS_DMA1_4) || \
((x) == AOS_DMA1_5) || \
((x) == AOS_DMA1_6) || \
((x) == AOS_DMA1_7) || \
((x) == AOS_DMA2_0) || \
((x) == AOS_DMA2_1) || \
((x) == AOS_DMA2_2) || \
((x) == AOS_DMA2_3) || \
((x) == AOS_DMA2_4) || \
((x) == AOS_DMA2_5) || \
((x) == AOS_DMA2_6) || \
((x) == AOS_DMA2_7) || \
((x) == AOS_DMA_RC) || \
((x) == AOS_TMR6_0) || \
((x) == AOS_TMR6_1) || \
((x) == AOS_TMR6_2) || \
((x) == AOS_TMR6_3) || \
((x) == AOS_EVTPORT12) || \
((x) == AOS_EVTPORT34) || \
((x) == AOS_TMR0) || \
((x) == AOS_TMR2) || \
((x) == AOS_HASH_A) || \
((x) == AOS_HASH_B) || \
((x) == AOS_TMRA_0) || \
((x) == AOS_TMRA_1) || \
((x) == AOS_TMRA_2) || \
((x) == AOS_TMRA_3) || \
((x) == AOS_OTS) || \
((x) == AOS_ADC1_0) || \
((x) == AOS_ADC1_1) || \
((x) == AOS_ADC2_0) || \
((x) == AOS_ADC2_1) || \
((x) == AOS_ADC3_0) || \
((x) == AOS_ADC3_1) || \
((x) == AOS_COMM_1) || \
((x) == AOS_COMM_2))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup AOS_Global_Functions AOS Global Functions
* @{
*/
/**
* @brief Event Port Hardware trigger common event function command
* @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details
* @param [in] u32CommonTrigger Common trigger ID
* This parameter can be one of the following values:
* @arg AOS_COMM_TRIG1: Common trigger 1.
* @arg AOS_COMM_TRIG2: Common trigger 2.
* @param [in] enNewState An @ref en_functional_state_t enumeration value.
* @retval None
*/
void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel));
DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
if (ENABLE == enNewState) {
SET_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger);
} else {
CLR_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger);
}
}
/**
* @brief Event Port Hardware trigger common event function command
* @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details
* @param [in] enEvent Event source configuration, @ref en_event_src_t in details
* @retval None
*/
void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent)
{
DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel));
MODIFY_REG32(*(__IO uint32_t *)u32TriggerSel, AOS_TRIG_SEL_MASK, enEvent);
}
/**
* @}
*/
#endif /* LL_AOS_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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