forked from yystopf/xiuos
Modify USB Device Initialization in xHCI code and Command TRB code to apply to XiZi AIOT.
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2eba5a8071
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77bed3c28f
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@ -38,6 +38,10 @@ Modification: rewrite xhci functions to dock with USB core layer, so that the US
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2. Date: 2024-06-24
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Author: AIIT XUOS Lab
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Modification: rewrite xhci function usbh_get_port_speed to dock with USB core layer.
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3. Date: 2024-08-05
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Author: AIIT XUOS Lab
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Modification: Modify USB Device Initialization in xHCI code to apply to XiZi AIOT.
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*************************************************/
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#include "usb_hc_xhci.h"
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#include "usbh_hub.h"
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@ -686,7 +690,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set
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return -EPIPE;
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}
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portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
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portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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switch (setup->wValue)
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{
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case HUB_PORT_FEATURE_ENABLE:
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@ -712,7 +716,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set
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uint32_t pclear = portsc & XHCI_PORTSC_RW_MASK;
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/* clear port status */
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writel(pclear, xhci->op + XHCI_OP_PORTSC ( port ));
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writel(pclear, xhci->op_addr + XHCI_OP_PORTSC ( port ));
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break;
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case HUB_REQUEST_SET_FEATURE:
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@ -740,7 +744,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set
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return -EPIPE;
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}
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portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
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portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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status = 0;
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if (portsc & XHCI_PORTSC_CSC)
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@ -750,7 +754,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set
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/* always clear all the status change bits */
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uint32_t temp = portsc & ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
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writel ( temp, xhci->op + XHCI_OP_PORTSC ( port ) );
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writel ( temp, xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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}
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if (portsc & XHCI_PORTSC_PEC)
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@ -816,12 +820,23 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set
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return 0;
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}
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// TODO:
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uint8_t xhci_usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port)
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{
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return 0;
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}
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USB_ASSERT(hub);
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struct usbh_bus *usb = hub->usb;
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USB_ASSERT(usb && usb->priv);
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struct xhci_host *xhci = usb->priv;
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if (hub->is_roothub) {
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return xhci_root_speed(xhci, port);
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} else {
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struct usbh_hubport *roothub_port = usbh_root_hub_port(&(hub->child[port]));
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/* TODO, hanlde TT for low-speed device on high-speed hub, but it doesn't matter, since
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we haven't well handle hub yet */
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USB_ASSERT(roothub_port);
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return xhci_root_speed(xhci, roothub_port->port);
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}
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}
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int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed){
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struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe;
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@ -29,6 +29,10 @@ History:
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1. Date: 2024-06-18
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Author: AIIT XUOS Lab
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Modification: replant and redefine some xhci data structure, so that the cherryUSB can adapt to XiZi AIOT.
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2. Date: 2024-08-05
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Author: AIIT XUOS Lab
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Modification: Modify Command TRB code to apply to XiZi AIOT.
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*************************************************/
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#include "usbh_core.h"
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@ -1265,7 +1269,7 @@ void xhci_remove ( struct xhci_host *xhci ) {
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* @ret rc Return status code
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*/
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int xhci_port_enable(struct xhci_host *xhci, uint32_t port) {
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uint32_t portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
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uint32_t portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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/* double check if connected */
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if (!(portsc & XHCI_PORTSC_CCS)) {
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@ -1281,7 +1285,7 @@ int xhci_port_enable(struct xhci_host *xhci, uint32_t port) {
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case XHCI_PORTSC_PLS_POLLING:
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/* A USB2 port - perform device reset */
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xhci_dump_port_status(port, portsc);
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writel ((portsc | XHCI_PORTSC_PR), (xhci->op + XHCI_OP_PORTSC ( port ))); /* reset port */
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writel ((portsc | XHCI_PORTSC_PR), (xhci->op_addr + XHCI_OP_PORTSC ( port ))); /* reset port */
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break;
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default:
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USB_LOG_ERR("PLS: %d \r\n", (portsc & XHCI_PORTSC_PLS_MASK));
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@ -1291,7 +1295,7 @@ int xhci_port_enable(struct xhci_host *xhci, uint32_t port) {
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/* Wait for device to complete reset and be enabled */
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uint32_t end = 1000U, start = 0U;
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for (;;) {
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portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
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portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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if (!(portsc & XHCI_PORTSC_CCS)) {
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/* USB 2.0 port would be disconnected after reset */
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USB_LOG_INFO("USB 2.0 port disconnected during reset, need rescan \r\n");
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@ -1455,7 +1459,7 @@ static int xhci_port_psiv ( struct xhci_host *xhci, unsigned int port,
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return -ENOTSUP;
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/* Get protocol speed ID count */
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ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
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ports = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PORTS );
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psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
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/* Use the default mappings if applicable */
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@ -1474,7 +1478,7 @@ static int xhci_port_psiv ( struct xhci_host *xhci, unsigned int port,
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/* Iterate over PSI dwords looking for a match */
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for ( i = 0 ; i < psic ; i++ ) {
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psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
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psi = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PSI ( i ));
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mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
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exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
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if ( xhci_speed_to_psi(speed) == XCHI_PSI ( mantissa, exponent ) ) {
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@ -1505,7 +1509,7 @@ uint32_t xhci_root_speed ( struct xhci_host *xhci, uint8_t port ) {
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unsigned int protocol = xhci_port_protocol(xhci, port);
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/* Read port status */
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portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
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portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) );
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USB_LOG_DBG("XHCI %s-%d status is 0x%08x, protocol 0x%x\n",
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xhci->name, port, portsc, protocol );
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ccs = ( portsc & XHCI_PORTSC_CCS );
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@ -1616,7 +1620,7 @@ int xhci_event_wait(struct xhci_host *xhci,
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static inline void xhci_doorbell ( struct xhci_host *xhci, uint32_t slotid, uint32_t value ) {
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DSB();
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BARRIER();
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writel ( value, xhci->db + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */
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writel ( value, xhci->db_addr + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */
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}
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/**
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@ -1793,14 +1797,25 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot,
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size_t len;
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void *input;
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int rc;
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uintptr_t input_vir;
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uintptr_t input_phy;
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/* Allocate an input context */
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len = xhci_input_context_offset ( xhci, XHCI_CTX_END );
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#if 0
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input = usb_align(xhci_align ( len ), len);
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if ( ! input ) {
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rc = -ENOMEM;
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goto err_alloc;
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}
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#endif
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rc = naive_mmap(&input_vir, &input_phy, len, false);
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if(rc != 0){
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USB_LOG_ERR("XHCI %s could not allocate xhci context\n", xhci->name );
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rc = -ENOMEM;
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goto err_alloc;
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}
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input = input_vir;
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memset ( input, 0, len );
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/* Populate input context */
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@ -1809,7 +1824,10 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot,
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/* Construct command */
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memset ( context, 0, sizeof ( *context ) );
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context->type = type;
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#if 0
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context->input = CPU_TO_LE64 ( ( (uintptr_t)input ) );
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#endif
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context->input = CPU_TO_LE64 ( ( (uintptr_t)input_phy ) );
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context->slot = slot->id;
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/* Issue command and wait for completion */
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@ -1983,7 +2001,7 @@ static int xhci_port_slot_type ( struct xhci_host *xhci, unsigned int port ) {
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return -ENOTSUP;
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/* Get slot type */
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slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
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slot = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_SLOT );
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type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
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return type;
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@ -2006,6 +2024,8 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl
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int rc;
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int id;
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size_t len;
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uintptr_t context_vir;
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uintptr_t context_phy;
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/* Determine applicable slot type */
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type = xhci_port_slot_type ( xhci, hport->port );
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@ -2043,16 +2063,30 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl
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/* Allocate a device context */
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len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
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#if 0
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slot->context = usb_align(xhci_align ( len ), len);
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if ( ! slot->context ) {
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rc = -ENOMEM;
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goto err_alloc_context;
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}
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#endif
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rc = naive_mmap(&context_addr, &context_phy, len, false);
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if(rc != 0){
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USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name );
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rc = -ENOMEM;
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goto err_alloc;
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}
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slot->context_vir = context_vir;
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slot->context_phy = context_phy;
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slot->context = (struct xhci_slot_context *)context_vir;
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memset ( slot->context, 0, len );
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/* Set device context base address */
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USB_ASSERT ( xhci->dcbaa.context[id] == 0 );
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#if 0
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xhci->dcbaa.context[id] = CPU_TO_LE64 ( ( (uintptr_t)slot->context ) );
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#endif
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xhci->dcbaa.context[id] = CPU_TO_LE64 ( ( (uintptr_t)slot->context_phy ) );
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USB_LOG_DBG("XHCI %s slot %d device context [%08lx,%08lx)\n",
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xhci->name, slot->id, ( slot->context ),
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@ -799,6 +799,8 @@ struct xhci_slot {
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unsigned int id;
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/** Slot context */
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struct xhci_slot_context *context;
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uintptr_t context_vir;
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uintptr_t context_phy;
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/** Route string */
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unsigned int route;
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