lr
200 lines
6.0 KiB
C
200 lines
6.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "hal_base.h"
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#include "hal_gmac.h"
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#include "hal_debug.h"
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#include "hal_cru.h"
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup GMAC
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* @{
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*/
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/** @defgroup GMAC_Private_Definition Private Definition
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* @{
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*/
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/********************* Private MACRO Definition ******************************/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_BIT(nr) (1 << (nr) | 1 << (nr+16))
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#define GRF_CLR_BIT(nr) (1 << (nr+16))
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#define DELAY_ENABLE(soc, tx, rx) \
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(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
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((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
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#define RK3568_GRF_GMAC0_CON0 0X0380
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#define RK3568_GRF_GMAC0_CON1 0X0384
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#define RK3568_GRF_GMAC1_CON0 0X0388
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#define RK3568_GRF_GMAC1_CON1 0X038c
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/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
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#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
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#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
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(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
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#define RK3568_GMAC_PHY_INTF_SEL_RMII \
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(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
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#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
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#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
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#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
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/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
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#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
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#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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/********************* Private Structure Definition **************************/
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/********************* Private Variable Definition ***************************/
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/********************* Private Function Definition ***************************/
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/** @} */
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/********************* Public Function Definition ****************************/
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/** @defgroup GMAC_Exported_Functions_Group5 Other Functions
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* @{
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*/
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/**
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* @brief Set RGMII Mode.
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* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
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* the information for GMAC module.
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* @param txDelay: RGMII tx delayline
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* @param rxDelay: RGMII rx delayline
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*/
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void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
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int32_t txDelay, int32_t rxDelay)
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{
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uint32_t *con0, *con1;
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con0 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON0) :
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&(GRF->MAC0_CON0));
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con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
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&(GRF->MAC0_CON1));
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WRITE_REG(*con1,
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RK3568_GMAC_PHY_INTF_SEL_RGMII |
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RK3568_GMAC_RXCLK_DLY_ENABLE |
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RK3568_GMAC_TXCLK_DLY_ENABLE);
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WRITE_REG(*con0,
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RK3568_GMAC_CLK_RX_DL_CFG(rxDelay) |
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RK3568_GMAC_CLK_TX_DL_CFG(txDelay));
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}
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/**
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* @brief Set RMII Mode.
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* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
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* the information for GMAC module.
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*/
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void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC)
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{
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uint32_t *con1, *cruCon, val;
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con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
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&(GRF->MAC0_CON1));
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WRITE_REG(*con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
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cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
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&(CRU->CRU_CLKSEL_CON[31]));
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/* RMII mode */
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val = HIWORD_UPDATE(0x1, 0x3, 0);
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/* clock from io if it was */
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/* val |= HIWORD_UPDATE(0x1, 0x1, 2); */
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/* ref clock sel 50M */
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val |= HIWORD_UPDATE(0x1, 0x3, 8);
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/* clock speed 25M */
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val |= HIWORD_UPDATE(0x1, 0x1, 3);
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WRITE_REG(*cruCon, val);
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}
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/**
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* @brief Set external clock source select.
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* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
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* the information for GMAC module.
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* @param extClk: 0: select clk_mac as the clock of mac
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* 1: select external phy clock as the clock of mac
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*/
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void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk)
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{
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uint32_t *cruCon, val;
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uint32_t clksel = 0;
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cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
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&(CRU->CRU_CLKSEL_CON[31]));
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if (extClk) {
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clksel = 1;
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}
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val = HIWORD_UPDATE(clksel, 0x1, 2);
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WRITE_REG(*cruCon, val);
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}
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/**
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* @brief Set RGMII speed.
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* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
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* the information for GMAC module.
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* @param speed: RGMII speed 10/100/1000
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*/
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void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
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{
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eCLOCK_Name clkID;
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uint32_t rate;
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int32_t ret;
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switch (speed) {
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case 10:
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rate = 2500000;
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break;
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case 100:
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rate = 25000000;
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break;
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case 1000:
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rate = 125000000;
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break;
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default:
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HAL_DBG_ERR("unknown speed value for GMAC speed=%ld", speed);
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return;
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}
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if (pGMAC->phyStatus.interface == PHY_INTERFACE_MODE_RMII) {
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clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RMII_SPEED :
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SCLK_GMAC0_RMII_SPEED;
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} else {
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clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RGMII_SPEED :
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SCLK_GMAC0_RGMII_SPEED;
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}
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ret = HAL_CRU_ClkSetFreq(clkID, rate);
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if (ret) {
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HAL_DBG_ERR("%s: set clk_mac_speed rate %ld failed %ld\n",
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__func__, rate, ret);
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}
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}
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/**
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* @brief Set RGMII speed.
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* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
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* the information for GMAC module.
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* @param speed: RGMII speed 10/100
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*/
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void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
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{
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HAL_GMAC_SetRGMIISpeed(pGMAC, speed);
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}
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