modify XiUOS DIR : (1.add plc_demo in APP_Framework/control_app; 2.add industrial_network、industrial_fieldbus and industrial_wlan; 3.add XiZi_AIoT and modify XiZi as XiZi_IIoT.)
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Liu_Weichao
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/*
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* Copyright 2017-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file board.h
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* @brief define imxrt1052-board init configure and start-up function
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-05-28
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*/
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/*************************************************
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File name: board.h
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Description: define imxrt1052-board board init function and struct
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Others:
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History:
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1. Date: 2021-05-28
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Author: AIIT XUOS Lab
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Modification:
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1. define imxrt-board InitBoardHardware
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2. define imxrt-board heap struct
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*************************************************/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include "fsl_common.h"
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#include "fsl_gpio.h"
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#include "fsl_clock.h"
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#include "fsl_enet.h"
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#include "clock_config.h"
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// #include <xizi.h>
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#include <arch_interrupt.h>
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extern int heap_start;
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extern int heap_end;
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#define HEAP_BEGIN (&heap_start)
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#define HEAP_END (&heap_end)
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#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
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void InitBoardHardware(void);
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief The board name */
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#define BOARD_NAME "IMXRT1050"
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/
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/*! @brief The ENET PHY address. */
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#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */
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/* USB PHY condfiguration */
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#define BOARD_USB_PHY_D_CAL (0x0CU)
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#define BOARD_USB_PHY_TXCAL45DP (0x06U)
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#define BOARD_USB_PHY_TXCAL45DM (0x06U)
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#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
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#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
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#define BOARD_ARDUINO_I2C_INDEX (1)
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#define BOARD_USDHC1_BASEADDR USDHC1
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#define BOARD_USDHC2_BASEADDR USDHC2
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#define BOARD_USDHC_CD_GPIO_BASE GPIO2
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#define BOARD_USDHC_CD_GPIO_PIN 28
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#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
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#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
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#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
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#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
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#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
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#define BOARD_USDHC_CD_GPIO_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalInput, \
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0, \
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kGPIO_IntRisingOrFallingEdge, \
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}; \
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GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
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GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
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GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
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}
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#define BOARD_HAS_SDCARD (1U)
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#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
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#define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
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#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
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#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
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#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalOutput, \
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0, \
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kGPIO_NoIntmode, \
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}; \
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GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
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GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
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}
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#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
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{ \
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gpio_pin_config_t sw_config = { \
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kGPIO_DigitalOutput, \
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0, \
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kGPIO_NoIntmode, \
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}; \
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GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
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}
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#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
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(GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
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#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
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#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
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#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
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#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
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#define BOARD_SD_HOST_IRQ USDHC1_IRQn
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#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
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#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
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#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
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#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
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#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
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/* we are using the BB SD socket to DEMO the MMC example,but the
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* SD socket provide 4bit bus only, so we define this macro to avoid
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* 8bit data bus test
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*/
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#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
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#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
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#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
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/* @Brief Board accelerator sensor configuration */
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#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
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/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
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#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
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/* Clock divider for LPI2C clock source */
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#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
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#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
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#define BOARD_CODEC_I2C_BASEADDR LPI2C1
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#define BOARD_CODEC_I2C_INSTANCE 1U
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#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
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#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
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#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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void BOARD_ConfigMPU(void);
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void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
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void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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#endif /* _BOARD_H_ */
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