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cortex m7 emulator

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This commit is contained in:
huang
2023-08-07 09:41:15 +08:00
parent b0eabde4f6
commit b481abd4eb
49 changed files with 11620 additions and 1 deletions
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Ubiquitous/XiZi_IIoT/arch/arm/Makefile
+5
View File
@@ -35,6 +35,11 @@ SRC_DIR := shared
SRC_DIR += cortex-m7
endif
ifeq ($(CONFIG_BOARD_CORTEX_V2M_EVB),y)
SRC_DIR := shared
SRC_DIR += cortex-m7
endif
ifeq ($(CONFIG_BOARD_IMXRT1176_SBC_EVB),y)
SRC_DIR := shared
SRC_DIR += cortex-m7
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/Makefile
+5
View File
@@ -1,3 +1,8 @@
ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y)
SRC_FILES := boot.S interrupt.c interrupt_vector.S
endif
ifeq ($(CONFIG_BOARD_CORTEX_V2M_EVB),y)
SRC_DIR += V2M
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := boot.S interrupt.c interrupt_vector.S
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/arch_interrupt.h
+39
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@@ -0,0 +1,39 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include <xs_base.h>
#define ARCH_MAX_IRQ_NUM (256)
//#define ARCH_IRQ_NUM_OFFSET 0
//#define SYSTICK_IRQN 15
//#define UART1_IRQn 36
//#define UART2_IRQn 37
#define ARCH_IRQ_NUM_OFFSET 16
#define SYSTICK_IRQN -1
#define UART0RX_IRQn 0
#define UART0TX_IRQn 1
#define UART1RX_IRQn 2
// #define USB1_IRQn 113
// #define USB2_IRQn 112
int32 ArchEnableHwIrq(uint32 irq_num);
int32 ArchDisableHwIrq(uint32 irq_num);
#endif
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S
+204
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@@ -0,0 +1,204 @@
/* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1052.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1052 */
/* @version: 1.0 */
/* @date: 2018-9-21 */
/* @build: b180921 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
/**
* @file boot.S
* @brief Cortex-M7 start function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: boot.S
Description: Contex-M7 start function function
Others: take startup_MIMXRT1052.s for references
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. add OS entry function
*************************************************/
.syntax unified
.arch armv7-m
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#ifdef __BOOTLOADER /* BOOT */
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr r0,=SystemInit
blx r0
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __bootloader_end: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LoopCopy0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LoopCopy0
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LoopCopy1:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LoopCopy1
ldr r0,=ota_entry
blx r0
#else /* APP */
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#if 1
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
ldr r0,=entry
blx r0
#endif /* MCUBOOT_BOOTLOADER */
.size Reset_Handler, . - Reset_Handler
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt.c
+89
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@@ -0,0 +1,89 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file interrupt.c
* @brief support arm cortex-m7 interrupt function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#include <xs_base.h>
#include <xs_isr.h>
#include "fsl_common.h"
x_base __attribute__((naked)) DisableLocalInterrupt()
{
asm volatile ("MRS r0, PRIMASK");
asm volatile ("CPSID I");
asm volatile ("BX LR ");
}
void __attribute__((naked)) EnableLocalInterrupt(x_base level)
{
asm volatile ("MSR PRIMASK, r0");
asm volatile ("BX LR");
}
int32 ArchEnableHwIrq(uint32 irq_num)
{
EnableIRQ(irq_num);
return EOK;
}
int32 ArchDisableHwIrq(uint32 irq_num)
{
DisableIRQ(irq_num);
return EOK;
}
extern void KTaskOsAssignAfterIrq(void *context);
void IsrEntry()
{
uint32 ipsr;
__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
if (ipsr!=17){
KPrintf("%d\n",ipsr);
}
isrManager.done->incCounter();
isrManager.done->handleIrq(ipsr);
KTaskOsAssignAfterIrq(NONE);
isrManager.done->decCounter();
}
void UsageFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
void BusFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
void NMI_Handler(int irqn, void *arg)
{
while (1)
{
}
}
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt_vector.S
+319
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@@ -0,0 +1,319 @@
/* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1052.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1052 */
/* @version: 1.0 */
/* @date: 2018-9-21 */
/* @build: b180921 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
/**
* @file interrupt_vector.S
* @brief vector table for Cortex M7
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: interrupt_vector.S
Description: vector table for a Cortex M7
Others:
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. add IsrEntry as default isr function
*************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Initial Stack Pointer */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFaultHandler /* Hard Fault Handler*/
.long MemFaultHandler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVC Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* Interrupts */
.long UART0RX_Handler /* 0 UART 0 receive interrupt */
.long UART0TX_Handler /* 1 UART 0 transmit interrupt */
.long UART1RX_Handler /* 2 UART 1 receive interrupt */
.long UART1TX_Handler /* 3 UART 1 transmit interrupt */
.long UART2RX_Handler /* 4 UART 2 receive interrupt */
.long UART2TX_Handler /* 5 UART 2 transmit interrupt */
.long GPIO0ALL_Handler /* 6 GPIO 0 combined interrupt */
.long GPIO1ALL_Handler /* 7 GPIO 1 combined interrupt */
.long TIMER0_Handler /* 8 Timer 0 interrupt */
.long TIMER1_Handler /* 9 Timer 1 interrupt */
.long DUALTIMER_Handler /* 10 Dual Timer interrupt */
.long SPI_0_1_Handler /* 11 SPI 0, 1 interrupt */
.long UART_0_1_2_OVF_Handler /* 12 UART overflow (0, 1 & 2) interrupt */
.long ETHERNET_Handler /* 13 Ethernet interrupt */
.long I2S_Handler /* 14 Audio I2S interrupt */
.long TOUCHSCREEN_Handler /* 15 Touch Screen interrupt */
.long GPIO2_Handler /* 16 GPIO 2 combined interrupt */
.long GPIO3_Handler /* 17 GPIO 3 combined interrupt */
.long UART3RX_Handler /* 18 UART 3 receive interrupt */
.long UART3TX_Handler /* 19 UART 3 transmit interrupt */
.long UART4RX_Handler /* 20 UART 4 receive interrupt */
.long UART4TX_Handler /* 21 UART 4 transmit interrupt */
.long SPI_2_Handler /* 22 SPI 2 interrupt */
.long SPI_3_4_Handler /* 23 SPI 3, 4 interrupt */
.long GPIO0_0_Handler /* 24 GPIO 0 individual interrupt ( 0) */
.long GPIO0_1_Handler /* 25 GPIO 0 individual interrupt ( 1) */
.long GPIO0_2_Handler /* 26 GPIO 0 individual interrupt ( 2) */
.long GPIO0_3_Handler /* 27 GPIO 0 individual interrupt ( 3) */
.long GPIO0_4_Handler /* 28 GPIO 0 individual interrupt ( 4) */
.long GPIO0_5_Handler /* 29 GPIO 0 individual interrupt ( 5) */
.long GPIO0_6_Handler /* 30 GPIO 0 individual interrupt ( 6) */
.long GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */
.long 0 /* 32 Reserved */
.long 0 /* 33 Reserved */
.long 0 /* 34 Reserved */
.long 0 /* 35 Reserved */
.long 0 /* 36 Reserved */
.long 0 /* 37 Reserved */
.long 0 /* 38 Reserved */
.long 0 /* 39 Reserved */
.long 0 /* 40 Reserved */
.long 0 /* 41 Reserved */
.long 0 /* 42 Reserved */
.long 0 /* 43 Reserved */
.long 0 /* 44 Reserved */
.long 0 /* 45 Reserved */
.long 0 /* 46 Reserved */
.long 0 /* 47 Reserved */
.long 0 /* 48 Reserved */
.long 0 /* 49 Reserved */
.long 0 /* 50 Reserved */
.long 0 /* 51 Reserved */
.long 0 /* 52 Reserved */
.long 0 /* 53 Reserved */
.long 0 /* 54 Reserved */
.long 0 /* 55 Reserved */
.long 0 /* 56 Reserved */
.long 0 /* 57 Reserved */
.long 0 /* 58 Reserved */
.long 0 /* 59 Reserved */
.long 0 /* 60 Reserved */
.long 0 /* 61 Reserved */
.long 0 /* 62 Reserved */
.long 0 /* 63 Reserved */
.long 0 /* 64 Reserved */
.long 0 /* 65 Reserved */
.long 0 /* 66 Reserved */
.long 0 /* 67 Reserved */
.long 0 /* 68 Reserved */
.long 0 /* 69 Reserved */
.long 0 /* 70 Reserved */
.long 0 /* 71 Reserved */
.long 0 /* 72 Reserved */
.long 0 /* 73 Reserved */
.long 0 /* 74 Reserved */
.long 0 /* 75 Reserved */
.long 0 /* 76 Reserved */
.long 0 /* 77 Reserved */
.long 0 /* 78 Reserved */
.long 0 /* 79 Reserved */
.long 0 /* 80 Reserved */
.long 0 /* 81 Reserved */
.long 0 /* 82 Reserved */
.long 0 /* 83 Reserved */
.long 0 /* 84 Reserved */
.long 0 /* 85 Reserved */
.long 0 /* 86 Reserved */
.long 0 /* 87 Reserved */
.long 0 /* 88 Reserved */
.long 0 /* 89 Reserved */
.long 0 /* 90 Reserved */
.long 0 /* 91 Reserved */
.long 0 /* 92 Reserved */
.long 0 /* 93 Reserved */
.long 0 /* 94 Reserved */
.long 0 /* 95 Reserved */
.long 0 /* 96 Reserved */
.long 0 /* 97 Reserved */
.long 0 /* 98 Reserved */
.long 0 /* 99 Reserved */
.long 0 /* 100 Reserved */
.long 0 /* 101 Reserved */
.long 0 /* 102 Reserved */
.long 0 /* 103 Reserved */
.long 0 /* 104 Reserved */
.long 0 /* 105 Reserved */
.long 0 /* 106 Reserved */
.long 0 /* 107 Reserved */
.long 0 /* 108 Reserved */
.long 0 /* 109 Reserved */
.long 0 /* 110 Reserved */
.long 0 /* 111 Reserved */
.long 0 /* 112 Reserved */
.long 0 /* 113 Reserved */
.long 0 /* 114 Reserved */
.long 0 /* 115 Reserved */
.long 0 /* 116 Reserved */
.long 0 /* 117 Reserved */
.long 0 /* 118 Reserved */
.long 0 /* 119 Reserved */
.long 0 /* 120 Reserved */
.long 0 /* 121 Reserved */
.long 0 /* 122 Reserved */
.long 0 /* 123 Reserved */
.long 0 /* 124 Reserved */
.long 0 /* 125 Reserved */
.long 0 /* 126 Reserved */
.long 0 /* 127 Reserved */
.long 0 /* 128 Reserved */
.long 0 /* 129 Reserved */
.long 0 /* 130 Reserved */
.long 0 /* 131 Reserved */
.long 0 /* 132 Reserved */
.long 0 /* 133 Reserved */
.long 0 /* 134 Reserved */
.long 0 /* 135 Reserved */
.long 0 /* 136 Reserved */
.long 0 /* 137 Reserved */
.long 0 /* 138 Reserved */
.long 0 /* 139 Reserved */
.long 0 /* 140 Reserved */
.long 0 /* 141 Reserved */
.long 0 /* 142 Reserved */
.long 0 /* 143 Reserved */
.long 0 /* 144 Reserved */
.long 0 /* 145 Reserved */
.long 0 /* 146 Reserved */
.long 0 /* 147 Reserved */
.long 0 /* 148 Reserved */
.long 0 /* 149 Reserved */
.long 0 /* 150 Reserved */
.long 0 /* 151 Reserved */
.long 0 /* 152 Reserved */
.long 0 /* 153 Reserved */
.long 0 /* 154 Reserved */
.long 0 /* 155 Reserved */
.long 0 /* 156 Reserved */
.long 0 /* 157 Reserved */
.long 0 /* 158 Reserved */
.long 0 /* 159 Reserved */
.long 0 /* 160 Reserved */
.long 0 /* 161 Reserved */
.long 0 /* 162 Reserved */
.long 0 /* 163 Reserved */
.long 0 /* 164 Reserved */
.long 0 /* 165 Reserved */
.long 0 /* 166 Reserved */
.long 0 /* 167 Reserved */
.long 0 /* 168 Reserved */
.long 0 /* 169 Reserved */
.long 0 /* 170 Reserved */
.long 0 /* 171 Reserved */
.long 0 /* 172 Reserved */
.long 0 /* 173 Reserved */
.long 0 /* 174 Reserved */
.long 0 /* 175 Reserved */
.long 0 /* 176 Reserved */
.long 0 /* 177 Reserved */
.long 0 /* 178 Reserved */
.long 0 /* 179 Reserved */
.long 0 /* 180 Reserved */
.long 0 /* 181 Reserved */
.long 0 /* 182 Reserved */
.long 0 /* 183 Reserved */
.long 0 /* 184 Reserved */
.long 0 /* 185 Reserved */
.long 0 /* 186 Reserved */
.long 0 /* 187 Reserved */
.long 0 /* 188 Reserved */
.long 0 /* 189 Reserved */
.long 0 /* 190 Reserved */
.long 0 /* 191 Reserved */
.long 0 /* 192 Reserved */
.long 0 /* 193 Reserved */
.long 0 /* 194 Reserved */
.long 0 /* 195 Reserved */
.long 0 /* 196 Reserved */
.long 0 /* 197 Reserved */
.long 0 /* 198 Reserved */
.long 0 /* 199 Reserved */
.long 0 /* 200 Reserved */
.long 0 /* 201 Reserved */
.long 0 /* 202 Reserved */
.long 0 /* 203 Reserved */
.long 0 /* 204 Reserved */
.long 0 /* 205 Reserved */
.long 0 /* 206 Reserved */
.long 0 /* 207 Reserved */
.long 0 /* 208 Reserved */
.long 0 /* 209 Reserved */
.long 0 /* 210 Reserved */
.long 0 /* 211 Reserved */
.long 0 /* 212 Reserved */
.long 0 /* 213 Reserved */
.long 0 /* 214 Reserved */
.long 0 /* 215 Reserved */
.long 0 /* 216 Reserved */
.long 0 /* 217 Reserved */
.long 0 /* 218 Reserved */
.long 0 /* 219 Reserved */
.long 0 /* 220 Reserved */
.long 0 /* 221 Reserved */
.long 0 /* 222 Reserved */
.long 0 /* 223 Reserved */
#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT
.long ARM_VSI0_Handler /* 224 VSI 0 interrupt */
.long ARM_VSI1_Handler /* 225 VSI 1 interrupt */
.long ARM_VSI2_Handler /* 226 VSI 2 interrupt */
.long ARM_VSI3_Handler /* 227 VSI 3 interrupt */
.long ARM_VSI4_Handler /* 228 VSI 4 interrupt */
.long ARM_VSI5_Handler /* 229 VSI 5 interrupt */
.long ARM_VSI6_Handler /* 230 VSI 6 interrupt */
.long ARM_VSI7_Handler /* 231 VSI 7 interrupt */
#else
.long 0 /* 224 reserved */
.long 0 /* 225 reserved */
.long 0 /* 226 reserved */
.long 0 /* 227 reserved */
.long 0 /* 228 reserved */
.long 0 /* 229 reserved */
.long 0 /* 230 reserved */
.long 0 /* 231 reserved */
#endif
.long 0 /* 232 reserved */
.long 0 /* 233 reserved */
.long 0 /* 234 reserved */
.long 0 /* 235 reserved */
.long 0 /* 236 reserved */
.long 0 /* 237 reserved */
.long 0 /* 238 reserved */
.long 0 /* 239 reserved */
.size __isr_vector, . - __isr_vector
.text
.thumb