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/*
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* Copyright?: (C)?2022?Phytium?Information?Technology,?Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: xhci_reg.h
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* Date: 2022-07-19 09:26:25
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* LastEditTime: 2022-07-19 09:26:25
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* Description: ?This file is for xhci register definition.
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*
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* Modify?History:
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* Ver???Who????????Date?????????Changes
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* -----?------?????--------????--------------------------------------
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* 1.0 zhugengyu 2022/9/19 init commit
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* 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub
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*/
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#ifndef XHCI_REG_H_
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#define XHCI_REG_H_
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#include <stdint.h>
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#if defined(__aarch64__)
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#define BITS_PER_LONG 64U
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#define XHCI_AARCH64
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#else
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#define BITS_PER_LONG 32U
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#define XHCI_AARCH32
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#endif
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#define XHCI_GENMASK(h, l) \
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(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#define XHCI_GENMASK_ULL(h, l) \
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(((~0ULL) - (1ULL << (l)) + 1) & \
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(~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
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#define XHCI32_GET_BITS(x, a, b) (uint32_t)((((uint32_t)(x)) & XHCI_GENMASK(a, b)) >> b)
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#define XHCI32_SET_BITS(x, a, b) (uint32_t)((((uint32_t)(x)) << b) & XHCI_GENMASK(a, b))
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#define XHCI64_GET_BITS(x, a, b) (uint64_t)((((uint64_t)(x)) & XHCI_GENMASK_ULL(a, b)) >> b)
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#define XHCI64_SET_BITS(x, a, b) (uint64_t)((((uint64_t)(x)) << b) & XHCI_GENMASK_ULL(a, b))
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/** Capability register length */
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#define XHCI_CAP_CAPLENGTH 0x00
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/** Host controller interface version number */
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#define XHCI_CAP_HCIVERSION 0x02
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/** Structural parameters 1 */
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#define XHCI_CAP_HCSPARAMS1 0x04
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/** Number of device slots */
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#define XHCI_HCSPARAMS1_SLOTS(params) ( ( (params) >> 0 ) & 0xff )
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/** Number of interrupters */
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#define XHCI_HCSPARAMS1_INTRS(params) ( ( (params) >> 8 ) & 0x3ff )
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/** Number of ports */
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#define XHCI_HCSPARAMS1_PORTS(params) ( ( (params) >> 24 ) & 0xff )
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/** Structural parameters 2 */
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#define XHCI_CAP_HCSPARAMS2 0x08
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/** Number of page-sized scratchpad buffers */
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#define XHCI_HCSPARAMS2_SCRATCHPADS(params) \
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( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )
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/** Capability parameters */
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#define XHCI_CAP_HCCPARAMS1 0x10
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/** 64-bit addressing capability */
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#define XHCI_HCCPARAMS1_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
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/** Context size shift */
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#define XHCI_HCCPARAMS1_CSZ_SHIFT(params) ( 5 + ( ( (params) >> 2 ) & 0x1 ) )
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/** xHCI extended capabilities pointer */
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#define XHCI_HCCPARAMS1_XECP(params) ( ( ( (params) >> 16 ) & 0xffff ) << 2 )
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/** Doorbell offset */
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#define XHCI_CAP_DBOFF 0x14
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/** Runtime register space offset */
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#define XHCI_CAP_RTSOFF 0x18
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/** xHCI extended capability ID */
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#define XHCI_XECP_ID(xecp) ( ( (xecp) >> 0 ) & 0xff )
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/** Next xHCI extended capability pointer */
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#define XHCI_XECP_NEXT(xecp) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )
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/** USB legacy support extended capability */
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#define XHCI_XECP_ID_LEGACY 1
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/** USB legacy support BIOS owned semaphore */
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#define XHCI_USBLEGSUP_BIOS 0x02
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/** USB legacy support BIOS ownership flag */
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#define XHCI_USBLEGSUP_BIOS_OWNED 0x01
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/** USB legacy support OS owned semaphore */
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#define XHCI_USBLEGSUP_OS 0x03
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/** USB legacy support OS ownership flag */
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#define XHCI_USBLEGSUP_OS_OWNED 0x01
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/** USB legacy support control/status */
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#define XHCI_USBLEGSUP_CTLSTS 0x04
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/** Supported protocol extended capability */
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#define XHCI_XECP_ID_SUPPORTED 2
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/** Supported protocol revision */
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#define XHCI_SUPPORTED_REVISION 0x00
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/** Supported protocol minor revision */
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#define XHCI_SUPPORTED_REVISION_VER(revision) ( ( (revision) >> 16 ) & 0xffff )
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/** Supported protocol name */
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#define XHCI_SUPPORTED_NAME 0x04
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/** Supported protocol ports */
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#define XHCI_SUPPORTED_PORTS 0x08
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/** Supported protocol port offset */
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#define XHCI_SUPPORTED_PORTS_OFFSET(ports) ( ( (ports) >> 0 ) & 0xff )
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/** Supported protocol port count */
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#define XHCI_SUPPORTED_PORTS_COUNT(ports) ( ( (ports) >> 8 ) & 0xff )
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/** Supported protocol PSI count */
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#define XHCI_SUPPORTED_PORTS_PSIC(ports) ( ( (ports) >> 28 ) & 0x0f )
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/** Supported protocol slot */
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#define XHCI_SUPPORTED_SLOT 0x0c
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/** Supported protocol slot type */
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#define XHCI_SUPPORTED_SLOT_TYPE(slot) ( ( (slot) >> 0 ) & 0x1f )
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/** Supported protocol PSI */
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#define XHCI_SUPPORTED_PSI(index) ( 0x10 + ( (index) * 4 ) )
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/** Supported protocol PSI value */
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#define XHCI_SUPPORTED_PSI_VALUE(psi) ( ( (psi) >> 0 ) & 0x0f )
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/** Supported protocol PSI mantissa */
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#define XHCI_SUPPORTED_PSI_MANTISSA(psi) ( ( (psi) >> 16 ) & 0xffff )
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/** Supported protocol PSI exponent */
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#define XHCI_SUPPORTED_PSI_EXPONENT(psi) ( ( (psi) >> 4 ) & 0x03 )
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/** Default PSI values */
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enum {
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/** Full speed (12Mbps) */
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XHCI_SPEED_FULL = 1,
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/** Low speed (1.5Mbps) */
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XHCI_SPEED_LOW = 2,
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/** High speed (480Mbps) */
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XHCI_SPEED_HIGH = 3,
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/** Super speed */
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XHCI_SPEED_SUPER = 4,
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};
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/** USB command register */
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#define XHCI_OP_USBCMD 0x00
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/** Run/stop */
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#define XHCI_USBCMD_RUN 0x00000001UL
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/* Interrupter Enable (INTE) 1: enabled - RW */
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#define XHCI_USBCMD_INTE (1UL << 2)
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/** Host controller reset */
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#define XHCI_USBCMD_HCRST 0x00000002UL
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/** USB status register */
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#define XHCI_OP_USBSTS 0x04
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/** Host controller halted */
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#define XHCI_USBSTS_HCH 0x00000001UL
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/** Interrupt Pending (IP) */
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#define XHCI_USBSTS_EINT (1UL << 3)
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/** Page size register */
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#define XHCI_OP_PAGESIZE 0x08
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/** Page size */
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#define XHCI_PAGESIZE(pagesize) ( (pagesize) << 12 )
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/** Device notifcation control register */
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#define XHCI_OP_DNCTRL 0x14
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/** Command ring control register */
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#define XHCI_OP_CRCR 0x18
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/** Command ring cycle state */
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#define XHCI_CRCR_RCS 0x00000001UL
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/** Command abort */
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#define XHCI_CRCR_CA 0x00000004UL
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/** Command ring running */
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#define XHCI_CRCR_CRR 0x00000008UL
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/** Device context base address array pointer */
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#define XHCI_OP_DCBAAP 0x30
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/** Configure register */
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#define XHCI_OP_CONFIG 0x38
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/** Maximum device slots enabled */
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#define XHCI_CONFIG_MAX_SLOTS_EN(slots) ( (slots) << 0 )
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/** Maximum device slots enabled mask */
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#define XHCI_CONFIG_MAX_SLOTS_EN_MASK \
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XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )
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/** Port status and control register */
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#define XHCI_OP_PORTSC(port) ( 0x400 - 0x10 + ( (port) << 4 ) )
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/** Current connect status */
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#define XHCI_PORTSC_CCS 0x00000001UL
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/** Port enabled */
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#define XHCI_PORTSC_PED 0x00000002UL
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#define XHCI_PORTSC_OCA (1 << 3)
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/** Port reset */
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#define XHCI_PORTSC_PR 0x00000010UL
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/** Port link state */
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#define XHCI_PORTSC_PLS(pls) ( (pls) << 5 )
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/** U0 state */
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#define XHCI_PORTSC_PLS_U0 XHCI_PORTSC_PLS ( 0 )
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/** Disabled port link state */
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#define XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 )
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/** RxDetect port link state */
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#define XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 )
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/** Polling state */
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#define XHCI_PORTSC_PLS_POLLING XHCI_PORTSC_PLS ( 7 )
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/** Port link state mask */
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#define XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf )
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/** Port power */
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#define XHCI_PORTSC_PP 0x00000200UL
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/** Time to delay after enabling power to a port */
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#define XHCI_PORT_POWER_DELAY_MS 20
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/** Port speed ID value */
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#define XHCI_PORTSC_PSIV(portsc) ( ( (portsc) >> 10 ) & 0xf )
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/** Port indicator control */
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#define XHCI_PORTSC_PIC(indicators) ( (indicators) << 14 )
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/** Port indicator control mask */
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#define XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 )
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/** Port link state write strobe */
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#define XHCI_PORTSC_LWS 0x00010000UL
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/** Time to delay after writing the port link state */
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#define XHCI_LINK_STATE_DELAY_MS 100
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/** Connect status change */
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#define XHCI_PORTSC_CSC (1 << 17)
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/** Port enabled/disabled change */
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#define XHCI_PORTSC_PEC (1 << 18)
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/** Warm port reset change */
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#define XHCI_PORTSC_WRC (1 << 19)
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/** Over-current change */
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#define XHCI_PORTSC_OCC (1 << 20)
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/** Port reset change */
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#define XHCI_PORTSC_PRC (1 << 21)
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/** Port link state change */
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#define XHCI_PORTSC_PLC (1 << 22)
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/** Port config error change */
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#define XHCI_PORTSC_CEC (1 << 23)
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/* Cold Attach Status 1: Far-end Receiver Terminations were detected */
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#define XHCI_PORTSC_CAS (1 << 24)
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/* Wake on Connect Enable 1: enable port to be sensitive to device connects */
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#define XHCI_PORTSC_WCE (1 << 25)
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/* Wake on Disconnect Enable 1: enable port to be sensitive to device disconnects */
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#define XHCI_PORTSC_WDE (1 << 26)
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/* Wake on Over-current Enable 1: enable port to be sensitive to over-current conditions */
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#define XHCI_PORTSC_WOE (1 << 27)
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/* Device Removable, 0: Device is removable. 1: Device is non-removable */
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#define XHCI_PORTSC_DR (1 << 30)
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/* Warm Port Reset 1: follow Warm Reset sequence */
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#define XHCI_PORTSC_WPR (1 << 31)
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/** Port status change mask */
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#define XHCI_PORTSC_CHANGE \
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( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \
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XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
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XHCI_PORTSC_CEC )
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#define XHCI_PORTSC_RW_MASK (XHCI_PORTSC_PR | XHCI_PORTSC_PLS_MASK | XHCI_PORTSC_PP \
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| XHCI_PORTSC_PIC_MASK | XHCI_PORTSC_LWS | XHCI_PORTSC_WCE \
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| XHCI_PORTSC_WDE | XHCI_PORTSC_WOE)
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/** Port status and control bits which should be preserved
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*
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* The port status and control register is a horrendous mix of
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* differing semantics. Some bits are written to only when a separate
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* write strobe bit is set. Some bits should be preserved when
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* modifying other bits. Some bits will be cleared if written back as
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* a one. Most excitingly, the "port enabled" bit has the semantics
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* that 1=enabled, 0=disabled, yet writing a 1 will disable the port.
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*/
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#define XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK )
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/** Port power management status and control register */
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#define XHCI_OP_PORTPMSC(port) ( 0x404 - 0x10 + ( (port) << 4 ) )
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/** Port link info register */
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#define XHCI_OP_PORTLI(port) ( 0x408 - 0x10 + ( (port) << 4 ) )
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/** Port hardware link power management control register */
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#define XHCI_OP_PORTHLPMC(port) ( 0x40c - 0x10 + ( (port) << 4 ) )
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/* Doorbell registers are 32 bits in length */
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#define XHCI_REG_DB_SIZE 4
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/** Interrupter Management Register */
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#define XHCI_RUN_IR_IMAN(intr) ( 0x20 + ( (intr) << 5 ) )
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/* Interrupt Pending, 1: an interrupt is pending for this Interrupter */
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#define XHCI_RUN_IR_IMAN_IP (1 << 0)
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/* Interrupt Enable, 1: capable of generating an interrupt. */
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#define XHCI_RUN_IR_IMAN_IE (1 << 1)
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/** Interrupter Moderation Register */
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#define XHCI_RUN_IR_IMOD(intr) ( 0x24 + ( (intr) << 5 ) )
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/** Event ring segment table size register */
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#define XHCI_RUN_ERSTSZ(intr) ( 0x28 + ( (intr) << 5 ) )
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/** Event ring segment table base address register */
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#define XHCI_RUN_ERSTBA(intr) ( 0x30 + ( (intr) << 5 ) )
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/** Event ring dequeue pointer register */
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#define XHCI_RUN_ERDP(intr) ( 0x38 + ( (intr) << 5 ) )
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/** Event Handler Busy */
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#define XHCI_RUN_ERDP_EHB (1 << 3)
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/** Minimum alignment required for data structures
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*
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* With the exception of the scratchpad buffer pages (which are
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* page-aligned), data structures used by xHCI generally require from
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* 16 to 64 byte alignment and must not cross an (xHCI) page boundary.
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* We simplify this requirement by aligning each structure on its own
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* size, with a minimum of a 64 byte alignment.
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*/
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#define XHCI_MIN_ALIGN 64
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/** Maximum transfer size */
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#define XHCI_MTU 65536
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/** Read/Write Data Barrier for ARM */
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#define BARRIER() __asm__ __volatile__("": : :"memory")
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#ifdef XHCI_AARCH64
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#define DSB() __asm__ __volatile__("dsb sy": : : "memory")
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#else
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#define DSB() __asm__ __volatile__("dsb": : : "memory")
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#endif
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/**
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* Read byte from memory-mapped device
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*
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* @v io_addr I/O address
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* @ret data Value read
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*/
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static inline uint8_t readb(void *io_addr ) {
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uint8_t val = *(volatile const uint8_t *)io_addr;
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BARRIER();
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return val;
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}
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/**
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* Read 16-bit word from memory-mapped device
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*
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* @v io_addr I/O address
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* @ret data Value read
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*/
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static inline uint16_t readw(void * io_addr ) {
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uint16_t val = *(volatile const uint16_t *)io_addr;
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BARRIER();
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return val;
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}
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/**
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* Read 32-bit dword from memory-mapped device
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*
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* @v io_addr I/O address
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* @ret data Value read
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*/
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static inline uint32_t readl(void * io_addr ) {
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uint32_t val = *(volatile const uint32_t *)io_addr;
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BARRIER();
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return val;
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}
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/**
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* Read 64-bit qword from memory-mapped device
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*
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* @v io_addr I/O address
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* @ret data Value read
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*/
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static inline uint64_t readq(void * io_addr ) {
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uint64_t val = *(volatile const uint64_t *)io_addr;
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BARRIER();
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return val;
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}
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/**
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* Write byte to memory-mapped device
|
||||
*
|
||||
* @v data Value to write
|
||||
* @v io_addr I/O address
|
||||
*/
|
||||
static inline void writeb(uint8_t data, void * io_addr ) {
|
||||
BARRIER();
|
||||
*(volatile uint8_t *)io_addr = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write 16-bit word to memory-mapped device
|
||||
*
|
||||
* @v data Value to write
|
||||
* @v io_addr I/O address
|
||||
*/
|
||||
static inline void writew(uint16_t data, void * io_addr ) {
|
||||
BARRIER();
|
||||
*(volatile uint16_t *)io_addr = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write 32-bit dword to memory-mapped device
|
||||
*
|
||||
* @v data Value to writed
|
||||
* @v io_addr I/O address
|
||||
*/
|
||||
static inline void writel(uint32_t data, void * io_addr ) {
|
||||
BARRIER();
|
||||
*(volatile uint32_t *)io_addr = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write 64-bit qword to memory-mapped device
|
||||
*
|
||||
* @v data Value to write
|
||||
* @v io_addr I/O address
|
||||
*/
|
||||
static inline void writeq(uint64_t data, void * io_addr ) {
|
||||
BARRIER();
|
||||
*(volatile uint64_t *)io_addr = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Byte-order converter for ARM-Little-End
|
||||
*/
|
||||
#define CPU_TO_LE64(x) ((uint64_t)(x))
|
||||
#define LE64_to_CPU(x) ((uint64_t)(x))
|
||||
#define CPU_TO_LE32(x) ((uint32_t)(x))
|
||||
#define LE32_TO_CPU(x) ((uint32_t)(x))
|
||||
#define CPU_TO_LE16(x) ((uint16_t)(x))
|
||||
#define LE16_TO_CPU(x) ((uint16_t)(x))
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue