ArmV8 support arch mmu intr clock
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@@ -57,20 +57,20 @@ Modification:
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.global _spinlock_lock
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.func _spinlock_lock
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_spinlock_lock:
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mov w2, #1
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sevl
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wfe
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// wait for an event signal
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ldaxrb w1, [x0] // check if the spinlock is currently unlocked
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cmp x1, #UNLOCKED
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wfe
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// wfe // wait for an event signal
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ldaxrb w1, [x0] // check if the spinlock is currently unlocked
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cmp w1, #UNLOCKED
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bne _spinlock_lock
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mrs x1, mpidr_el1 // get our CPU ID
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and x1, x1, #3
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stxrb w2, w1, [x0]
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cbnz x2, _spinlock_lock // check if the write was successful, if the write failed, start over
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cmp x2, #0
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bne _spinlock_lock // check if the write was successful, if the write failed, start over
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dmb ish // Ensure that accesses to shared resource have completed
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@@ -88,21 +88,21 @@ _spinlock_unlock:
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mrs x1, mpidr_el1 // get our CPU ID
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and x1, x1, #3
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ldr x2, [x0]
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cmp x1, x2
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ldr w2, [x0]
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cmp w1, w2
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bne 1f //doesn't match,jump to 1
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dmb ish
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mov x1, #UNLOCKED
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str x1, [x0]
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mov w1, #UNLOCKED
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str w1, [x0]
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dsb ish //Ensure that no instructions following the barrier execute until
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// all memory accesses prior to the barrier have completed.
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sev // send event to wake up other cores waiting on spinlock
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sevl // send event to wake up other cores waiting on spinlock
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mov x0, #0 // return success
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ret
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@@ -73,7 +73,7 @@ void syscall_arch_handler(struct trapframe* tf)
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xizi_enter_kernel();
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assert(cur_cpu()->task == NULL);
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sys_exit(cur_cpu()->task);
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context_switch(&cur_cpu()->task->main_thread.context, cur_cpu()->scheduler);
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context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler);
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panic("dabort end should never be reashed.\n");
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}
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}
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