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Support armv8 clock.

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TXuian
2024-05-29 15:10:52 +08:00
parent 5a2c07e1a9
commit 6d4cef4358
6 changed files with 12 additions and 10 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c
+1 -2
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@@ -192,8 +192,7 @@ gic_set_prio0(uint32_t intid)
gicd_write(D_IPRIORITYR(intid / 4), p);
}
static void
gic_set_target(uint32_t intid, uint32_t cpuid)
static void gic_set_target(uint32_t intid, uint32_t cpuid)
{
uint32_t itargetsr = gicd_read(D_ITARGETSR(intid / 4));
itargetsr &= ~((uint32_t)0xff << (intid % 4 * 8));
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_common_opa.h
+1
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@@ -83,6 +83,7 @@ void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt);
void gic_set_irq_priority(uint32_t irq_id, uint32_t priority);
void gic_setup_spi(uint32_t cpuid, uint32_t intid);
void gic_setup_ppi(uint32_t cpuid, uint32_t intid);
void gicv3inithart(uint32_t cpu_id);
//! @brief Send a software generated interrupt to a specific CPU.
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
+1 -1
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@@ -70,7 +70,7 @@ static void _cpu_irq_disable(void)
static void _single_irq_enable(int irq, int cpu, int prio)
{
gic_setup_spi((uint32_t)cpu, (uint32_t)irq);
gic_setup_ppi((uint32_t)cpu, (uint32_t)irq);
}
static void _single_irq_disable(int irq, int cpu)
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S
-3
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@@ -197,7 +197,6 @@ el1irq:
bl intr_irq_dispatch
urestorereg
msr daifclr, #0xf
eret
@@ -209,7 +208,6 @@ el0sync:
bl syscall_arch_handler
urestorereg
msr daifclr, #0xf
eret
@@ -223,6 +221,5 @@ el0irq:
.global trap_return
trap_return:
urestorereg
msr daifclr, #0xf
eret