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TODO: Port ok1028a-c.

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This commit is contained in:
liuqh
2024-05-08 15:35:21 +08:00
parent f5ad8437b5
commit 6b91caac18
43 changed files with 2862 additions and 2 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile
+1 -1
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@@ -1,4 +1,4 @@
SRC_DIR := arm/armv7-a/cortex-a9
SRC_DIR := arm
SRC_FILES := spinlock.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile
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@@ -0,0 +1,9 @@
ifneq ($(findstring $(BOARD), ok1028a-c), )
SRC_DIR := armv8-a
endif
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := armv7-a
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/Makefile
+6
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@@ -0,0 +1,6 @@
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := cortex-a9
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile
+3
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@@ -0,0 +1,3 @@
SRC_DIR := cortex-a72
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c
+121
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@@ -0,0 +1,121 @@
/* Copyright (c) 2006-2018 Frans Kaashoek, Robert Morris, Russ Cox,
* Massachusetts Institute of Technology
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* @file error_debug.c
* @brief handle program abort
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.4.25
*/
/*************************************************
File name: error_debug.c
Description: handle program abort
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. Take only armv8 abort reason part(_abort_reason).
2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler())
*************************************************/
#include "log.h"
#include "multicores.h"
#include "spinlock.h"
#include "syscall.h"
__attribute__((always_inline)) static inline void _abort_reason(uint32_t fault_status)
{
if ((fault_status & 0x3f) == 0x21) // Alignment failure
KPrintf("reason: alignment\n");
else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0
KPrintf("reason: sect. translation level 0\n");
else if ((fault_status & 0x3f) == 0x5) // Translation fault, level 1
KPrintf("reason: sect. translation level 1\n");
else if ((fault_status & 0x3f) == 0x6) // Translation fault, level 2
KPrintf("reason: sect. translation level 2\n");
else if ((fault_status & 0x3f) == 0x7) // Translation fault, level 3
KPrintf("reason: sect. translation level 3\n");
else if ((fault_status & 0x3f) == 0x3d) //Section Domain fault
KPrintf("reason: sect. domain\n");
else if ((fault_status & 0x3f) == 0x13) // Permission level 1
KPrintf("reason: sect. permission level 1\n");
else if ((fault_status & 0x3f) == 0x14) // Permission level 2
KPrintf("reason: sect. permission level 2\n");
else if ((fault_status & 0x3f) == 0x15) // Permission level 3
KPrintf("reason: sect. permission level 3\n");
else if ((fault_status & 0x3f) == 0x8) // External abort
KPrintf("reason: ext. abort\n");
else if ((fault_status & 0x3f) == 0x9) // Access flag fault, level 1
KPrintf("reason: sect. Access flag fault level 1\n");
else if ((fault_status & 0x3f) == 0xa) // Access flag fault, level 2
KPrintf("reason: sect. Access flag fault level 2\n");
else if ((fault_status & 0x3f) == 0xb) // Access flag fault, level 3
KPrintf("reason: sect. Access flag fault level 3\n");
else
KPrintf("reason: unknown???\n");
}
void dump_tf(struct trapframe* tf)
{
KPrintf(" elr_el1: 0x%x\n", tf->elr_el1);
KPrintf(" spsr_el1: 0x%x\n", tf->spsr_el1);
KPrintf(" x0: 0x%x\n", tf->x0);
KPrintf(" x1: 0x%x\n", tf->x1);
KPrintf(" x2: 0x%x\n", tf->x2);
KPrintf(" x3: 0x%x\n", tf->x3);
KPrintf(" x4: 0x%x\n", tf->x4);
KPrintf(" x5: 0x%x\n", tf->x5);
KPrintf(" x6: 0x%x\n", tf->x6);
KPrintf(" x7: 0x%x\n", tf->x7);
KPrintf(" x8: 0x%x\n", tf->x8);
KPrintf(" x9: 0x%x\n", tf->x9);
KPrintf(" x10: 0x%x\n", tf->x10);
KPrintf(" x11: 0x%x\n", tf->x11);
KPrintf(" x12: 0x%x\n", tf->x12);
KPrintf(" x13: 0x%x\n", tf->x13);
KPrintf(" x14: 0x%x\n", tf->x14);
KPrintf(" x15: 0x%x\n", tf->x15);
KPrintf(" x16: 0x%x\n", tf->x16);
KPrintf(" x17: 0x%x\n", tf->x17);
KPrintf(" x18: 0x%x\n", tf->x18);
KPrintf(" x19: 0x%x\n", tf->x19);
KPrintf(" x20: 0x%x\n", tf->x20);
KPrintf(" x21: 0x%x\n", tf->x21);
KPrintf(" x22: 0x%x\n", tf->x22);
KPrintf(" x23: 0x%x\n", tf->x23);
KPrintf(" x24: 0x%x\n", tf->x24);
KPrintf(" x25: 0x%x\n", tf->x25);
KPrintf(" x26: 0x%x\n", tf->x26);
KPrintf(" x27: 0x%x\n", tf->x27);
KPrintf(" x28: 0x%x\n", tf->x28);
KPrintf(" x29: 0x%x\n", tf->x29);
KPrintf(" pc: 0x%x\n", tf->pc);
}
void handle_undefined_instruction(struct trapframe* tf)
{
// unimplemented trap handler
KPrintf("undefined instruction at %x\n", tf->pc);
panic("");
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/arch_gicv3.h
+27
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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file arch_gicv3.h
* @brief gicv3 operation
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.05.07
*/
/*************************************************
File name: arch_gicv3.h
Description: gicv3 operation
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. Rename file
*************************************************/
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c
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Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.h
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Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/sysreg.h
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Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S
+109
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@@ -0,0 +1,109 @@
/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Portions Copyright (c) 2011-2012 ARM Ltd. All rights reserved.
*/
/**
* @file hard_spinlock.S
* @brief spinlock implementation
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.11
*/
/*************************************************
File name: hard_spinlock.S
Description: spinlock implementation
Others:
History:
Author: AIIT XUOS Lab
Modification:
*************************************************/
.code 64
.section ".text","ax"
.global cpu_get_current
#define UNLOCKED 0xFF
// int spinlock_lock(spinlock_t * lock, uint64_t timeout)
.global _spinlock_lock
.func _spinlock_lock
_spinlock_lock:
ldxr x1, [x0] // check if the spinlock is currently unlocked
cmp x1, #UNLOCKED
wfene // wait for an event signal
bne _spinlock_lock
mrs x1, mpidr_el1 // get our CPU ID
and x1, x1, #3
stxr x2, x1, [x0]
cbnz x2, _spinlock_lock // check if the write was successful, if the write failed, start over
dmb // Ensure that accesses to shared resource have completed
mov x0, #0
ret
.endfunc
// void spinlock_unlock(spinlock_t * lock)
.global _spinlock_unlock
.func _spinlock_unlock
_spinlock_unlock:
mrs x1, mpidr_el1 // get our CPU ID
and x1, x1, #3
ldr x2, [x0]
cmp x1, x2
bne 1f //doesn't match,jump to 1
dmb
mov x1, #UNLOCKED
str x1, [x0]
dsb //Ensure that no instructions following the barrier execute until
// all memory accesses prior to the barrier have completed.
sev // send event to wake up other cores waiting on spinlock
mov x0, #0 // return success
ret
1:
mov x0, #1 //doesn't match, so exit with failure
ret
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h
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/**
* @file irq_numbers.c
* @brief irq numbers
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.08.25
*/
/*************************************************
File name: irq_numbers.c
Description: irq numbers
Others:
History:
1. Date: 2023-08-28
Author: AIIT XUOS Lab
Modification:
1. Add HW_NR_IRQS
*************************************************/
#if !defined(__IRQ_NUMBERS_H__)
#define __IRQ_NUMBERS_H__
#define HW_NR_IRQS NR_OK1028_INTRS
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief i.MX6 interrupt numbers.
//!
//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
//! Use these numbers when specifying an interrupt to the GIC.
//!
//! The first 16 interrupts are special in that they are reserved for software interrupts generated
//! by the SWI instruction.
enum _ls_interrupts {
SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
RSVD_INTERRUPT_16 = 16, //!< Reserved.
RSVD_INTERRUPT_17 = 17, //!< Reserved.
RSVD_INTERRUPT_18 = 18, //!< Reserved.
RSVD_INTERRUPT_19 = 19, //!< Reserved.
RSVD_INTERRUPT_20 = 20, //!< Reserved.
RSVD_INTERRUPT_21 = 21, //!< Reserved.
LS_INT_DEBUG_CC = 22, //!<(cluster-internal) COMMIRQ - Debug communications channel
LS_INT_PMU = 23, //!<(cluster-internal) PMUIRQ - Perfmon*
LS_INT_CTI = 24, //!<(cluster-internal) CTIIRQ - Cross-trigger interface*
LS_INT_VMI = 25, //!<(cluster-internal) VCPUMNTIRQ -Virtual maintenance interface*
LS_INT_WDOG = 28, //!< Watchdog timer
LS_INT_SEC_PHY_TIMER = 29, //!<(cluster-internal) CNTPSIRQ - EL1 Secure physical timer event*
LS_INT_NON_SEC_PHY_TIMER = 30, //!<(cluster-internal) CNTPNSIRQ - EL1 Non-secure physical timer event*
RSVD_INTERRUPT_31 = 31, //!< Reserved.
RSVD_INTERRUPT_32 = 32, //!< Reserved.
RSVD_INTERRUPT_33 = 33, //!< Reserved.
RSVD_INTERRUPT_34 = 34, //!< Reserved.
RSVD_INTERRUPT_35 = 35, //!< Reserved.
RSVD_INTERRUPT_36 = 36, //!< Reserved.
RSVD_INTERRUPT_37 = 37, //!< Reserved.
RSVD_INTERRUPT_38 = 38, //!< Reserved.
RSVD_INTERRUPT_39 = 39, //!< Reserved.
RSVD_INTERRUPT_40 = 40, //!< Reserved.
RSVD_INTERRUPT_41 = 41, //!< Reserved.
RSVD_INTERRUPT_42 = 42, //!< Reserved.
LS_INT_DUART1 = 64, // Logical OR of DUART1 interrupt requests.
LS_INT_I2C1_2 = 66, //!< I2C1 and I2C2 ORed
LS_INT_I2C3_4 = 67, //!< I2C3 and I2C4 ORed
LS_INT_GPIO1_2 = 68, //!< GPIO1 and GPIO2 ORed
LS_INT_GPIO3 = 69, //!< GPIO3
LS_INT_FLETIMER1 = 76, //!< ORed all Flextimer 1 interrupt signals
LS_INT_FLETIMER1 = 77, //!< ORed all Flextimer 2 interrupt signals
LS_INT_FLETIMER1 = 78, //!< ORed all Flextimer 3 interrupt signals
LS_INT_FLETIMER1 = 79, //!< ORed all Flextimer 4 interrupt signals
LS_INT_I2C5_6 = 106, //!< I2C5 and I2C6 ORed
LS_INT_I2C7_8 = 107, //!< I2C7 and I2C8 ORed
LS_INT_USB3_1 = 112, //!< USB1 ORed INT
LS_INT_USB3_2 = 113, //!< USB2 ORed INT
LS_INT_LPUART1 = 264, //!< LPUART1 interrupt request.
LS_INT_LPUART2 = 265, //!< LPUART1 interrupt request.
LS_INT_LPUART3 = 266, //!< LPUART1 interrupt request.
LS_INT_LPUART4 = 267, //!< LPUART1 interrupt request.
LS_INT_LPUART5 = 268, //!< LPUART1 interrupt request.
LS_INT_LPUART6 = 269, //!< LPUART1 interrupt request.
NR_OK1028_INTRS,
};
#endif //__IRQ_NUMBERS_H__
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file trap_common.c
* @brief trap interface of hardkernel
* @version 1.0
* @author AIIT XUOS Lab
* @date 2023.05.06
*/
/*************************************************
File name: trap_common.c
Description: trap interface of hardkernel
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <string.h>
#include "core.h"
#include "gicv2_common_opa.h"
#include "trap_common.h"
#include "log.h"
#include "multicores.h"
extern void init_stack(uint64_t, uint64_t);
extern void user_trap_swi_enter(void);
extern void trap_iabort(void);
extern void trap_dabort(void);
extern void trap_irq_enter(void);
extern void trap_undefined_instruction(void);
static struct XiziTrapDriver xizi_trap_driver;
void panic(char* s)
{
xizi_trap_driver.cpu_irq_disable();
spinlock_unlock(&whole_kernel_lock);
KPrintf("panic: %s\n", s);
for (;;)
;
}
/* stack for different mode*/
static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE];
extern uint64_t _vector_jumper;
extern uint64_t _vector_start;
extern uint64_t _vector_end;
void init_cpu_mode_stacks(int cpu_id)
{
uint32_t modes[] = { ARM_MODE_EL0_t, ARM_MODE_EL1_t, ARM_MODE_EL2_t, ARM_MODE_EL3_t };
// initialize the stacks for different mode
for (int i = 0; i < sizeof(modes) / sizeof(uint64_t); i++) {
memset(mode_stack_pages[cpu_id][i], 0, MODE_STACK_SIZE);
init_stack(modes[i], (uint64_t)mode_stack_pages[cpu_id][i]);
}
}
void handle_reserved(void)
{
// unimplemented trap handler
LOG("Unimplemented Reserved\n");
panic("");
}
void handle_fiq(void)
{
LOG("Unimplemented FIQ\n");
panic("");
}
static void _sys_irq_init(int cpu_id)
{
/* load exception vectors */
init_cpu_mode_stacks(cpu_id);
if (cpu_id == 0) {
volatile uint64_t* vector_base = &_vector_start;
// Set Interrupt handler start address
vector_base[1] = (uint64_t)trap_undefined_instruction; // Undefined Instruction
vector_base[2] = (uint64_t)user_trap_swi_enter; // Software Interrupt
vector_base[3] = (uint64_t)trap_iabort; // Prefetch Abort
vector_base[4] = (uint64_t)trap_dabort; // Data Abort
vector_base[5] = (uint64_t)handle_reserved; // Reserved
vector_base[6] = (uint64_t)trap_irq_enter; // IRQ
vector_base[7] = (uint64_t)handle_fiq; // FIQ
}
/* active hardware irq responser */
gic_init();
xizi_trap_driver.switch_hw_irqtbl((uint64_t*)&_vector_jumper);
}
static void _cpu_irq_enable(void)
{
arm_set_interrupt_state(true);
}
static void _cpu_irq_disable(void)
{
arm_set_interrupt_state(false);
}
static void _single_irq_enable(int irq, int cpu, int prio)
{
gic_set_irq_priority(irq, prio);
gic_set_irq_security(irq, false); // set IRQ as non-secure
gic_set_cpu_target(irq, cpu, true);
gic_enable_irq(irq, true);
}
static void _single_irq_disable(int irq, int cpu)
{
gic_enable_irq(irq, false);
gic_set_cpu_target(irq, cpu, false);
}
#define VBAR
static inline uint64_t _switch_hw_irqtbl(uint64_t* new_tbl_base)
{
uint64_t old_tbl_base = 0;
//get old irq table base addr
asm volatile("mrs %0, vbar_el1" : "=r" (old_tbl_base));
// set new irq table base addr
asm volatile("msr vbar_el1, %0" : : "r" (new_tbl_base));
return old_tbl_base;
}
static void _bind_irq_handler(int irq, irq_handler_t handler)
{
xizi_trap_driver.sw_irqtbl[irq].handler = handler;
}
static bool _send_sgi(uint32_t irq, uint32_t bitmask, enum SgiFilterType type)
{
if (bitmask > (1 << NR_CPU) - 1) {
return false;
}
enum _gicd_sgi_filter sgi_filter;
switch (type) {
case SgiFilter_TargetList:
sgi_filter = kGicSgiFilter_UseTargetList;
break;
case SgiFilter_AllOtherCPUs:
sgi_filter = kGicSgiFilter_AllOtherCPUs;
break;
default:
sgi_filter = kGicSgiFilter_OnlyThisCPU;
break;
}
gic_send_sgi(irq, bitmask, sgi_filter);
return true;
}
static uint32_t _hw_before_irq()
{
uint32_t vectNum = gic_read_irq_ack();
if (vectNum & 0x200) {
gic_write_end_of_irq(vectNum);
return 0;
}
return vectNum;
}
static uint32_t _hw_cur_int_num(uint32_t int_info)
{
return int_info & 0x1FF;
}
static uint32_t _hw_cur_int_cpu(uint32_t int_info)
{
return (int_info >> 10) & 0x7;
}
static void _hw_after_irq(uint32_t int_info)
{
gic_write_end_of_irq(int_info);
}
static int _is_interruptable(void)
{
uint32_t val;
asm volatile("mrs %0, spsr_el1" : "=r"(val));
return !(val & DIS_INT);
}
int _cur_cpu_id()
{
return cpu_get_current();
}
static struct XiziTrapDriver xizi_trap_driver = {
.sys_irq_init = _sys_irq_init,
.cur_cpu_id = _cur_cpu_id,
.cpu_irq_enable = _cpu_irq_enable,
.cpu_irq_disable = _cpu_irq_disable,
.single_irq_enable = _single_irq_enable,
.single_irq_disable = _single_irq_disable,
.switch_hw_irqtbl = _switch_hw_irqtbl,
.bind_irq_handler = _bind_irq_handler,
.send_sgi = _send_sgi,
.is_interruptable = _is_interruptable,
.hw_before_irq = _hw_before_irq,
.hw_cur_int_num = _hw_cur_int_num,
.hw_cur_int_cpu = _hw_cur_int_cpu,
.hw_after_irq = _hw_after_irq,
};
struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
{
xizi_trap_driver.sys_irq_init(0);
xizi_trap_driver.cpu_irq_disable();
return &xizi_trap_driver;
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file trampoline.S
* @brief trap in and out code
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-04-22
*/
/*************************************************
File name: trampoline.S
Description: trap in and out code
Others:
History:
1. Date: 2024-04-22
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include "memlayout.h"
#include "core.h"
.global trap_irq_enter
.global trap_return
.global usertrapret
trap_return:
/* Restore registers. */
ldp x1, x2, [sp], #16
ldp x3, x0, [sp], #16
msr sp_el0, x1
msr spsr_el1, x2
msr elr_el1, x3
ldp x1, x2, [sp], #16
ldp x3, x4, [sp], #16
ldp x5, x6, [sp], #16
ldp x7, x8, [sp], #16
ldp x9, x10, [sp], #16
ldp x11, x12, [sp], #16
ldp x13, x14, [sp], #16
ldp x15, x16, [sp], #16
ldp x17, x18, [sp], #16
ldp x19, x20, [sp], #16
ldp x21, x22, [sp], #16
ldp x23, x24, [sp], #16
ldp x25, x26, [sp], #16
ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
eret
user_trap_swi_enter:
// Save trapframe to swi stack
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x9, x10, [sp, #-16]!
stp x7, x8, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
mrs x2, spsr_el1
str x2, [sp, #-8]
str x30, [sp, #-8]
stp sp, elr_el1, [sp, #-16]!
str sp, [sp, #-8]
// Call syscall handler
mov x0, sp
bl software_irq_dispatch
b trap_return
trap_irq_enter:
/* Build trapframe. */
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x9, x10, [sp, #-16]!
stp x7, x8, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
mrs x3, elr_el1
mrs x2, spsr_el1
mrs x1, sp_el0
stp x3, x0, [sp, #-16]!
stp x1, x2, [sp, #-16]!
/* Call trap(struct trapframe*). */
mov x0, sp
bl intr_irq_dispatch
b trap_return
/* Help forkret to call trap_return in an expected way. */
usertrapret:
/* Overlay stack pointer in trap_return. */
mov sp, x0
b trap_return
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/vector.S
+67
View File
@@ -0,0 +1,67 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file vector.S
* @brief define vector table function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.4.22
*/
/*************************************************
File name: vector.S
Description: cortex-a9 vector table
Others:
History:
1. Date: 2024.4.22
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include "memlayout.h"
#define ventry .align 7; b trap_irq_enter
#define verror(type) .align 7; mov x0, #(type); b irq_error
.globl vectors
.align 11
vectors:
el1_sp0:
verror(0)
verror(1)
verror(2)
verror(3)
el1_spx:
/* Current EL with SPx */
verror(4)
verror(5)
verror(6)
verror(7)
el0_aarch64:
/* Lower EL using AArch64 */
ventry
ventry
verror(10)
verror(11)
el0_aarch32:
/* Lower EL using AArch32 */
verror(12)
verror(13)
verror(14)
verror(15)