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add hal ethernet driver

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This commit is contained in:
lr
2024-06-03 16:45:09 +08:00
parent 5d6cd493bf
commit 4f182f90c9
29 changed files with 28189 additions and 2 deletions
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Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/Makefile
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ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
endif
ifeq ($(BOARD), zynq7000-zc702)
toolchain ?= arm-xilinx-eabi-
endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
cflags = -std=c11 -g \
-Wno-unused -Wno-format -fno-common -ffreestanding -fno-builtin -static \
-Wno-unaligned-access -fdce -Wall -Werror -Wno-uninitialized -Wno-strict-aliasing -fdiagnostics-show-option \
-mapcs -marm -mfpu=neon -ftree-vectorize -fno-math-errno -funsafe-math-optimizations -fno-signed-zeros -mfloat-abi=softfp \
-fno-omit-frame-pointer -fno-stack-protector -fno-pie
# cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic \
# -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
INC_DIR = -I$(KERNEL_ROOT)/services/app \
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
-I$(KERNEL_ROOT)/services/lib/serial \
-I$(KERNEL_ROOT)/services/drivers/rk-3568/include \
-I$(KERNEL_ROOT)/services/lib/usyscall \
-I$(KERNEL_ROOT)/services/lib/ipc \
-I$(KERNEL_ROOT)/services/lib/memory
all: gmac.o gmac_3568.o test_gmac.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o
@mv $^ $(KERNEL_ROOT)/services/app
%.o: %.c
@echo "cc $^"
@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/gmac.c
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Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/gmac_3568.c
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_base.h"
#include "hal_gmac.h"
#include "hal_debug.h"
#include "hal_cru.h"
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup GMAC
* @{
*/
/** @defgroup GMAC_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
#define GRF_BIT(nr) (1 << (nr) | 1 << (nr+16))
#define GRF_CLR_BIT(nr) (1 << (nr+16))
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
#define RK3568_GRF_GMAC0_CON0 0X0380
#define RK3568_GRF_GMAC0_CON1 0X0384
#define RK3568_GRF_GMAC1_CON0 0X0388
#define RK3568_GRF_GMAC1_CON1 0X038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
#define RK3568_GMAC_PHY_INTF_SEL_RMII \
(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
/********************* Private Structure Definition **************************/
/********************* Private Variable Definition ***************************/
/********************* Private Function Definition ***************************/
/** @} */
/********************* Public Function Definition ****************************/
/** @defgroup GMAC_Exported_Functions_Group5 Other Functions
* @{
*/
/**
* @brief Set RGMII Mode.
* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
* the information for GMAC module.
* @param txDelay: RGMII tx delayline
* @param rxDelay: RGMII rx delayline
*/
void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
int32_t txDelay, int32_t rxDelay)
{
uint32_t *con0, *con1;
con0 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON0) :
&(GRF->MAC0_CON0));
con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
&(GRF->MAC0_CON1));
WRITE_REG(*con1,
RK3568_GMAC_PHY_INTF_SEL_RGMII |
RK3568_GMAC_RXCLK_DLY_ENABLE |
RK3568_GMAC_TXCLK_DLY_ENABLE);
WRITE_REG(*con0,
RK3568_GMAC_CLK_RX_DL_CFG(rxDelay) |
RK3568_GMAC_CLK_TX_DL_CFG(txDelay));
}
/**
* @brief Set RMII Mode.
* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
* the information for GMAC module.
*/
void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC)
{
uint32_t *con1, *cruCon, val;
con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
&(GRF->MAC0_CON1));
WRITE_REG(*con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
&(CRU->CRU_CLKSEL_CON[31]));
/* RMII mode */
val = HIWORD_UPDATE(0x1, 0x3, 0);
/* clock from io if it was */
/* val |= HIWORD_UPDATE(0x1, 0x1, 2); */
/* ref clock sel 50M */
val |= HIWORD_UPDATE(0x1, 0x3, 8);
/* clock speed 25M */
val |= HIWORD_UPDATE(0x1, 0x1, 3);
WRITE_REG(*cruCon, val);
}
/**
* @brief Set external clock source select.
* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
* the information for GMAC module.
* @param extClk: 0: select clk_mac as the clock of mac
* 1: select external phy clock as the clock of mac
*/
void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk)
{
uint32_t *cruCon, val;
uint32_t clksel = 0;
cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
&(CRU->CRU_CLKSEL_CON[31]));
if (extClk) {
clksel = 1;
}
val = HIWORD_UPDATE(clksel, 0x1, 2);
WRITE_REG(*cruCon, val);
}
/**
* @brief Set RGMII speed.
* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
* the information for GMAC module.
* @param speed: RGMII speed 10/100/1000
*/
void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
{
eCLOCK_Name clkID;
uint32_t rate;
int32_t ret;
switch (speed) {
case 10:
rate = 2500000;
break;
case 100:
rate = 25000000;
break;
case 1000:
rate = 125000000;
break;
default:
HAL_DBG_ERR("unknown speed value for GMAC speed=%ld", speed);
return;
}
if (pGMAC->phyStatus.interface == PHY_INTERFACE_MODE_RMII) {
clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RMII_SPEED :
SCLK_GMAC0_RMII_SPEED;
} else {
clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RGMII_SPEED :
SCLK_GMAC0_RGMII_SPEED;
}
ret = HAL_CRU_ClkSetFreq(clkID, rate);
if (ret) {
HAL_DBG_ERR("%s: set clk_mac_speed rate %ld failed %ld\n",
__func__, rate, ret);
}
}
/**
* @brief Set RGMII speed.
* @param pGMAC: pointer to a GMAC_HANDLE structure that contains
* the information for GMAC module.
* @param speed: RGMII speed 10/100
*/
void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
{
HAL_GMAC_SetRGMIISpeed(pGMAC, speed);
}
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_base.c
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_base.h"
#include "hal_def.h"
#include "hal_bsp.h"
#include "hal_timer.h"
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup HAL_BASE
* @{
*/
/** @defgroup HAL_BASE_How_To_Use How To Use
* @{
HAL system support is including delay system, HAL tick system and global system clock,
HAL system tick setting:
- Attach HAL_IncTick() to system tick interrupt handler;
- Notify the HAL system the system's tick frequency by calling HAL_SetTickFreq() unless
it is the same as default value HAL_TICK_FREQ_1KHZ;
- If you need a more accurate delay system, specify SYS_TIMER in hal_conf.h.
Init HAL system:
- Initialize the HAL system by calling HAL_Init():
Reset when SOC system is changed:
- Update system with new core clock and new SysTick clock source by calling HAL_SystemCoreClockUpdate();
APIs:
- Get system time by calling HAL_GetTick().
- Delay for a certain length of time, HAL_DelayMs(), HAL_DelayUs(), and HAL_CPUDelayUs().
- Blocking for a certain period of time to continuously query HW status, use HAL_GetTick()
to do timeout, this will be more accurate.
- Get current cpu usage by calling HAL_GetCPUUsage().
@} */
/** @defgroup HAL_BASE_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
#define SYSTEM_CLOCK 816000000U
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/********************* Private Structure Definition **************************/
/********************* Private Variable Definition ***************************/
static __IO uint32_t uwTick;
static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT;
/********************* Private Function Definition ***************************/
static void CPUCycleLoop(uint32_t cycles)
{
__asm volatile (
"mov r0, %0\n\t"
"adds r0, r0, #2\n\t" // 1 2 Round to the nearest multiple of 4.
"lsrs r0, r0, #2\n\t" // 1 2 Divide by 4 and set flags.
"beq 2f\n\t" // 2 2 Skip if 0.
".align 4\n\t"
"1:\n\t"
"adds r0, r0, #1\n\t" // 1 2 Increment the counter.
"subs r0, r0, #2\n\t" // 1 2 Decrement the counter by 2.
"bne 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken).
"nop\n\t" // 1 2 Loop alignment padding.
"2:"
: : "r" (cycles)
);
}
static inline HAL_Status TimerDelayUs(uint32_t us)
{
uint64_t count, from, now, pass;
from = HAL_TIMER_GetCount(SYS_TIMER);
count = PLL_INPUT_OSC_RATE / 1000000 * us;
do {
now = HAL_TIMER_GetCount(SYS_TIMER);
pass = now > from ? now - from : from - now;
} while (pass < count);
return HAL_OK;
}
/** @} */
/********************* Public Function Definition ***************************/
/** @defgroup HAL_BASE_Exported_Functions_Group4 Init and DeInit Functions
This section provides functions allowing to init and deinit the module:
* @{
*/
/**
* @brief Init HAL driver basic code.
* @return HAL_OK.
*/
/**
* @brief HAL system update with new core clock and systick clock source.
* @param hz: new core clock.
* @param clkSource: new systick clock source.
* @return HAL_OK.
*/
HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource)
{
uint32_t rate = hz;
HAL_Status ret = HAL_OK;
#if defined(__CORTEX_M) && defined(HAL_SYSTICK_MODULE_ENABLED)
ret = HAL_SYSTICK_CLKSourceConfig(clkSource);
if (ret == HAL_OK && clkSource == HAL_SYSTICK_CLKSRC_EXT) {
rate = PLL_INPUT_OSC_RATE;
}
HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq()));
ret = HAL_OK;
#endif
if (ret == HAL_OK) {
SystemCoreClock = rate; /* Update global SystemCoreClock */
}
return ret;
}
/** @} */
/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
* @{
*/
/**
* @brief Count plus tickFreq when interrupt occurs.
* @return HAL_Status: HAL_OK.
*/
HAL_Status HAL_IncTick(void)
{
uwTick += uwTickFreq;
return HAL_OK;
}
/**
* @brief Provides tick value in millisecond.
* @return uint32_t: tick value in millisecond.
* @attention this API allow direct use in the HAL layer.
*/
uint32_t HAL_GetTick(void)
{
uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER);
uint32_t base = PLL_INPUT_OSC_RATE / 1000;
if (tick >> 62) {
tick = ~tick;
}
return (uint32_t)HAL_DivU64(tick, base);
}
/**
* @brief Provides system timer count.
* @return uint64_t: timer count.
* @attention this API allow direct use in the HAL layer.
*/
uint64_t HAL_GetSysTimerCount(void)
{
uint64_t count = HAL_TIMER_GetCount(SYS_TIMER);
if (count >> 62) {
count = ~count;
}
return count;
}
/**
* @brief Set new tick frequency.
* @return HAL_Status.
*/
HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq)
{
// HAL_ASSERT(IS_TICKFREQ(freq));
uwTickFreq = freq;
return HAL_OK;
}
/**
* @brief Return tick frequency.
* @return uint32_t: tick period in Hz.
* @attention this API allow direct use in the HAL layer.
*/
eHAL_tickFreq HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief SysTick mdelay.
* @param ms: mdelay count.
* @return HAL_Status: HAL_OK.
* @attention this API allow direct use in the HAL layer. Blocking for a
* certain period of time to continuously query HW status, use HAL_GetTick
* to do timeout, that will be more accurate.
*/
__attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms)
{
for (uint32_t i = 0; i < ms; i++) {
HAL_DelayUs(1000);
}
return HAL_OK;
}
/**
* @brief SysTick udelay.
* @param us: udelay count.
* @return HAL_Status: HAL_OK.
* @attention this API allow direct use in the HAL layer. The longer the delay,
* the more accurate. Actual delay is greater than the parameter.
*/
HAL_Status HAL_DelayUs(uint32_t us)
{
#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
return TimerDelayUs(us);
#else
return HAL_CPUDelayUs(us);
#endif
}
/**
* @brief CPU loop udelay.
* @param us: udelay count.
* @return HAL_Status: HAL_OK.
* @attention this API allow direct use in the HAL layer. The longer the delay,
* the more accurate. Actual delay is greater than the parameter.
* During delay, CPU rate change result in delay imprecise, so call it in
* following case:
* 1.IRQ disable
* 2.CRU code
*/
HAL_Status HAL_CPUDelayUs(uint32_t us)
{
volatile uint32_t cycles;
#if (__CORTEX_M == 0)
cycles = (uint32_t)HAL_DivU64((uint64_t)SystemCoreClock, 1000000) * us; /* Add few cycles penalty */
#else
cycles = SystemCoreClock / 1000000 * us; /* Add few cycles penalty */
#endif
CPUCycleLoop(cycles);
return HAL_OK;
}
uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder)
{
uint64_t remainder = numerator;
uint64_t b = denominator;
uint64_t result;
uint64_t d = 1;
uint32_t high = numerator >> 32;
result = 0;
if (high >= denominator) {
high /= denominator;
result = (uint64_t)high << 32;
remainder -= (uint64_t)(high * denominator) << 32;
}
while ((int64_t)b > 0 && b < remainder) {
b = b + b;
d = d + d;
}
do {
if (remainder >= b) {
remainder -= b;
result += d;
}
b >>= 1;
d >>= 1;
} while (d);
if (pRemainder) {
*pRemainder = remainder;
}
return result;
}
/** @} */
/** @} */
/** @} */
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_bsp.c
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_bsp.h"
#include "rk3568.h"
#include "soc.h"
#include "hal_gmac.h"
const struct HAL_GMAC_DEV g_gmac0Dev =
{
.pReg = GMAC0,
.clkID = CLK_MAC0_2TOP,
.clkGateID = CLK_MAC0_2TOP_GATE,
.pclkID = PCLK_PHP,
.pclkGateID = PCLK_GMAC0_GATE,
.irqNum = GMAC0_IRQn,
};
const struct HAL_GMAC_DEV g_gmac1Dev =
{
.pReg = GMAC1,
.clkID = CLK_MAC1_2TOP,
.clkGateID = CLK_MAC1_2TOP_GATE,
.pclkID = PCLK_USB,
.pclkGateID = PCLK_GMAC1_GATE,
.irqNum = GMAC1_IRQn,
};
void BSP_Init(void)
{
}
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cache.c
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Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru.c
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Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru_rk3568.c
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Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_debug.c
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*/
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup DEBUG
* @{
*/
/** @defgroup DEBUG_How_To_Use How To Use
* @{
The DEBUG driver can be used as follows:
Implement DBG hook:
- printf func: define new HAL_SYSLOG in hal_conf.h or use HAL_DBG_Printf() in default;
- assert func: redefine AssertFailed().
Define debug level in hal_conf.h:
- HAL_DBG_ON: print master switch;
- HAL_DBG_INFO_ON: information printing switch;
- HAL_DBG_WRN_ON: information printing switch;
- HAL_DBG_ERR_ON: information printing switch;
- HAL_ASSERT_ON: Support assert.
APIS:
- printf information by calling HAL_DBG();
- printf warning by calling HAL_DBG_WRN();
- printf error by calling HAL_DBG_ERR();
- do assert by calling HAL_ASSERT().
@} */
#include "hal_base.h"
#include "hal_debug.h"
/** @defgroup DEBUG_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
/********************* Private Structure Definition **************************/
/********************* Private Variable Definition ***************************/
/********************* Private Function Definition ***************************/
/** @} */
/********************* Public Function Definition ****************************/
/** @defgroup DEBUG_Exported_Functions_Group5 Other Functions
This section provides functions allowing to init and deinit module as follows:
* @{
*/
/**
* @brief Reports the name of the source file and the source line number
* where the HAL_ASSERT error has occurred.
* @param file: pointer to the source file name
* @param line: HAL_ASSERT error line source number
*/
__attribute__((weak)) void HAL_AssertFailed(const char *file, uint32_t line)
{
HAL_DBG_ERR("assert failed at %s %lu\n", file, line);
while (1) {
;
}
}
/**
* @brief format hex print.
* @param s: head tag for every new line.
* @param buf: buffer for printing.
* @param width: every single printed object width.
* @param len: the number of printed objects.
* @return HAL_Status: HAL_OK.
* sum = width * len (BYTE).
*/
HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len)
{
#ifdef HAL_DBG_ON
uint32_t i, j;
unsigned char *p8 = (unsigned char *)buf;
unsigned short *p16 = (unsigned short *)buf;
uint32_t *p32 = (uint32_t *)buf;
j = 0;
for (i = 0; i < len; i++) {
if (j == 0) {
HAL_SYSLOG("[HAL_DBG_HEX] %s %p + 0x%lx:", s, buf, i * width);
}
if (width == 4) {
HAL_SYSLOG("0x%08lx,", p32[i]);
} else if (width == 2) {
HAL_SYSLOG("0x%04x,", p16[i]);
} else {
HAL_SYSLOG("0x%02x,", p8[i]);
}
if (++j >= 16) {
j = 0;
HAL_SYSLOG("\n");
}
}
HAL_SYSLOG("\n");
#endif
return HAL_OK;
}
#ifdef HAL_DBG_USING_HAL_PRINTF
static void reverse(char *start, char *end)
{
while (start < end) {
char temp = *start;
*start = *end;
*end = temp;
start++;
end--;
}
}
#ifdef __GNUC__
extern int _write(int fd, char *ptr, int len);
#endif
/**
* @brief format and print data
* @param format: format printf param. only support: \%d, \%s, \%ld, \%lld
* @return int32_t.
*/
__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
{
static char g_printf_buf[HAL_PRINTF_BUF_SIZE];
char *str = g_printf_buf;
int32_t len = 0;
va_list args;
va_start(args, format);
while (*format != '\0') {
if (*format == '%') {
format++;
if (*format == 'd') {
int i = va_arg(args, int);
char *start = str;
do {
*str++ = '0' + (i % 10);
i /= 10;
} while (i > 0);
reverse(start, str - 1);
} else if (*format == 's') {
char *s = va_arg(args, char *);
while (*s) {
*str++ = *s++;
}
} else if (*format == 'l') {
format++;
if (*format == 'd') {
long i = va_arg(args, long);
char *start = str;
do {
*str++ = '0' + (i % 10);
i /= 10;
} while (i > 0);
reverse(start, str - 1);
} else if (*format == 'l') {
format++;
if (*format == 'd') {
long long int i = va_arg(args, long long int);
char *start = str;
do {
*str++ = '0' + (i % 10);
i /= 10;
} while (i > 0);
reverse(start, str - 1);
}
}
}
} else {
*str++ = *format;
}
format++;
}
*str = '\0';
va_end(args);
len = str - g_printf_buf;
#ifdef __GNUC__
return _write(2, g_printf_buf, len);
#else
for (int i = 0; i < len; i++) {
fputc(g_printf_buf[i], stdout);
}
return len;
#endif
}
#else
/**
* @brief format and print data
* @param format: format printf param.
* @return int32_t.
*/
__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
{
return 0;
}
#endif /* HAL_DBG_USING_HAL_PRINTF */
/** @} */
/** @} */
/** @} */
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gpio.c
+577
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@@ -0,0 +1,577 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_base.h"
#include "hal_pinctrl.h"
#include "hal_gpio.h"
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_How_To_Use How To Use
* @{
The GPIO driver can be used as follows:
APIs for GPIO io read write:
1. HAL_GPIO_GetPinLevel() to get EXT port level.
2. HAL_GPIO_SetPinLevel() to set io level.
3. HAL_GPIO_SetPinDirection() to set io direction.
APIs for GPIO IRQ:
1. HAL_GPIO_EnableIRQ() to enable a GPIO IRQ.
2. HAL_GPIO_DisableIRQ() to disable a GPIO IRQ.
3. HAL_GPIO_IRQHandler() to handle GPIO IRQ isr.
4. HAL_GPIO_IRQDispatch() to dispatch GPIO IRQ, should be implemented by User.
Please open the macro definition HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED to support
APIs for GPIO virtual model:
1. HAL_GPIO_EnableVirtualModel() to enable a GPIO virtual model.
2. HAL_GPIO_DisableVirtualModel() to disable a GPIO virtual model.
3. HAL_GPIO_SetVirtualModel() to configure GPIO pins virtual model.
@} */
/** @defgroup GPIO_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */
/********************* Private Function Definition ***************************/
/**
* @brief Set the GPIO IRQ end of interrupt(EOI).
* @param pGPIO: The pointer of GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
*/
static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
pGPIO->PORT_EOI_H = pin | (pin >> 16);
} else {
pin &= 0x0000FFFF;
pGPIO->PORT_EOI_L = pin | (pin << 16);
}
#else
{
pGPIO->PORTA_EOI = pin;
}
#endif
}
/**
* @brief Get GPIO all pins irq type.
* @param pGPIO: the GPIO struct.
* @return uint32_t: type value.
*/
static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
{
uint32_t type;
#if (GPIO_VER_ID == 0x01000C2BU)
type = (pGPIO->INT_TYPE_L & 0xffff);
type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16);
#else
type = pGPIO->INTTYPE_LEVEL;
#ifdef GPIO_INT_BOTHEDGE_OFFSET
type |= pGPIO->INT_BOTHEDGE;
#endif
#endif
return type;
}
/**
* @brief Get GPIO all pins irq status.
* @param pGPIO: the GPIO struct.
* @return uint32_t: status value.
*/
static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO)
{
return pGPIO->INT_STATUS;
}
/** @} */
/********************* Public Function Definition ***************************/
/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions
This section provides functions allowing to get the status of the module:
* @{
*/
/**
* @brief GPIO Configure IRQ trigger type.
* @param pGPIO: The pointer of GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @param mode: The value defined in @ref eGPIO_intType.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode)
{
uint32_t both = 0, type = 0, plar = 0;
UNUSED(both);
switch (mode) {
case GPIO_INT_TYPE_EDGE_RISING:
type = 1;
plar = 1;
both = 0;
break;
case GPIO_INT_TYPE_EDGE_FALLING:
type = 1;
plar = 0;
both = 0;
break;
case GPIO_INT_TYPE_LEVEL_HIGH:
type = 0;
plar = 1;
both = 0;
break;
case GPIO_INT_TYPE_LEVEL_LOW:
type = 0;
plar = 0;
both = 0;
break;
case GPIO_INT_TYPE_EDGE_BOTH:
type = 0;
plar = 0;
both = 1;
break;
default:
return HAL_INVAL;
}
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin);
pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin);
} else {
pin &= 0x0000FFFF;
pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16);
pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16);
pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16);
}
#else
{
pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin));
pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin));
#ifdef GPIO_INT_BOTHEDGE_OFFSET
pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin));
#endif
}
#endif
return HAL_OK;
}
/**
* @brief Set GPIO direction.
* @param pGPIO: the GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @param direction: direction value defined in @ref eGPIO_pinDirection.
* @return HAL_Status: HAL_OK if success.
*/
HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
{
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
} else {
pin &= 0x0000FFFF;
pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16);
}
#else
if (direction == GPIO_OUT) {
pGPIO->SWPORTA_DDR |= pin;
} else {
pGPIO->SWPORTA_DDR &= ~pin;
}
#endif
return HAL_OK;
}
/**
* @brief Set GPIO direction.
* @param pGPIO: the GPIO struct.
* @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
* @param direction: value defined in @ref eGPIO_pinDirection.
* @return HAL_Status: HAL_OK if success.
*/
HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction)
{
uint8_t pin;
HAL_Status rc;
HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
for (pin = 0; pin < 32; pin++) {
if (mPins & (1 << pin)) {
rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction);
if (rc) {
return rc;
}
}
}
return HAL_OK;
}
/**
* @brief Get GPIO Pin data direction value.
* @param pGPIO: the GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @retval eGPIO_pinDirection: data direction value.
*/
eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
eGPIO_pinDirection direction;
uint32_t value;
#if (GPIO_VER_ID == 0x01000C2BU)
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
#else
value = pGPIO->SWPORTA_DDR & pin;
#endif
if (value != (uint32_t)GPIO_IN) {
direction = GPIO_OUT;
} else {
direction = GPIO_IN;
}
return direction;
}
/**
* @brief Set GPIO pin level.
* @param pGPIO: The pointer of GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @param level: The level defined in @ref eGPIO_pinLevel.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
{
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
} else {
pin &= 0x0000FFFF;
pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16);
}
#else
if (level == GPIO_HIGH) {
pGPIO->SWPORTA_DR |= pin;
} else {
pGPIO->SWPORTA_DR &= ~pin;
}
#endif
return HAL_OK;
}
/**
* @brief Set GPIO pin level.
* @param pGPIO: The pointer of GPIO struct.
* @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
* @param level: The level defined in @ref eGPIO_pinLevel.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level)
{
uint8_t pin;
HAL_Status rc;
HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
for (pin = 0; pin < 32; pin++) {
if (mPins & (1 << pin)) {
rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level);
if (rc) {
return rc;
}
}
}
return HAL_OK;
}
/** @} */
/** @defgroup GPIO_Exported_Functions_Group2 IO Functions
This section provides functions allowing to IO controlling:
* @{
*/
/**
* @brief Get GPIO Pin data value.
* @param pGPIO: the GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @retval eGPIO_pinLevel: data value.
*/
eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
eGPIO_pinLevel level;
uint32_t value;
#if (GPIO_VER_ID == 0x01000C2BU)
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
#else
value = pGPIO->SWPORTA_DR & pin;
#endif
if (value != (uint32_t)GPIO_LOW) {
level = GPIO_HIGH;
} else {
level = GPIO_LOW;
}
return level;
}
/**
* @brief Get GPIO Pin ext bank level.
* @param pGPIO: the GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @retval GPIO_PinState: ext bank value.
*/
eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
uint32_t value;
#if (GPIO_VER_ID == 0x01000C2BU)
value = (pGPIO->EXT_PORT & pin);
#else
value = (pGPIO->EXT_PORTA & pin);
#endif
return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH;
}
/**
* @brief Get GPIO Pin ext bank level.
* @param pGPIO: the GPIO struct.
* @retval uint32_t: ext bank value.
*/
uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
{
uint32_t value;
#if (GPIO_VER_ID == 0x01000C2BU)
value = (pGPIO->EXT_PORT);
#else
value = (pGPIO->EXT_PORTA);
#endif
return value;
}
/** @} */
/** @defgroup GPIO_Exported_Functions_Group3 Other Functions
* @{
*/
/**
* @brief Set GPIO irq enable.
* @param pGPIO: The pointer of GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
*/
void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
pGPIO->INT_MASK_H = pin;
#endif
pGPIO->INT_EN_H = pin | (pin >> 16);
} else {
pin &= 0x0000FFFF;
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
pGPIO->INT_MASK_L = pin << 16;
#endif
pGPIO->INT_EN_L = pin | (pin << 16);
}
#else
{
pGPIO->INTEN |= pin;
pGPIO->INTMASK &= ~pin;
}
#endif
}
/**
* @brief Set GPIO irq disable.
* @param pGPIO: The pointer of GPIO struct.
* @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
*/
void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{
#if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000;
pGPIO->INT_EN_H = pin;
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
pGPIO->INT_MASK_H = pin | (pin >> 16);
#endif
} else {
pin &= 0x0000FFFF;
pGPIO->INT_EN_L = pin << 16;
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
pGPIO->INT_MASK_L = pin | (pin << 16);
#endif
}
#else
{
pGPIO->INTEN &= ~pin;
pGPIO->INTMASK |= pin;
}
#endif
}
/**
* @brief GPIO IRQ callbacks.
* @param bank: The bank id.
* @param pin: The true pin index, 0~31.
* NOTE: This function Should not be modified, when the callback is needed,
* the HAL_GPIO_IRQDispatch could be implemented in the user file.
*/
__attribute__((weak)) void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin)
{
UNUSED(bank);
UNUSED(pin);
}
/**
* @brief GPIO IRQ hanlder.
* @param pGPIO: The pointer of GPIO struct.
* @param bank: The bank id.
*/
void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
{
uint32_t stat, type, clear;
uint32_t i;
uint32_t pin;
stat = GPIO_GetIntStatus(pGPIO);
type = GPIO_GetIntType(pGPIO);
/* Then process each pending GPIO interrupt */
for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) {
clear = 0x1U << i;
pin = HAL_BIT(i);
if ((stat & clear) != 0x0U) {
/* If gpio is Edge-sensitive triggered, clear eoi */
if (type & clear) {
GPIO_SetEOI(pGPIO, pin);
}
/* Remove the pending interrupt bit from the clear */
stat &= ~clear;
/* And disptach the GPIO interrupt to the handler */
HAL_GPIO_IRQDispatch(bank, i);
}
}
}
#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED
/**
* @brief GPIO virtual model enable.
* @param pGPIO: The pointer of GPIO struct.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
{
#if (GPIO_VER_ID == 0x01000C2BU)
pGPIO->GPIO_VIRTUAL_EN = 0x10001;
return HAL_OK;
#endif
return HAL_ERROR;
}
/**
* @brief GPIO virtual model disable.
* @param pGPIO: The pointer of GPIO struct.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
{
#if (GPIO_VER_ID == 0x01000C2BU)
pGPIO->GPIO_VIRTUAL_EN = 0x10000;
return HAL_OK;
#endif
return HAL_ERROR;
}
/**
* @brief GPIO Configure pins for virtual model.
* @param pGPIO: The pointer of GPIO struct.
* @param pins: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
* @param vmode: The value defined in @ref eGPIO_VirtualModel.
* @return HAL_Status.
*/
HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
{
#if (GPIO_VER_ID == 0x01000C2BU)
uint32_t low_pins, high_pins;
low_pins = pin & 0x0000ffff;
high_pins = (pin & 0xffff0000) >> 16;
/* Support OS_A and OS_B */
if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
pGPIO->GPIO_REG_GROUP_L = low_pins << 16;
pGPIO->GPIO_REG_GROUP_H = high_pins << 16;
} else {
pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16);
pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16);
}
return HAL_OK;
#endif
return HAL_ERROR;
}
#endif /* HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED */
/** @} */
/** @} */
/** @} */
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_pinctrl_v2.c
+565
View File
@@ -0,0 +1,565 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_base.h"
#include "hal_def.h"
#include "hal_pinctrl.h"
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup PINCTRL
* @{
*/
/** @defgroup PINCTRL_How_To_Use How To Use
* @{
The pinctrl setting registers actually is bus grf registers, which include
iomux, drive strength, pull mode, slew rate and schmitt trigger.
The pinctrl driver provides APIs:
- HAL_PINCTRL_SetIOMUX() to set pin iomux
- HAL_PINCTRL_SetParam() to set pin iomux/drive/pull/slewrate/schmitt/ie
Example:
HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
GPIO_PIN_A0 | // I2S_IN_SCLK
GPIO_PIN_A1 | // I2S_IN_LRCK
GPIO_PIN_A2 | // I2S_IN_SDI0
GPIO_PIN_A3, // I2S_IN_SDI1
PIN_CONFIG_MUX_FUNC2);
HAL_PINCTRL_SetParam(GPIO_BANK0,
GPIO_PIN_A0 | // I2S_IN_SCLK
GPIO_PIN_A1 | // I2S_IN_LRCK
GPIO_PIN_A2 | // I2S_IN_SDI0
GPIO_PIN_A3, // I2S_IN_SDI1
PIN_CONFIG_MUX_FUNC2 |
PIN_CONFIG_PUL_DOWN |
PIN_CONFIG_DRV_LEVEL2 |
PIN_CONFIG_SRT_FAST |
PIN_CONFIG_SMT_ENABLE);
@} */
/** @defgroup PINCTRL_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
#define _TO_MASK(w) ((1U << (w)) - 1U)
#define _TO_OFFSET(p, w) ((p) * (w))
#define RK_GEN_VAL(p, v, w) ((_TO_MASK(w) << (_TO_OFFSET(p, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(p, w)))
/*
* Use HAL_DBG("pinctrl: write val = 0x%lx to register %p\n", VAL, &REG);
* and HAL_DBG("pinctrl: readback register %p = 0x%lx\n", &REG, REG);
* for debug
*/
#define _PINCTRL_WRITE(REG, DATA) \
{ \
REG = DATA; \
}
#if defined(GRF_GPIO0A_IOMUX_OFFSET)
#define IOMUX_BIT_PER_PIN (2)
#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN)
#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX)
#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define SET_IOMUX(_GPIO, _PORT, pin, val) RK_SET_IOMUX_0(_GPIO, _PORT, pin, val)
#elif defined(GRF_GPIO0A_IOMUX_H_OFFSET)
#define IOMUX_BIT_PER_PIN (4)
#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN)
#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_L)
#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_H)
#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define SET_IOMUX(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 4) { \
RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
} \
}
#elif defined(GRF_GPIO0A_IOMUX_0_OFFSET)
#define IOMUX_BIT_PER_PIN (8)
#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN)
#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_0)
#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_1)
#define IOMUX_2(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_2)
#define IOMUX_3(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_3)
#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_IOMUX_2(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_2(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_IOMUX_3(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_3(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define RK_SET_IOMUX_2(B, P, p, v) SET_IOMUX_2(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define RK_SET_IOMUX_3(B, P, p, v) SET_IOMUX_3(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
#define SET_IOMUX(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 2) { \
RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 4) { \
RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 6) { \
RK_SET_IOMUX_2(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_IOMUX_3(_GPIO, _PORT, pin, val); \
} \
}
#endif
#if defined(GRF_GPIO0A_DS_OFFSET)
#define DS_BIT_PER_PIN (2)
#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN)
#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS)
#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define SET_DS(_GPIO, _PORT, pin, val) RK_SET_DS_0(_GPIO, _PORT, pin, val)
#elif defined(GRF_GPIO0A_DS_H_OFFSET)
#define DS_BIT_PER_PIN (4)
#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN)
#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_L)
#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_L)
#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define SET_DS(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 4) { \
RK_SET_DS_0(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_DS_1(_GPIO, _PORT, pin, val); \
} \
}
#elif defined(GRF_GPIO0A_DS_0_OFFSET)
#define DS_BIT_PER_PIN (8)
#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN)
#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_0)
#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_1)
#define DS_2(__B, __P) (GRF->GPIO##__B##__P##_DS_2)
#define DS_3(__B, __P) (GRF->GPIO##__B##__P##_DS_3)
#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_DS_2(_B, _P, p, v, w) _PINCTRL_WRITE(DS_2(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_DS_3(_B, _P, p, v, w) _PINCTRL_WRITE(DS_3(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define RK_SET_DS_2(B, P, p, v) SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define RK_SET_DS_3(B, P, p, v) SET_DS_3(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
#define SET_DS(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 2) { \
RK_SET_DS_0(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 4) { \
RK_SET_DS_1(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 6) { \
RK_SET_DS_2(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_DS_3(_GPIO, _PORT, pin, val); \
} \
}
#endif
#if defined(GRF_GPIO0A_P_OFFSET)
#define P_BIT_PER_PIN (2)
#define P_PIN_PER_REG (16 / P_BIT_PER_PIN)
#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P)
#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define SET_P(_GPIO, _PORT, pin, val) RK_SET_P_0(_GPIO, _PORT, pin, val)
#elif defined(GRF_GPIO0A_P_H_OFFSET)
#define P_BIT_PER_PIN (4)
#define P_PIN_PER_REG (16 / P_BIT_PER_PIN)
#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_L)
#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_L)
#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define SET_P(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 4) { \
RK_SET_P_0(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_P_3(_GPIO, _PORT, pin, val); \
} \
}
#elif defined(GRF_GPIO0A_P_0_OFFSET)
#define P_BIT_PER_PIN (8)
#define P_PIN_PER_REG (16 / P_BIT_PER_PIN)
#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_0)
#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_1)
#define P_2(__B, __P) (GRF->GPIO##__B##__P##_P_2)
#define P_3(__B, __P) (GRF->GPIO##__B##__P##_P_3)
#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_P_2(_B, _P, p, v, w) _PINCTRL_WRITE(P_2(_B, _P), RK_GEN_VAL(p, v, w))
#define SET_P_3(_B, _P, p, v, w) _PINCTRL_WRITE(P_3(_B, _P), RK_GEN_VAL(p, v, w))
#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define RK_SET_P_2(B, P, p, v) SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define RK_SET_P_3(B, P, p, v) SET_P_3(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
#define SET_P(_GPIO, _PORT, pin, val) \
{ \
if ((pin % 8) < 2) { \
RK_SET_P_0(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 4) { \
RK_SET_P_1(_GPIO, _PORT, pin, val); \
} else if ((pin % 8) < 6) { \
RK_SET_P_2(_GPIO, _PORT, pin, val); \
} else { \
RK_SET_P_3(_GPIO, _PORT, pin, val); \
} \
}
#endif
#ifdef SET_IOMUX
#define PINCTRL_SET_IOMUX(bank, pin, val) \
{ \
if (pin < 8) { \
SET_IOMUX(bank, A, pin, val); \
} else if (pin < 16) { \
SET_IOMUX(bank, B, pin, val); \
} else if (pin < 24) { \
SET_IOMUX(bank, C, pin, val); \
} else { \
SET_IOMUX(bank, D, pin, val); \
} \
}
#endif
#ifdef SET_DS
#define PINCTRL_SET_DS(bank, pin, val) \
{ \
if (pin < 8) { \
SET_DS(bank, A, pin, val); \
} else if (pin < 16) { \
SET_DS(bank, B, pin, val); \
} else if (pin < 24) { \
SET_DS(bank, C, pin, val); \
} else { \
SET_DS(bank, D, pin, val); \
} \
}
#endif
#ifdef SET_P
#define PINCTRL_SET_P(bank, pin, val) \
{ \
if (pin < 8) { \
SET_P(bank, A, pin, val); \
} else if (pin < 16) { \
SET_P(bank, B, pin, val); \
} else if (pin < 24) { \
SET_P(bank, C, pin, val); \
} else { \
SET_P(bank, D, pin, val); \
} \
}
#endif
/********************* Private Variable Definition ***************************/
/********************* Private Function Definition ***************************/
/**
* @brief Private function to set iomux for one pin.
* @param bank: pin bank channel.
* @param pin: pin index, 0~31.
* @param param: value to write.
* @return HAL_Status.
*/
static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t data)
{
#ifdef PINCTRL_SET_IOMUX
switch (bank) {
#ifdef GPIO0
case 0:
PINCTRL_SET_IOMUX(0, pin, data);
break;
#endif
#ifdef GPIO1
case 1:
PINCTRL_SET_IOMUX(1, pin, data);
break;
#endif
#ifdef GPIO2
case 2:
PINCTRL_SET_IOMUX(2, pin, data);
break;
#endif
#ifdef GPIO3
case 3:
PINCTRL_SET_IOMUX(3, pin, data);
break;
#endif
#ifdef GPIO4
case 4:
#ifdef SOC_RV1126
if (pin < 2) {
GRF->GPIO4A_IOMUX_L = RK_GEN_VAL(pin % IOMUX_PIN_PER_REG, data, IOMUX_BIT_PER_PIN);
}
#else
PINCTRL_SET_IOMUX(4, pin, data);
#endif
break;
#endif
default:
HAL_DBG("unknown gpio%d\n", bank);
break;
}
return HAL_OK;
#else
return HAL_ERROR;
#endif
}
/**
* @brief Private function to set drive strength for one pin.
* @param bank: pin bank channel.
* @param pin: pin index, 0~31.
* @param param: value to write.
* @return HAL_Status.
*/
static HAL_Status PINCTRL_SetDS(eGPIO_bankId bank, uint8_t pin, uint32_t data)
{
#ifdef PINCTRL_SET_DS
switch (bank) {
#ifdef GPIO0
case 0:
PINCTRL_SET_DS(0, pin, data);
break;
#endif
#ifdef GPIO1
case 1:
PINCTRL_SET_DS(1, pin, data);
break;
#endif
#ifdef GPIO2
case 2:
PINCTRL_SET_DS(2, pin, data);
break;
#endif
#ifdef GPIO3
case 3:
PINCTRL_SET_DS(3, pin, data);
break;
#endif
#ifdef GPIO4
case 4:
#ifdef SOC_RV1126
if (pin < 2) {
GRF->GPIO4A_DS_L = RK_GEN_VAL(pin % DS_PIN_PER_REG, data, DS_BIT_PER_PIN);
}
#else
PINCTRL_SET_DS(4, pin, data);
#endif
break;
#endif
default:
HAL_DBG("unknown gpio%d\n", bank);
break;
}
return HAL_OK;
#else
return HAL_ERROR;
#endif
}
/**
* @brief Private function to set pupd for one pin.
* @param bank: pin bank channel.
* @param pin: pin index, 0~31.
* @param param: value to write.
* @return HAL_Status.
*/
static HAL_Status PINCTRL_SetPUPD(eGPIO_bankId bank, uint8_t pin, uint32_t data)
{
#ifdef PINCTRL_SET_P
switch (bank) {
#ifdef GPIO0
case 0:
#ifdef SOC_RV1126
if (pin < 8) {
SET_P(0, A, pin, data);
} else if (pin < 16) {
SET_P(0, B, pin, data);
} else if (pin < 20) {
GRF->GPIO0C_P_L = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
} else if (pin < 24) {
GRF->GPIO0C_P_H = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
} else {
SET_P(0, D, pin, data);
}
#else
PINCTRL_SET_P(0, pin, data);
#endif
break;
#endif
#ifdef GPIO1
case 1:
PINCTRL_SET_P(1, pin, data);
break;
#endif
#ifdef GPIO2
case 2:
PINCTRL_SET_P(2, pin, data);
break;
#endif
#ifdef GPIO3
case 3:
PINCTRL_SET_P(3, pin, data);
break;
#endif
#ifdef GPIO4
case 4:
#ifdef SOC_RV1126
if (pin < 2) {
GRF->GPIO4A_P = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
}
#else
PINCTRL_SET_P(4, pin, data);
#endif
break;
#endif
default:
HAL_DBG("unknown gpio%d\n", bank);
break;
}
return HAL_OK;
#else
return HAL_ERROR;
#endif
}
/**
* @brief Private function to configure one pin.
* @param bank: pin bank channel defined in @ref eGPIO_bankId.
* @param pin: pin index, 0~31.
* @param param: multi params defined in @ref ePINCTRL_configParam,
* @return HAL_Status.
*/
static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param)
{
HAL_Status rc = HAL_OK;
if (param & FLAG_MUX) {
rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX));
}
if (param & FLAG_PUL) {
rc |= PINCTRL_SetPUPD(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL));
}
if (param & FLAG_DRV) {
rc |= PINCTRL_SetDS(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV));
}
return rc;
}
/** @} */
/********************* Public Function Definition ****************************/
/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions
This section provides functions allowing to suspend and resume the module:
* @{
*/
/** @} */
/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions
This section provides functions allowing to init and deinit the module:
* @{
*/
HAL_Status HAL_PINCTRL_Init(void)
{
return HAL_OK;
}
HAL_Status HAL_PINCTRL_DeInit(void)
{
return HAL_OK;
}
/** @} */
/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions
* @{
*/
/**
* @brief Public function to configure for multi pins.
* @param bank: pin bank channel defined in eGPIO_bankId.
* @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
* @param param: multi params defined in @ref ePINCTRL_configParam.
* @return HAL_Status.
*/
HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
{
uint8_t pin;
HAL_Status rc;
HAL_ASSERT(bank < GPIO_BANK_NUM);
if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SRT | FLAG_SMT))) {
return HAL_OK;
}
for (pin = 0; pin < 32; pin++) {
if (mPins & (1 << pin)) {
rc = PINCTRL_SetPinParam(bank, pin, param);
if (rc) {
return rc;
}
}
}
return HAL_OK;
}
/**
* @brief Public function to set iomux for multi pins.
* @param bank: pin bank channel defined in eGPIO_bankId.
* @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
* @param param: multi params defined in @ref ePINCTRL_configParam.
* @return HAL_Status.
*/
HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
{
return HAL_PINCTRL_SetParam(bank, mPins, param);
}
/** @} */
/** @} */
/** @} */
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_timer.c
+306
View File
@@ -0,0 +1,306 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_base.h"
#include "hal_def.h"
#include "hal_timer.h"
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup TIMER
* @{
*/
/** @defgroup TIMER_How_To_Use How To Use
* @{
The TIMER driver can be used as follows:
- IT mode: Resgister TIMER handler.
- Initialize the TIMER by calling HAL_TIMER_Init():
- Set TIMER count by calling HAL_TIMER_SetCount().
- Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT().
- Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT().
SYS_TIMER
- SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init.
@} */
/** @defgroup TIMER_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT)
#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT)
/********************* Private Structure Definition **************************/
/********************* Private Variable Definition ***************************/
/********************* Private Function Definition ***************************/
/** @} */
/********************* Public Function Definition ****************************/
/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions
This section provides functions allowing to init and deinit module as follows:
* @{
*/
/**
* @brief Timer init.
* @param pReg: Choose TIMER.
* @param mode: Choose TIMER mode.
* @return HAL_Status.
*/
HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT);
return HAL_OK;
}
/**
* @brief System Timer init.
* @return HAL_Status.
* @attention this API allow direct use in the HAL layer. SYS_TTIMER is used for delay system.
*/
HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
if (READ_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK)) {
return HAL_OK;
}
WRITE_REG(pReg->CONTROLREG, TIMER_FREE_RUNNING);
pReg->LOAD_COUNT[0] = 0xFFFFFFFFU;
pReg->LOAD_COUNT[1] = 0xFFFFFFFFU;
CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
return HAL_OK;
}
/**
* @brief Timer deinit.
* @param pReg: Choose TIMER.
* @return HAL_Status.
*/
HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
WRITE_REG(pReg->CONTROLREG, 0);
return HAL_OK;
}
/** @} */
/** @defgroup TIMER_Exported_Functions_Group5 Other Functions
* @{
*/
/**
* @brief Start TIMER counter.
* @param pReg: Choose TIMER.
* @return HAL_Status.
*/
HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
return HAL_OK;
}
/**
* @brief Stop TIMER counter.
* @param pReg: Choose TIMER.
* @return HAL_Status.
* Just disable TIMER, and keep TIMER configuration.
*/
HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
return HAL_OK;
}
/**
* @brief Start TIMER counter in interrupt mode.
* @param pReg: Choose TIMER.
* @return HAL_Status.
*/
HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK);
return HAL_OK;
}
/**
* @brief Stop TIMER counter in interrupt mode.
* @param pReg: Choose TIMER.
* @return HAL_Status.
* Just disable TIMER, and keep TIMER configuration.
*/
HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg)
{
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
return HAL_OK;
}
/**
* @brief Set TIMER count number.
* @param pReg: Choose TIMER.
* @param timerCount: TIMER counter loading number.
* @return HAL_Status.
* Set timer count number.
*/
HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount)
{
uint64_t loadCount = 0;
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
#ifdef SYS_TIMER
if (pReg == SYS_TIMER) {
return HAL_BUSY;
}
#endif
loadCount = timerCount;
pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff);
pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff);
return HAL_OK;
}
/**
* @brief Get TIMER count number.
* @param pReg: Choose TIMER.
* @return uint64_t: Current conut number.
*/
HAL_SECTION_SRAM_CODE
uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg)
{
uint32_t high, low, temp;
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
do {
high = pReg->CURRENT_VALUE[1];
low = pReg->CURRENT_VALUE[0];
temp = pReg->CURRENT_VALUE[1];
} while (high != temp);
return ((uint64_t)high << 32) | low;
}
/**
* @brief Clear TIMER interrupt status.
* @param pReg: Choose TIMER.
* @return HAL_Status: HAL_OK.
*/
HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg)
{
uint32_t timeOut = 1000;
HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
pReg->INTSTATUS = 0x1;
while (pReg->INTSTATUS && timeOut) {
timeOut--;
}
if (timeOut == 0) {
return HAL_TIMEOUT;
} else {
return HAL_OK;
}
}
/**
* @brief TIMER0 interrupt handler.
* @return HAL_Status: HAL_OK.
* Clear interrupt status.
*/
__attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void)
{
HAL_TIMER_ClrInt(TIMER0);
return HAL_OK;
}
/**
* @brief TIMER1 interrupt handler.
* @return HAL_Status: HAL_OK.
* Clear interrupt status.
*/
__attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void)
{
HAL_TIMER_ClrInt(TIMER1);
return HAL_OK;
}
/** @} */
/** @} */
/** @} */
Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/test_gmac.c
+800
View File
@@ -0,0 +1,800 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "hal_bsp.h"
#include "hal_base.h"
#include "hal_gmac.h"
#include "hal_pinctrl.h"
#include "hal_debug.h"
#include "hal_timer.h"
#include "hal_cache.h"
#include "hal_gpio.h"
#include "hal_cru.h"
#include "libserial.h"
#include "stdlib.h"
/*************************** GMAC DRIVER ****************************/
/***************************** MACRO Definition ******************************/
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
#define CONFIG_SYS_NONCACHED_MEMORY (4 << 20) /* 4M */
/* 1MB granularity */
#define MMU_SECTION_SIZE (1 << 20)
/***************************** Structure Definition **************************/
/***************************** Function Declare ******************************/
/********************* Private MACRO Definition ******************************/
#define GMAC_BUS_MAX 2
#define ARCH_DMA_MINALIGN 64
#define GMAC_DESCRIPTOR_SIZE 16
#define GMAC_DESCRIPTORS_TX 8
#define GMAC_DESCRIPTORS_RX 8
#define GMAC_DESC_TX_SIZE HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_TX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
#define GMAC_DESC_RX_SIZE HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_RX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
#define GMAC_RX_BUFFER_SIZE (GMAC_DESCRIPTORS_RX * HAL_GMAC_MAX_PACKET_SIZE)
#define GMAC_TX_BUFFER_SIZE (GMAC_DESCRIPTORS_TX * HAL_GMAC_MAX_PACKET_SIZE)
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
#define BMCR_PDOWN 0x0800 /* Enable low power state */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset to default state */
#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
#define GMAC_TEST_TIMES 1600
/********************* Private Structure Definition **************************/
/* GMAC consumer config data. */
struct GMAC_ETH_CONFIG {
struct GMAC_HANDLE instance;
const struct HAL_GMAC_DEV *halDev;
eGMAC_PHY_Interface mode;
uint32_t speed;
uint32_t maxSpeed;
uint16_t phyAddr;
bool extClk;
/* phy reset gpio */
struct GPIO_REG *resetGpioBank;
ePINCTRL_GPIO_PINS resetGpioNum;
uint32_t resetDelayMs[3];
int32_t txDelay;
int32_t rxDelay;
struct GMAC_Desc *txDescs;
struct GMAC_Desc *rxDescs;
uint8_t *txBuff;
uint8_t *rxBuff;
/* MAC address info, hw address */
uint8_t macAddr[6];
};
/********************* Private Variable Definition ***************************/
#ifdef NC_MEM_BASE
static const unsigned long os_no_cache_start = (unsigned long)NC_MEM_BASE;
#else
static const unsigned long os_no_cache_start = 0;
#endif
/*
* Reserve one MMU section worth of address space below the malloc() area that
* will be mapped uncached.
*/
static unsigned long noncached_start;
static unsigned long noncached_end;
static unsigned long noncached_next;
static unsigned int m_nocachemem_inited = 0;
static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
static struct GMAC_ETH_CONFIG ethConfigTable[] =
{
{
.halDev = &g_gmac0Dev,
.mode = PHY_INTERFACE_MODE_RGMII,
.maxSpeed = 1000,
.phyAddr = 1,
.extClk = false,
.resetGpioBank = GPIO2,
.resetGpioNum = GPIO_PIN_D3,
.resetDelayMs = { 0, 20, 100 },
.txDelay = 0x3C,
.rxDelay = 0x2f,
},
// {
// .halDev = &g_gmac1Dev,
// .mode = PHY_INTERFACE_MODE_RGMII,
// .maxSpeed = 1000,
// .phyAddr = 1,
// .extClk = false,
// .resetGpioBank = GPIO2,
// .resetGpioNum = GPIO_PIN_D1,
// .resetDelayMs = { 0, 20, 100 },
// .txDelay = 0x4f,
// .rxDelay = 0x26,
// },
};
/********************* Private Function Definition ***************************/
static void Dump_Hex(char *message, uint8_t *ptr, uint16_t buflen)
{
unsigned char *buf = (unsigned char *)ptr;
int i, j;
printf("%s package at %p, len: %d: \n", message, ptr, buflen);
for (i = 0; i < buflen; i += 16) {
printf("%08X: ", i);
for (j = 0; j < 16; j++) {
if (i + j < buflen) {
printf("%02X ", buf[i + j]);
} else {
printf(" ");
}
}
printf(" ");
for (j = 0; j < 16; j++) {
if (i + j < buflen) {
printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
}
}
printf("\n");
}
}
static void print_desc(struct GMAC_HANDLE *pGMAC)
{
struct GMAC_Desc *desc;
int nIndex;
printf("\n");
if (pGMAC->rxDescs) {
desc = pGMAC->rxDescs;
for (nIndex = 0; nIndex < pGMAC->rxSize; nIndex++) {
desc = pGMAC->rxDescs + nIndex;
printf("rx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
nIndex, (uint32_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
}
}
if (pGMAC->txDescs) {
desc = pGMAC->txDescs;
for (nIndex = 0; nIndex < pGMAC->txSize; nIndex++) {
desc = pGMAC->txDescs + nIndex;
printf("tx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
nIndex, (uint32_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
}
}
}
static void Dump_Regs(struct GMAC_HANDLE *pGMAC)
{
uint32_t *reg = (uint32_t *)pGMAC->pReg;
int i;
printf("\n");
for (i = 0; i < (0x200 / 0x4); i++) {
printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10,
*((volatile const uint32_t *)(reg + 0x4 * i)), *(volatile const uint32_t *)((reg + 0x4 * i + 1)),
*((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
}
reg = reg + 0x1000 / 4;
for (i = 0; i < (0x100 / 0x4); i++) {
printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10 + 0x1000,
*((volatile const uint32_t *)(reg + 0x4 * i)), *((volatile const uint32_t *)(reg + 0x4 * i + 1)),
*((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
}
}
static void PHY_Read(struct GMAC_HANDLE *pGMAC, uint32_t phyReg)
{
int data;
data = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyConfig.phyAddress, phyReg);
if (data >= 0) {
printf("PHY_Read: %02lX --> %08X\n", phyReg, data);
} else {
printf("PHY_Read: %02lX --> faild\n", phyReg);
}
}
static void PHY_Write(uint32_t phyReg, uint32_t data)
{
struct GMAC_HANDLE *pGMAC;
int status;
status = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyConfig.phyAddress, phyReg, data);
if (!status) {
printf("PHY_Write: %02lX --> %08lX\n", phyReg, data);
} else {
printf("PHY_Write: %02lX --> faild\n", phyReg);
}
}
static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
{
int data, i;
for (i = 0; i < 32; i++) {
data = HAL_GMAC_MDIORead(pGMAC, eth->phyAddr, i);
if (data < 0) {
printf("phy_dump: %d --> faild\n", i);
break;
}
if (i % 8 == 7) {
printf("%d --> %08X\n ", i, data);
} else {
printf("%d --> %08X\n\n", i, data);
}
}
printf("\n");
}
static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config)
{
if (config->resetGpioBank) {
HAL_GPIO_SetPinDirection(config->resetGpioBank,
config->resetGpioNum,
GPIO_OUT);
HAL_GPIO_SetPinLevel(config->resetGpioBank,
config->resetGpioNum,
GPIO_HIGH);
HAL_DelayMs(config->resetDelayMs[0]);
HAL_GPIO_SetPinLevel(config->resetGpioBank,
config->resetGpioNum,
GPIO_LOW);
HAL_DelayMs(config->resetDelayMs[1]);
HAL_GPIO_SetPinLevel(config->resetGpioBank,
config->resetGpioNum,
GPIO_HIGH);
HAL_DelayMs(config->resetDelayMs[2]);
}
}
static inline void NET_Random_ETHAddr(uint8_t *addr)
{
unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff;
uint8_t i;
for (i = 0; i < 6; i++) {
addr[i] = 0xae;
}
addr[0] &= 0xfe; /* clear multicast bit */
addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
}
static inline void NET_Random_Package(uint8_t *addr, uint16_t len)
{
unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff;
uint16_t i;
for (i = 0; i < len; i++) {
addr[i] = 0xae;
}
}
static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
uint8_t id)
{
HAL_Status status;
status = HAL_GMAC_PHYStartup(pGMAC);
if (status) {
printf("HAL_PHY_Startup() failed: %d\n", status);
return;
}
HAL_DelayMs(7000);
status = HAL_GMAC_PHYUpdateLink(pGMAC);
if (status == HAL_OK) {
if (pGMAC->phyStatus.link) {
status = HAL_GMAC_PHYParseLink(pGMAC);
if (PHY_SPEED_1000M == pGMAC->phyStatus.speed) {
printf("Phy%d: 1000M link speed\n", id);
} else if (PHY_SPEED_100M == pGMAC->phyStatus.speed) {
printf("Phy%d: 100M link speed\n", id);
} else {
printf("Phy%d: 10M link speed\n", id);
}
if (PHY_DUPLEX_HALF == pGMAC->phyStatus.duplex) {
printf("Phy%d: half dumplex\n", id);
} else {
printf("Phy%d: full dumplex\n", id);
}
if (pGMAC->phyStatus.pause) {
printf("Phy%d: flow control rx/tx\n", id);
} else {
printf("Phy%d: flow control off\n", id);
}
status = HAL_GMAC_AdjustLink(pGMAC, eth->txDelay, eth->rxDelay);
if (status != HAL_OK) {
printf("HAL_GMAC_AdjustLink() failed: %d\n", status);
}
printf("Phy%d: link up.\n", id);
} else {
printf("Phy%d: link down.\n", id);
}
}
}
/* interrupt service routine polling */
static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC)
{
HAL_Status status;
/* enter interrupt */
/* rt_interrupt_enter(); */
status = HAL_GMAC_IRQHandler(pGMAC);
if (status & DMA_HANLE_RX) {
/* a frame has been received */
return 1;
}
return 0;
/* leave interrupt */
/* rt_interrupt_leave(); */
}
static HAL_Status noncached_init(void)
{
unsigned long start, end;
size_t size;
if (os_no_cache_start <= 0) {
printf("Noncached_init failed, plase defined no cached memort\n");
return -1;
}
start = HAL_GMAC_ALIGN(os_no_cache_start, 64);
size = HAL_GMAC_ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
end = start + size;
noncached_start = start;
noncached_end = end;
noncached_next = start;
m_nocachemem_inited = 1;
return 0;
}
static unsigned long noncached_alloc(size_t size, size_t align)
{
if (!m_nocachemem_inited) {
if (noncached_init())
return (unsigned long)NULL;
}
unsigned long next = HAL_GMAC_ALIGN(noncached_next, align);
if (next >= noncached_end || (noncached_end - next) < size) {
return 0;
}
noncached_next = next + size;
return next;
}
static void *malloc_align(size_t size, size_t align)
{
void *align_ptr;
void *ptr;
size_t align_size;
/* align the alignment size to 4 byte */
align = ((align + 0x03) & ~0x03);
/* get total aligned size */
align_size = ((size + 0x03) & ~0x03) + align;
/* allocate memory block from heap */
ptr = malloc(align_size);
if (ptr != NULL) {
/* the allocated memory block is aligned */
if (((uint32_t)ptr & (align - 1)) == 0) {
align_ptr = (void *)((uint32_t)ptr + align);
} else {
align_ptr = (void *)(((uint32_t)ptr + (align - 1)) & ~(align - 1));
}
/* set the pointer before alignment pointer to the real pointer */
*((uint32_t *)((uint32_t)align_ptr - sizeof(void *))) = (uint32_t)ptr;
ptr = align_ptr;
}
return ptr;
}
static void free_align(void *ptr)
{
void *real_ptr;
real_ptr = (void *)*(uint32_t *)((uint32_t)ptr - sizeof(void *));
free(real_ptr);
}
/********************* Public Function Definition ****************************/
static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
uint16_t len)
{
uint8_t *ptr = NULL;
HAL_Status status;
if (!pGMAC->phyStatus.link) {
return -1;
}
/* Check the frame length. */
if (len > HAL_GMAC_MAX_FRAME_SIZE) {
return -1;
}
ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC);
memcpy(ptr, dstAddr, 6);
memcpy(ptr + 6, eth->macAddr, 6);
ptr[12] = 0x40;
ptr[13] = 0x06;
ptr[14] = 0x00;
ptr[15] = 0x01;
NET_Random_Package(ptr + 16, len - 16);
if (len > 60) {
/* index */
ptr[50] = pGMAC->txDescIdx;
}
/* dump packages */
Dump_Hex("Tx", ptr, len);
HAL_DCACHE_CleanByRange((uint32_t)ptr, len);
status = HAL_GMAC_Send(pGMAC, ptr, len);
if (status) {
printf("GMAC send failed: %d\n", status);
}
return status;
}
static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
{
uint8_t *ptr = NULL;
HAL_Status status;
int32_t size;
if (!pGMAC->phyStatus.link) {
return -1;
}
status = GMAC_ETH_IRQ(pGMAC);
ptr = HAL_GMAC_Recv(pGMAC, &size);
while (status && ptr) {
if (size > 0 && ptr) {
/* dump packages */
Dump_Hex("Rx", ptr, size);
HAL_DCACHE_InvalidateByRange((uint32_t)ptr, size);
HAL_GMAC_CleanRX(pGMAC);
} else {
printf("GMAC recv failed: %ld\n", size);
return -1;
}
ptr = HAL_GMAC_Recv(pGMAC, &size);
}
return 0;
}
static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
{
eth->rxDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_RX_SIZE, ARCH_DMA_MINALIGN);
eth->txDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_TX_SIZE, ARCH_DMA_MINALIGN);
if (!eth->rxDescs || !eth->txDescs)
return -1;
eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN);
eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN);
if (!eth->rxBuff || !eth->txBuff)
return -1;
memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE);
memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE);
memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE);
HAL_DCACHE_InvalidateByRange((uint32_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE);
memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE);
HAL_DCACHE_CleanByRange((uint32_t)eth->txBuff, GMAC_TX_BUFFER_SIZE);
HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxBuff, GMAC_DESCRIPTORS_RX);
HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txBuff, GMAC_DESCRIPTORS_TX);
print_desc(pGMAC);
return 0;
}
static HAL_Status GMAC_Init(uint8_t id)
{
struct GMAC_ETH_CONFIG *eth;
struct GMAC_HANDLE *pGMAC;
const struct HAL_GMAC_DEV *gmacDev;
struct GMAC_PHY_Config config;
eGMAC_PHY_Interface interface;
HAL_Status status;
uint32_t freq;
HAL_ASSERT(id < GMAC_BUS_MAX);
eth = &ethConfigTable[id];
if (!eth) {
return HAL_ERROR;
}
pGMAC = &eth->instance;
gmacDev = eth->halDev;
/* MAC init */
interface = eth->mode;
if (interface == PHY_INTERFACE_MODE_RGMII) {
HAL_CRU_ClkSetFreq(gmacDev->clkID, 125000000);
} else {
HAL_CRU_ClkSetFreq(gmacDev->clkID, 50000000);
}
freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID);
HAL_GMAC_Init(pGMAC, gmacDev->pReg, freq, interface, eth->extClk);
/* PHY Init */
config.speed = eth->speed;
config.maxSpeed = eth->maxSpeed;
config.duplexMode = PHY_DUPLEX_FULL;
config.neg = PHY_AUTONEG_ENABLE;
config.interface = interface;
config.phyAddress = eth->phyAddr;
config.features = 0;
status = HAL_GMAC_PHYInit(pGMAC, &config);
if (status) {
printf("HAL_PHY_Init() failed: %d\n", status);
return status;
}
/* MAC Address */
NET_Random_ETHAddr(eth->macAddr);
HAL_GMAC_WriteHWAddr(&eth->instance, eth->macAddr);
return 0;
}
/*************************** GMAC TEST ****************************/
#define GMAC_MAX_DEVICES 2
/**
* @brief Config iomux for GMAC0
*/
static void GMAC0_Iomux_Config(void)
{
/* GMAC0 iomux */
HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
GPIO_PIN_B6, /* gmac0_rxd0 */
PIN_CONFIG_MUX_FUNC1);
HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
GPIO_PIN_C3 | /* gmac0_mdc */
GPIO_PIN_C4 | /* gmac0_mdio */
GPIO_PIN_C0 | /* gmac0_rxdvcrs */
GPIO_PIN_B7 | /* gmac0_rxd1 */
GPIO_PIN_A3 | /* gmac0_rxd2 */
GPIO_PIN_A4 | /* gmac0_rxd3 */
GPIO_PIN_A6 | /* gmac0_txd2 */
GPIO_PIN_A7 | /* gmac0_txd3 */
GPIO_PIN_A5, /* gmac0_rxclk */
PIN_CONFIG_MUX_FUNC2);
HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
GPIO_PIN_B3 | /* gmac0_txd0 */
GPIO_PIN_B4 | /* gmac0_txd1 */
GPIO_PIN_B5, /* gmac0_txen */
PIN_CONFIG_MUX_FUNC1 | PIN_CONFIG_DRV_LEVEL2);
HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
GPIO_PIN_A7 | /* gmac0_txd3 */
GPIO_PIN_A6, /* gmac0_txd2 */
PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL2);
HAL_PINCTRL_SetIOMUX(GPIO_BANK2, /* gmac0_txclk */
GPIO_PIN_B0,
PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1);
#if 0
/* io-domian: 1.8v or 3.3v for vccio4 */
WRITE_REG_MASK_WE(GRF->IO_VSEL0,
GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK,
(1 << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT));
WRITE_REG_MASK_WE(GRF->IO_VSEL1,
GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK,
(0 << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT));
#endif
}
/**
* @brief Config iomux for GMAC1
*/
// static void GMAC1_M1_Iomux_Config(void)
// {
// /* GMAC1 M1 iomux */
// HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
// GPIO_PIN_B6 | /* gmac1_mdcm1 */
// GPIO_PIN_B7 | /* gmac1_mdiom1 */
// GPIO_PIN_B1 | /* gmac1_rxdvcrsm1 */
// GPIO_PIN_A7 | /* gmac1_rxd0m1 */
// GPIO_PIN_B0 | /* gmac1_rxd1m1 */
// GPIO_PIN_A1 | /* gmac1_rxd2m1 */
// GPIO_PIN_A2 | /* gmac1_rxd3m1 */
// GPIO_PIN_A6 | /* gmac1_txenm1 */
// GPIO_PIN_A3, /* gmac1_rxclkm1 */
// PIN_CONFIG_MUX_FUNC3);
// HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
// GPIO_PIN_A0, /* gmac1_txd1m1 */
// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL3);
// HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
// GPIO_PIN_A4 | /* gmac1_txd0m1 */
// GPIO_PIN_A5, /* gmac1_txd1m1 */
// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2);
// /* GMAC1 M1 iomux */
// HAL_PINCTRL_SetIOMUX(GPIO_BANK3,
// GPIO_PIN_D6 | /* gmac1_txd2m1 */
// GPIO_PIN_D7, /* gmac1_txd3m1 */
// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2);
// HAL_PINCTRL_IOFuncSelForGMAC1(IOFUNC_SEL_M1);
// #if 0
// /* io-domian: 1.8v or 3.3v for vccio6 */
// WRITE_REG_MASK_WE(GRF->IO_VSEL0,
// GRF_IO_VSEL0_POC_VCCIO6_SEL18_MASK,
// (1 << GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT));
// WRITE_REG_MASK_WE(GRF->IO_VSEL1,
// GRF_IO_VSEL1_POC_VCCIO6_SEL33_MASK,
// (0 << GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT));
// #endif
// }
static void GMAC_Iomux_Config(uint8_t id)
{
// if (id == 1) {
// GMAC1_M1_Iomux_Config();
// } else if (id == 0) {
GMAC0_Iomux_Config();
// }
}
/*************************** GMAC TEST MAIN ****************************/
void main(){
struct GMAC_ETH_CONFIG *eth;
struct GMAC_HANDLE *pGMAC;
int32_t bus, num = 0, i;
HAL_DBG("\n");
HAL_DBG("%s\n", __func__);
HAL_DBG(" GMAC Test:\n");
num = sizeof(ethConfigTable) / sizeof(struct GMAC_ETH_CONFIG);
HAL_DBG(" GMAC Num: %ld\n", num);
for (bus = 0; bus < num; bus++) {
eth = &ethConfigTable[bus];
if (eth) {
pGMAC = &eth->instance;
} else {
return;
}
/* ionmux */
GMAC_Iomux_Config(bus);
HAL_CRU_ClkEnable(eth->halDev->pclkGateID);
HAL_CRU_ClkEnable(eth->halDev->clkGateID);
/* Register irq */
/* PHY reset */
GMAC_PHY_Reset(eth);
/* GMAC Init */
GMAC_Init(bus);
GMAC_Memory_Init(eth, pGMAC);
/* Enable GMAC and DMA transmission and reception */
HAL_GMAC_Start(pGMAC, eth->macAddr);
/* Update links information */
PHY_Update_Links(eth, pGMAC, bus);
/* Dump MAC Regs */
Dump_Regs(pGMAC);
/* Dump PHY Regs */
PHY_Dump(eth, pGMAC);
for (i = 0; i < GMAC_TEST_TIMES; i++) {
/* GMAC Send 64 bytes */
GMAC_Send_Test(eth, pGMAC, 64);
/* GMAC Send 1500 bytes */
GMAC_Send_Test(eth, pGMAC, 1500);
HAL_DelayMs(1000);
/* GMAC Recv */
GMAC_Recv_Test(pGMAC);
}
HAL_CRU_ClkDisable(eth->halDev->pclkGateID);
HAL_CRU_ClkDisable(eth->halDev->clkGateID);
free_align(eth->txBuff);
free_align(eth->rxBuff);
}
}