Support imx6q-sabrelite userland timer driver.
This commit is contained in:
TXuian
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/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CCM_PLL_H_
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#define _CCM_PLL_H_
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#include "sdk_types.h"
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//! @addtogroup diag_clocks
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//! @{
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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#define CLK_SRC_32K 32768
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//! @brief Create a clock gate bit mask value.
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//! @param x 0..15, for CG0 to CG15
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#define CG(x) (3 << (x*2))
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//! @brief Constants for CCM CCGR register fields.
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enum _clock_gate_constants
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{
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CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
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CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
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CLOCK_OFF = 0x0 //!< Clocked gated off.
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};
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//! @brief Low power mdoes.
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typedef enum _lp_modes {
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RUN_MODE,
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WAIT_MODE,
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STOP_MODE,
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} lp_modes_t;
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//! @brief Main clock sources.
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typedef enum _main_clocks {
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CPU_CLK,
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AXI_CLK,
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MMDC_CH0_AXI_CLK,
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AHB_CLK,
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IPG_CLK,
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IPG_PER_CLK,
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MMDC_CH1_AXI_CLK,
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} main_clocks_t;
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//! @brief Peripheral clocks.
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typedef enum _peri_clocks {
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UART1_MODULE_CLK,
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UART2_MODULE_CLK,
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UART3_MODULE_CLK,
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UART4_MODULE_CLK,
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SSI1_BAUD,
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SSI2_BAUD,
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CSI_BAUD,
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MSTICK1_CLK,
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MSTICK2_CLK,
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RAWNAND_CLK,
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USB_CLK,
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VPU_CLK,
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SPI_CLK,
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CAN_CLK
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} peri_clocks_t;
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//! @brief Available PLLs.
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typedef enum plls {
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PLL1,
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PLL2,
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PLL3,
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PLL4,
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PLL5,
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} plls_t;
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extern const uint32_t PLL1_OUTPUT;
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extern const uint32_t PLL2_OUTPUT[];
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extern const uint32_t PLL3_OUTPUT[];
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extern const uint32_t PLL4_OUTPUT;
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extern const uint32_t PLL5_OUTPUT;
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////////////////////////////////////////////////////////////////////////////////
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// API
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////////////////////////////////////////////////////////////////////////////////
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#if defined(__cplusplus)
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extern "C" {
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#endif
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//! @brief Set/unset clock gating for a peripheral.
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//! @param base_address configure clock gating for that module from the base address.
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//! @param gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF.
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void clock_gating_config(uint32_t base_address, uint32_t gating_mode);
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//! @brief Returns the frequency of a clock in megahertz.
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uint32_t get_main_clock(main_clocks_t clk);
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//! @brief Returns the frequency of a clock in megahertz.
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uint32_t get_peri_clock(peri_clocks_t clk);
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//! @brief Inits clock sources.
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void ccm_init(void);
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//! @brief Prepare and enter in a low power mode.
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//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE.
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void ccm_enter_low_power(lp_modes_t lp_mode);
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//! @brief Mask/unmask an interrupt source that can wake up the processor when in a
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//! low power mode.
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//!
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//! @param irq_id ID of the interrupt to mask/unmask.
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//! @param doEnable Pass true to unmask the source ID.
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void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable);
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#if defined(__cplusplus)
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}
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#endif
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//! @}
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#endif
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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@@ -0,0 +1,200 @@
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/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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||||
*
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||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/*!
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* @file gpio.h
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* @brief Defines related to the GPIO controller and used by gpio.c
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* @ingroup diag_gpio
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*/
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#include <stddef.h>
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#include <stdint.h>
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//! @addtogroup diag_gpio
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//! @{
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @brief Available GPIO ports.
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typedef enum {
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GPIO_NONE = 0,
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GPIO_PORT1 = 1,
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GPIO_PORT2 = 2,
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GPIO_PORT3 = 3,
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GPIO_PORT4 = 4,
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GPIO_PORT5 = 5,
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GPIO_PORT6 = 6,
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GPIO_PORT7 = 7,
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} GPIO_PORT;
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//! @name GPIO bitfield values
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//@{
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#define GPIO_GDIR_INPUT 0 //!< GPIO pin is input
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#define GPIO_GDIR_OUTPUT 1 //!< GPIO pin is output
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#define GPIO_LOW_LEVEL 0 //!< GPIO pin is low
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#define GPIO_HIGH_LEVEL 1 //!< GPIO pin is high
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#define GPIO_ICR_LOW_LEVEL 0 //!< Interrupt is low-level
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#define GPIO_ICR_HIGH_LEVEL 1 //!< Interrupt is high-level
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#define GPIO_ICR_RISE_EDGE 2 //!< Interrupt is rising edge
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#define GPIO_ICR_FALL_EDGE 3 //!< Interrupt is falling edge
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#define GPIO_IMR_MASKED 0 //!< Interrupt is masked
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#define GPIO_IMR_UNMASKED 1 //!< Interrupt is unmasked
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#define GPIO_ISR_NOT_ASSERTED 0 //!< Interrupt is not asserted
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#define GPIO_ISR_ASSERTED 1 //!< Interrupt is asserted
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#define GPIO_EDGE_SEL_DISABLE 0 //!< Edge select is disabled
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#define GPIO_EDGE_SEL_ENABLE 1 //!< Edge select is enabled
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//@}
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////////////////////////////////////////////////////////////////////////////////
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// API
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////////////////////////////////////////////////////////////////////////////////
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Returns the number of available GPIO instances.
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* @return An integer number of GPIO instances on this hardware.
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*/
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int32_t gpio_get_port_count(void);
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/*!
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* @brief Sets a GPIO pin to GPIO mode in the IOMUX controller.
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*
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* @retval SUCCESS
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* @retval INVALID_PARAMETER
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*/
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int gpio_set_gpio(int32_t port, int32_t pin);
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/*!
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* @brief Sets the GPIO direction for the specified pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @param dir Direction for the pin. GPIO_GDIR_INPUT(0) or GPIO_GDIR_OUTPUT(1).
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* @return INVALID_PARAMETER(-1)
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*/
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int32_t gpio_set_direction(int32_t port, int32_t pin, int32_t dir);
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/*!
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* @brief Returns the current direction for the specified pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @retval GPIO_GDIR_INPUT The pin is currently set as an input.
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* @retval GPIO_GDIR_OUTPUT The pin is currently set as an output.
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*/
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int32_t gpio_get_direction(int32_t port, int32_t pin);
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/*!
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* @brief Sets the GPIO level(high or low) for the specified pin.
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*
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* @warning Fails if pin is not configured as an output.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @param level GPIO_LOW_LEVEL(0), GPIO_HIGH_LEVEL(1)
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* @return INVALID_PARAMETER(-1)
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*/
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int32_t gpio_set_level(int32_t port, int32_t pin, uint32_t level);
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/*!
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* Gets the GPIO level(high or low) for the specified pin.
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*
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* @note Returns level for both input and output configured pins.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @retval INVALID_PARAMETER(-1),
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* @retval GPIO_LOW_LEVEL(0),
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* @retval GPIO_HIGH_LEVEL(1)
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*/
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int32_t gpio_get_level(int32_t port, int32_t pin);
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/*!
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* @brief Configures the interrupt condition for the specified GPIO input pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @param config Interrupt condition for the pin. GPIO_ICR_LOW_LEVEL(0), GPIO_ICR_HIGH_LEVEL(1),
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* GPIO_ICR_RISE_EDGE(2), GPIO_ICR_FALL_EDGE(3)
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* @return INVALID_PARAMETER(-1)
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*/
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int32_t gpio_set_interrupt_config(int32_t port, int32_t pin, int32_t config);
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/*!
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* @brief Enables/Disables the interrupt for the specified GPIO input pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @param mask interrupt mask for the pin. GPIO_IMR_MASKED(0), GPIO_IMR_UNMASKED(1)
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* @return INVALID_PARAMETER(-1)
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*/
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int32_t gpio_set_interrupt_mask(int32_t port, int32_t pin, int32_t mask);
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|
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/*!
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* @brief Gets the GPIO interrupt status for the specified pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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* @param pin GPIO pin 0 to 31.
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* @return INVALID_PARAMETER(-1), GPIO_ISR_NOT_ASSERTED(0), GPIO_ISR_ASSERTED(1)
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*/
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int32_t gpio_get_interrupt_status(int32_t port, int32_t pin);
|
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|
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/*!
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* @brief Clears the GPIO interrupt for the specified pin.
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*
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* @param port GPIO module instance, GPIO_PORT1, GPIO_PORT2, ... gpio_get_port_count().
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||||
* @param pin GPIO pin 0 to 31.
|
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* @return INVALID_PARAMETER(-1)
|
||||
*/
|
||||
int32_t gpio_clear_interrupt(int32_t port, int32_t pin);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
//! @}
|
||||
|
||||
#endif //__GPIO_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file gpio_map.h
|
||||
* @brief
|
||||
* @ingroup diag_gpio
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_MAP_H__
|
||||
#define __GPIO_MAP_H__
|
||||
|
||||
#include "regsgpio.h"
|
||||
#include <stdint.h>
|
||||
|
||||
//! @addtogroup diag_gpio
|
||||
//! @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Number of pins per GPIO bank.
|
||||
#define GPIO_PIN_COUNT (32)
|
||||
|
||||
//! @brief Table to map GPIO pins to their mux control register addresses.
|
||||
//!
|
||||
//! First subscript is bank, second is pin within the bank. There are always 32 pin
|
||||
//! entries per bank. If a pin does not have an assigned GPIO, its address is 0.
|
||||
//!
|
||||
//! Example code to set GPIO 3,12 to GPIO mode:
|
||||
//! @code
|
||||
//! uint32_t addr = k_gpio_mux_registers[3][12];
|
||||
//! volatile uint32_t * reg = (volatile uint32_t *)addr;
|
||||
//! *reg = (*reg & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE)
|
||||
//! | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(ALT5);
|
||||
//! @endcode
|
||||
//!
|
||||
//! The code above uses the bit field macros from an arbitrary mux register definition.
|
||||
extern const uint32_t k_gpio_mux_registers[HW_GPIO_INSTANCE_COUNT][GPIO_PIN_COUNT];
|
||||
|
||||
//! @}
|
||||
|
||||
#endif //__GPIO_MAP_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
// File: iomux_config.h
|
||||
|
||||
/* ------------------------------------------------------------------------------
|
||||
* <auto-generated>
|
||||
* This code was generated by a tool.
|
||||
* Runtime Version:3.4.0.3
|
||||
*
|
||||
* Changes to this file may cause incorrect behavior and will be lost if
|
||||
* the code is regenerated.
|
||||
* </auto-generated>
|
||||
* ------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef _IOMUX_CONFIG_H_
|
||||
#define _IOMUX_CONFIG_H_
|
||||
|
||||
// Board and Module IOMUXC configuration function prototypes.
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Board IOMUXC configuration function.
|
||||
void iomux_config(void);
|
||||
|
||||
// Module IOMUXC configuration functions.
|
||||
void arm_iomux_config(void);
|
||||
void asrc_iomux_config(void);
|
||||
void audmux_iomux_config(void);
|
||||
void ccm_iomux_config(void);
|
||||
void dcic_iomux_config(int instance);
|
||||
void dcic1_iomux_config(void);
|
||||
void dcic2_iomux_config(void);
|
||||
void ecspi_iomux_config(int instance);
|
||||
void ecspi1_iomux_config(void);
|
||||
void ecspi2_iomux_config(void);
|
||||
void ecspi3_iomux_config(void);
|
||||
void ecspi4_iomux_config(void);
|
||||
void ecspi5_iomux_config(void);
|
||||
void eim_iomux_config(void);
|
||||
void enet_iomux_config(void);
|
||||
void enet_iomux_reconfig(void);
|
||||
void epit_iomux_config(int instance);
|
||||
void epit1_iomux_config(void);
|
||||
void epit2_iomux_config(void);
|
||||
void esai_iomux_config(void);
|
||||
void flexcan_iomux_config(int instance);
|
||||
void flexcan1_iomux_config(void);
|
||||
void flexcan2_iomux_config(void);
|
||||
void gpio_iomux_config(int instance);
|
||||
void gpio1_iomux_config(void);
|
||||
void gpio2_iomux_config(void);
|
||||
void gpio3_iomux_config(void);
|
||||
void gpio4_iomux_config(void);
|
||||
void gpio5_iomux_config(void);
|
||||
void gpio6_iomux_config(void);
|
||||
void gpio7_iomux_config(void);
|
||||
void gpmi_iomux_config(void);
|
||||
void gpt_iomux_config(void);
|
||||
void hdmi_iomux_config(void);
|
||||
void i2c_iomux_config(int instance);
|
||||
void i2c1_iomux_config(void);
|
||||
void i2c2_iomux_config(void);
|
||||
void i2c3_iomux_config(void);
|
||||
void ipu_iomux_config(int instance);
|
||||
void ipu1_iomux_config(void);
|
||||
void ipu2_iomux_config(void);
|
||||
void kpp_iomux_config(void);
|
||||
void ldb_iomux_config(void);
|
||||
void mipi_csi_iomux_config(void);
|
||||
void mipi_dsi_iomux_config(void);
|
||||
void mipi_hsi_iomux_config(void);
|
||||
void mlb_iomux_config(void);
|
||||
void mmdc_iomux_config(void);
|
||||
void pcie_iomux_config(void);
|
||||
void pmu_iomux_config(void);
|
||||
void pwm_iomux_config(int instance);
|
||||
void pwm1_iomux_config(void);
|
||||
void pwm2_iomux_config(void);
|
||||
void pwm3_iomux_config(void);
|
||||
void pwm4_iomux_config(void);
|
||||
void sata_phy_iomux_config(void);
|
||||
void sdma_iomux_config(void);
|
||||
void sjc_iomux_config(void);
|
||||
void snvs_iomux_config(void);
|
||||
void spdif_iomux_config(void);
|
||||
void src_iomux_config(void);
|
||||
void uart_iomux_config(int instance);
|
||||
void uart1_iomux_config(void);
|
||||
void uart2_iomux_config(void);
|
||||
void uart3_iomux_config(void);
|
||||
void uart4_iomux_config(void);
|
||||
void uart5_iomux_config(void);
|
||||
void usb_iomux_config(void);
|
||||
void usdhc_iomux_config(int instance);
|
||||
void usdhc1_iomux_config(void);
|
||||
void usdhc2_iomux_config(void);
|
||||
void usdhc3_iomux_config(void);
|
||||
void usdhc4_iomux_config(void);
|
||||
void wdog_iomux_config(int instance);
|
||||
void wdog1_iomux_config(void);
|
||||
void wdog2_iomux_config(void);
|
||||
void xtalosc_iomux_config(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _IOMUX_CONFIG_H_
|
||||
@@ -0,0 +1,479 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _REGS_H
|
||||
#define _REGS_H 1
|
||||
|
||||
//
|
||||
// define base address of the register block only if it is not already
|
||||
// defined, which allows the compiler to override at build time for
|
||||
// users who've mapped their registers to locations other than the
|
||||
// physical location
|
||||
//
|
||||
|
||||
#ifndef REGS_BASE
|
||||
#define REGS_BASE 0x00000000
|
||||
#endif
|
||||
|
||||
//
|
||||
// common register types
|
||||
//
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
typedef unsigned char reg8_t;
|
||||
typedef unsigned short reg16_t;
|
||||
typedef unsigned int reg32_t;
|
||||
#endif
|
||||
|
||||
//
|
||||
// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
|
||||
// used to simplify macro definitions in the module register headers.
|
||||
//
|
||||
#ifndef __REG_VALUE_TYPE
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define __REG_VALUE_TYPE(v, t) ((t)(v))
|
||||
#else
|
||||
#define __REG_VALUE_TYPE(v, t) (v)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//
|
||||
// macros for single instance registers
|
||||
//
|
||||
|
||||
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
|
||||
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
|
||||
#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
|
||||
|
||||
#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
|
||||
#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
|
||||
#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
|
||||
|
||||
#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BF_RD(reg, field) HW_##reg.B.field
|
||||
#define BF_WR(reg, field, v) BW_##reg##_##field(v)
|
||||
|
||||
#define BF_CS1(reg, f1, v1) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1)))
|
||||
|
||||
#define BF_CS2(reg, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2)))
|
||||
|
||||
#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3)))
|
||||
|
||||
#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4)))
|
||||
|
||||
#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5)))
|
||||
|
||||
#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6)))
|
||||
|
||||
#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7)))
|
||||
|
||||
#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8)))
|
||||
|
||||
//
|
||||
// macros for multiple instance registers
|
||||
//
|
||||
|
||||
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
|
||||
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
|
||||
#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
|
||||
|
||||
#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
|
||||
#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
|
||||
#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
|
||||
|
||||
#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BF_RDn(reg, n, field) HW_##reg(n).B.field
|
||||
#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
|
||||
|
||||
#define BF_CS1n(reg, n, f1, v1) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
|
||||
|
||||
#define BF_CS2n(reg, n, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2))))
|
||||
|
||||
#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3))))
|
||||
|
||||
#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4))))
|
||||
|
||||
#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5))))
|
||||
|
||||
#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6))))
|
||||
|
||||
#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7))))
|
||||
|
||||
#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8))))
|
||||
|
||||
//
|
||||
// macros for single instance MULTI-BLOCK registers
|
||||
//
|
||||
|
||||
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
|
||||
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
|
||||
#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
|
||||
|
||||
#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
|
||||
#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
|
||||
#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
|
||||
|
||||
#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
|
||||
#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
|
||||
|
||||
#define BFn_CS1(reg, blk, f1, v1) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
|
||||
|
||||
#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2)))
|
||||
|
||||
#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3)))
|
||||
|
||||
#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4)))
|
||||
|
||||
#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5)))
|
||||
|
||||
#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6)))
|
||||
|
||||
#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7)))
|
||||
|
||||
#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8)))
|
||||
|
||||
//
|
||||
// macros for MULTI-BLOCK multiple instance registers
|
||||
//
|
||||
|
||||
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
|
||||
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
|
||||
#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
|
||||
|
||||
#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
|
||||
#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
|
||||
#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
|
||||
|
||||
#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
|
||||
#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
|
||||
|
||||
#define BFn_CS1n(reg, blk, n, f1, v1) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
|
||||
|
||||
#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2))))
|
||||
|
||||
#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3))))
|
||||
|
||||
#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4))))
|
||||
|
||||
#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5))))
|
||||
|
||||
#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6))))
|
||||
|
||||
#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7))))
|
||||
|
||||
#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8))))
|
||||
|
||||
#endif // _REGS_H
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,741 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
/*************************************************
|
||||
File name: regsgpc.h
|
||||
Description:
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-11-23
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. Comment unnecessary macros
|
||||
*************************************************/
|
||||
#ifndef __HW_GPC_REGISTERS_H__
|
||||
#define __HW_GPC_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
#include "soc_memory_map.h"
|
||||
|
||||
/*
|
||||
* i.MX6DQ GPC
|
||||
*
|
||||
* GPC
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_GPC_CNTR - GPC Interface control register
|
||||
* - HW_GPC_PGR - GPC Power Gating Register
|
||||
* - HW_GPC_IMR1 - IRQ masking register 1
|
||||
* - HW_GPC_IMR2 - IRQ masking register 2
|
||||
* - HW_GPC_IMR3 - IRQ masking register 3
|
||||
* - HW_GPC_IMR4 - IRQ masking register 4
|
||||
* - HW_GPC_ISR1 - IRQ status resister 1
|
||||
* - HW_GPC_ISR2 - IRQ status resister 2
|
||||
* - HW_GPC_ISR3 - IRQ status resister 3
|
||||
* - HW_GPC_ISR4 - IRQ status resister 4
|
||||
*
|
||||
* - hw_gpc_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_GPC_BASE
|
||||
#define HW_GPC_INSTANCE_COUNT (1) //!< Number of instances of the GPC module.
|
||||
#define REGS_GPC_BASE USERLAND_MMIO_P2V(0x020dc000) //!< Base address for GPC.
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_GPC_CNTR - GPC Interface control register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_CNTR - GPC Interface control register (RW)
|
||||
// *
|
||||
// * Reset value: 0x00100000
|
||||
// */
|
||||
// typedef union _hw_gpc_cntr
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_cntr_bitfields
|
||||
// {
|
||||
// unsigned GPU_VPU_PDN_REQ : 1; //!< [0] GPU /VPU Power Down request.
|
||||
// unsigned GPU_VPU_PUP_REQ : 1; //!< [1] GPU /VPU Power Up request.
|
||||
// unsigned RESERVED2 : 14; //!< [15:2] Reserved.
|
||||
// unsigned DVFS0CR : 1; //!< [16] DVFS0 (ARM) Change request (bit is read-only)
|
||||
// unsigned RESERVED3 : 4; //!< [20:17] Reserved.
|
||||
// unsigned GPCIRQM : 1; //!< [21] GPC interrupt/event masking
|
||||
// unsigned RESERVED4 : 10; //!< [31:22] Reserved.
|
||||
// } B;
|
||||
// } hw_gpc_cntr_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_CNTR register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_CNTR_ADDR (REGS_GPC_BASE + 0x0)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_CNTR (*(volatile hw_gpc_cntr_t *) HW_GPC_CNTR_ADDR)
|
||||
// #define HW_GPC_CNTR_RD() (HW_GPC_CNTR.U)
|
||||
// #define HW_GPC_CNTR_WR(v) (HW_GPC_CNTR.U = (v))
|
||||
// #define HW_GPC_CNTR_SET(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() | (v)))
|
||||
// #define HW_GPC_CNTR_CLR(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() & ~(v)))
|
||||
// #define HW_GPC_CNTR_TOG(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() ^ (v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_CNTR bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_CNTR, field GPU_VPU_PDN_REQ[0] (RW)
|
||||
// *
|
||||
// * GPU /VPU Power Down request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
|
||||
// * controlled by ANALOG configuration, not GPU /VPU PGC signals
|
||||
// *
|
||||
// * Values:
|
||||
// * - 0 - no request
|
||||
// * - 1 - Request Power Down sequence to start for GPU /VPU
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_CNTR_GPU_VPU_PDN_REQ (0) //!< Bit position for GPC_CNTR_GPU_VPU_PDN_REQ.
|
||||
// #define BM_GPC_CNTR_GPU_VPU_PDN_REQ (0x00000001) //!< Bit mask for GPC_CNTR_GPU_VPU_PDN_REQ.
|
||||
|
||||
// //! @brief Get value of GPC_CNTR_GPU_VPU_PDN_REQ from a register value.
|
||||
// #define BG_GPC_CNTR_GPU_VPU_PDN_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PDN_REQ) >> BP_GPC_CNTR_GPU_VPU_PDN_REQ)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PDN_REQ.
|
||||
// #define BF_GPC_CNTR_GPU_VPU_PDN_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PDN_REQ) & BM_GPC_CNTR_GPU_VPU_PDN_REQ)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the GPU_VPU_PDN_REQ field to a new value.
|
||||
// #define BW_GPC_CNTR_GPU_VPU_PDN_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PDN_REQ) | BF_GPC_CNTR_GPU_VPU_PDN_REQ(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*! @name Register GPC_CNTR, field GPU_VPU_PUP_REQ[1] (RW)
|
||||
// *
|
||||
// * GPU /VPU Power Up request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
|
||||
// * controlled by ANALOG configuration, not GPU /VPU PGC signals
|
||||
// *
|
||||
// * Values:
|
||||
// * - 0 - no request
|
||||
// * - 1 - Request Power Up sequence to start for GPU /VPU
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_CNTR_GPU_VPU_PUP_REQ (1) //!< Bit position for GPC_CNTR_GPU_VPU_PUP_REQ.
|
||||
// #define BM_GPC_CNTR_GPU_VPU_PUP_REQ (0x00000002) //!< Bit mask for GPC_CNTR_GPU_VPU_PUP_REQ.
|
||||
|
||||
// //! @brief Get value of GPC_CNTR_GPU_VPU_PUP_REQ from a register value.
|
||||
// #define BG_GPC_CNTR_GPU_VPU_PUP_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PUP_REQ) >> BP_GPC_CNTR_GPU_VPU_PUP_REQ)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PUP_REQ.
|
||||
// #define BF_GPC_CNTR_GPU_VPU_PUP_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PUP_REQ) & BM_GPC_CNTR_GPU_VPU_PUP_REQ)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the GPU_VPU_PUP_REQ field to a new value.
|
||||
// #define BW_GPC_CNTR_GPU_VPU_PUP_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PUP_REQ) | BF_GPC_CNTR_GPU_VPU_PUP_REQ(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*! @name Register GPC_CNTR, field DVFS0CR[16] (RO)
|
||||
// *
|
||||
// * DVFS0 (ARM) Change request (bit is read-only)
|
||||
// *
|
||||
// * Values:
|
||||
// * - 0 - DVFS0 has no request
|
||||
// * - 1 - DVFS0 is requesting for frequency/voltage update
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_CNTR_DVFS0CR (16) //!< Bit position for GPC_CNTR_DVFS0CR.
|
||||
// #define BM_GPC_CNTR_DVFS0CR (0x00010000) //!< Bit mask for GPC_CNTR_DVFS0CR.
|
||||
|
||||
// //! @brief Get value of GPC_CNTR_DVFS0CR from a register value.
|
||||
// #define BG_GPC_CNTR_DVFS0CR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_DVFS0CR) >> BP_GPC_CNTR_DVFS0CR)
|
||||
// //@}
|
||||
|
||||
// /*! @name Register GPC_CNTR, field GPCIRQM[21] (RW)
|
||||
// *
|
||||
// * GPC interrupt/event masking
|
||||
// *
|
||||
// * Values:
|
||||
// * - 0 - not masked
|
||||
// * - 1 - interrupt/event is masked
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_CNTR_GPCIRQM (21) //!< Bit position for GPC_CNTR_GPCIRQM.
|
||||
// #define BM_GPC_CNTR_GPCIRQM (0x00200000) //!< Bit mask for GPC_CNTR_GPCIRQM.
|
||||
|
||||
// //! @brief Get value of GPC_CNTR_GPCIRQM from a register value.
|
||||
// #define BG_GPC_CNTR_GPCIRQM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPCIRQM) >> BP_GPC_CNTR_GPCIRQM)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_CNTR_GPCIRQM.
|
||||
// #define BF_GPC_CNTR_GPCIRQM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPCIRQM) & BM_GPC_CNTR_GPCIRQM)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the GPCIRQM field to a new value.
|
||||
// #define BW_GPC_CNTR_GPCIRQM(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPCIRQM) | BF_GPC_CNTR_GPCIRQM(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_PGR - GPC Power Gating Register
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_PGR - GPC Power Gating Register (RW)
|
||||
// *
|
||||
// * Reset value: 0x00000000
|
||||
// */
|
||||
// typedef union _hw_gpc_pgr
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_pgr_bitfields
|
||||
// {
|
||||
// unsigned RESERVED0 : 29; //!< [28:0] Reserved
|
||||
// unsigned DRCIC : 2; //!< [30:29] Debug ref cir in mux control
|
||||
// unsigned RESERVED1 : 1; //!< [31] Reserved
|
||||
// } B;
|
||||
// } hw_gpc_pgr_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_PGR register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_PGR_ADDR (REGS_GPC_BASE + 0x4)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_PGR (*(volatile hw_gpc_pgr_t *) HW_GPC_PGR_ADDR)
|
||||
// #define HW_GPC_PGR_RD() (HW_GPC_PGR.U)
|
||||
// #define HW_GPC_PGR_WR(v) (HW_GPC_PGR.U = (v))
|
||||
// #define HW_GPC_PGR_SET(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() | (v)))
|
||||
// #define HW_GPC_PGR_CLR(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() & ~(v)))
|
||||
// #define HW_GPC_PGR_TOG(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() ^ (v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_PGR bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_PGR, field DRCIC[30:29] (RW)
|
||||
// *
|
||||
// * Debug ref cir in mux control
|
||||
// *
|
||||
// * Values:
|
||||
// * - 00 - ccm_cosr_1_clk_in
|
||||
// * - 01 - ccm_cosr_2_clk_in
|
||||
// * - 10 - restricted
|
||||
// * - 11 - restricted
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_PGR_DRCIC (29) //!< Bit position for GPC_PGR_DRCIC.
|
||||
// #define BM_GPC_PGR_DRCIC (0x60000000) //!< Bit mask for GPC_PGR_DRCIC.
|
||||
|
||||
// //! @brief Get value of GPC_PGR_DRCIC from a register value.
|
||||
// #define BG_GPC_PGR_DRCIC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_PGR_DRCIC) >> BP_GPC_PGR_DRCIC)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_PGR_DRCIC.
|
||||
// #define BF_GPC_PGR_DRCIC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_PGR_DRCIC) & BM_GPC_PGR_DRCIC)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the DRCIC field to a new value.
|
||||
// #define BW_GPC_PGR_DRCIC(v) (HW_GPC_PGR_WR((HW_GPC_PGR_RD() & ~BM_GPC_PGR_DRCIC) | BF_GPC_PGR_DRCIC(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_IMR1 - IRQ masking register 1
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_GPC_IMR1 - IRQ masking register 1 (RW)
|
||||
*
|
||||
* Reset value: 0x00000000
|
||||
*
|
||||
* IMR1 Register - masking of irq[63:32].
|
||||
*/
|
||||
typedef union _hw_gpc_imr1 {
|
||||
reg32_t U;
|
||||
struct _hw_gpc_imr1_bitfields {
|
||||
unsigned IMR1 : 32; //!< [31:0] IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
|
||||
} B;
|
||||
} hw_gpc_imr1_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPC_IMR1 register
|
||||
*/
|
||||
//@{
|
||||
#define HW_GPC_IMR1_ADDR (REGS_GPC_BASE + 0x8)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_GPC_IMR1 (*(volatile hw_gpc_imr1_t*)HW_GPC_IMR1_ADDR)
|
||||
#define HW_GPC_IMR1_RD() (HW_GPC_IMR1.U)
|
||||
#define HW_GPC_IMR1_WR(v) (HW_GPC_IMR1.U = (v))
|
||||
#define HW_GPC_IMR1_SET(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() | (v)))
|
||||
#define HW_GPC_IMR1_CLR(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() & ~(v)))
|
||||
#define HW_GPC_IMR1_TOG(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_IMR1 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_IMR1, field IMR1[31:0] (RW)
|
||||
// *
|
||||
// * IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_IMR1_IMR1 (0) //!< Bit position for GPC_IMR1_IMR1.
|
||||
// #define BM_GPC_IMR1_IMR1 (0xffffffff) //!< Bit mask for GPC_IMR1_IMR1.
|
||||
|
||||
// //! @brief Get value of GPC_IMR1_IMR1 from a register value.
|
||||
// #define BG_GPC_IMR1_IMR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR1_IMR1) >> BP_GPC_IMR1_IMR1)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_IMR1_IMR1.
|
||||
// #define BF_GPC_IMR1_IMR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR1_IMR1) & BM_GPC_IMR1_IMR1)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the IMR1 field to a new value.
|
||||
// #define BW_GPC_IMR1_IMR1(v) (HW_GPC_IMR1_WR((HW_GPC_IMR1_RD() & ~BM_GPC_IMR1_IMR1) | BF_GPC_IMR1_IMR1(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_IMR2 - IRQ masking register 2
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_GPC_IMR2 - IRQ masking register 2 (RW)
|
||||
*
|
||||
* Reset value: 0x00000000
|
||||
*
|
||||
* IMR2 Register - masking of irq[95:64].
|
||||
*/
|
||||
typedef union _hw_gpc_imr2 {
|
||||
reg32_t U;
|
||||
struct _hw_gpc_imr2_bitfields {
|
||||
unsigned IMR2 : 32; //!< [31:0] IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
|
||||
} B;
|
||||
} hw_gpc_imr2_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPC_IMR2 register
|
||||
*/
|
||||
//@{
|
||||
#define HW_GPC_IMR2_ADDR (REGS_GPC_BASE + 0xc)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_GPC_IMR2 (*(volatile hw_gpc_imr2_t*)HW_GPC_IMR2_ADDR)
|
||||
#define HW_GPC_IMR2_RD() (HW_GPC_IMR2.U)
|
||||
#define HW_GPC_IMR2_WR(v) (HW_GPC_IMR2.U = (v))
|
||||
#define HW_GPC_IMR2_SET(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() | (v)))
|
||||
#define HW_GPC_IMR2_CLR(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() & ~(v)))
|
||||
#define HW_GPC_IMR2_TOG(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_IMR2 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_IMR2, field IMR2[31:0] (RW)
|
||||
// *
|
||||
// * IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_IMR2_IMR2 (0) //!< Bit position for GPC_IMR2_IMR2.
|
||||
// #define BM_GPC_IMR2_IMR2 (0xffffffff) //!< Bit mask for GPC_IMR2_IMR2.
|
||||
|
||||
// //! @brief Get value of GPC_IMR2_IMR2 from a register value.
|
||||
// #define BG_GPC_IMR2_IMR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR2_IMR2) >> BP_GPC_IMR2_IMR2)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_IMR2_IMR2.
|
||||
// #define BF_GPC_IMR2_IMR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR2_IMR2) & BM_GPC_IMR2_IMR2)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the IMR2 field to a new value.
|
||||
// #define BW_GPC_IMR2_IMR2(v) (HW_GPC_IMR2_WR((HW_GPC_IMR2_RD() & ~BM_GPC_IMR2_IMR2) | BF_GPC_IMR2_IMR2(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_IMR3 - IRQ masking register 3
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_GPC_IMR3 - IRQ masking register 3 (RW)
|
||||
*
|
||||
* Reset value: 0x00000000
|
||||
*
|
||||
* IMR3 Register - masking of irq[127:96].
|
||||
*/
|
||||
typedef union _hw_gpc_imr3 {
|
||||
reg32_t U;
|
||||
struct _hw_gpc_imr3_bitfields {
|
||||
unsigned IMR3 : 32; //!< [31:0] IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
|
||||
} B;
|
||||
} hw_gpc_imr3_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPC_IMR3 register
|
||||
*/
|
||||
//@{
|
||||
#define HW_GPC_IMR3_ADDR (REGS_GPC_BASE + 0x10)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_GPC_IMR3 (*(volatile hw_gpc_imr3_t*)HW_GPC_IMR3_ADDR)
|
||||
#define HW_GPC_IMR3_RD() (HW_GPC_IMR3.U)
|
||||
#define HW_GPC_IMR3_WR(v) (HW_GPC_IMR3.U = (v))
|
||||
#define HW_GPC_IMR3_SET(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() | (v)))
|
||||
#define HW_GPC_IMR3_CLR(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() & ~(v)))
|
||||
#define HW_GPC_IMR3_TOG(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_IMR3 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_IMR3, field IMR3[31:0] (RW)
|
||||
// *
|
||||
// * IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_IMR3_IMR3 (0) //!< Bit position for GPC_IMR3_IMR3.
|
||||
// #define BM_GPC_IMR3_IMR3 (0xffffffff) //!< Bit mask for GPC_IMR3_IMR3.
|
||||
|
||||
// //! @brief Get value of GPC_IMR3_IMR3 from a register value.
|
||||
// #define BG_GPC_IMR3_IMR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR3_IMR3) >> BP_GPC_IMR3_IMR3)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_IMR3_IMR3.
|
||||
// #define BF_GPC_IMR3_IMR3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR3_IMR3) & BM_GPC_IMR3_IMR3)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the IMR3 field to a new value.
|
||||
// #define BW_GPC_IMR3_IMR3(v) (HW_GPC_IMR3_WR((HW_GPC_IMR3_RD() & ~BM_GPC_IMR3_IMR3) | BF_GPC_IMR3_IMR3(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_IMR4 - IRQ masking register 4
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_GPC_IMR4 - IRQ masking register 4 (RW)
|
||||
*
|
||||
* Reset value: 0x00000000
|
||||
*
|
||||
* IMR4 Register - masking of irq[159:128].
|
||||
*/
|
||||
typedef union _hw_gpc_imr4 {
|
||||
reg32_t U;
|
||||
struct _hw_gpc_imr4_bitfields {
|
||||
unsigned IMR4 : 32; //!< [31:0] IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
|
||||
} B;
|
||||
} hw_gpc_imr4_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPC_IMR4 register
|
||||
*/
|
||||
//@{
|
||||
#define HW_GPC_IMR4_ADDR (REGS_GPC_BASE + 0x14)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_GPC_IMR4 (*(volatile hw_gpc_imr4_t*)HW_GPC_IMR4_ADDR)
|
||||
#define HW_GPC_IMR4_RD() (HW_GPC_IMR4.U)
|
||||
#define HW_GPC_IMR4_WR(v) (HW_GPC_IMR4.U = (v))
|
||||
#define HW_GPC_IMR4_SET(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() | (v)))
|
||||
#define HW_GPC_IMR4_CLR(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() & ~(v)))
|
||||
#define HW_GPC_IMR4_TOG(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_IMR4 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_IMR4, field IMR4[31:0] (RW)
|
||||
// *
|
||||
// * IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_IMR4_IMR4 (0) //!< Bit position for GPC_IMR4_IMR4.
|
||||
// #define BM_GPC_IMR4_IMR4 (0xffffffff) //!< Bit mask for GPC_IMR4_IMR4.
|
||||
|
||||
// //! @brief Get value of GPC_IMR4_IMR4 from a register value.
|
||||
// #define BG_GPC_IMR4_IMR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR4_IMR4) >> BP_GPC_IMR4_IMR4)
|
||||
|
||||
// //! @brief Format value for bitfield GPC_IMR4_IMR4.
|
||||
// #define BF_GPC_IMR4_IMR4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR4_IMR4) & BM_GPC_IMR4_IMR4)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// //! @brief Set the IMR4 field to a new value.
|
||||
// #define BW_GPC_IMR4_IMR4(v) (HW_GPC_IMR4_WR((HW_GPC_IMR4_RD() & ~BM_GPC_IMR4_IMR4) | BF_GPC_IMR4_IMR4(v)))
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_ISR1 - IRQ status resister 1
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_ISR1 - IRQ status resister 1 (RO)
|
||||
// *
|
||||
// * Reset value: 0x00000000
|
||||
// *
|
||||
// * ISR1 Register - status of irq [63:32].
|
||||
// */
|
||||
// typedef union _hw_gpc_isr1
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_isr1_bitfields
|
||||
// {
|
||||
// unsigned ISR1 : 32; //!< [31:0] IRQ[63:32] status, read only
|
||||
// } B;
|
||||
// } hw_gpc_isr1_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_ISR1 register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_ISR1_ADDR (REGS_GPC_BASE + 0x18)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_ISR1 (*(volatile hw_gpc_isr1_t *) HW_GPC_ISR1_ADDR)
|
||||
// #define HW_GPC_ISR1_RD() (HW_GPC_ISR1.U)
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_ISR1 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_ISR1, field ISR1[31:0] (RO)
|
||||
// *
|
||||
// * IRQ[63:32] status, read only
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_ISR1_ISR1 (0) //!< Bit position for GPC_ISR1_ISR1.
|
||||
// #define BM_GPC_ISR1_ISR1 (0xffffffff) //!< Bit mask for GPC_ISR1_ISR1.
|
||||
|
||||
// //! @brief Get value of GPC_ISR1_ISR1 from a register value.
|
||||
// #define BG_GPC_ISR1_ISR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR1_ISR1) >> BP_GPC_ISR1_ISR1)
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_ISR2 - IRQ status resister 2
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_ISR2 - IRQ status resister 2 (RO)
|
||||
// *
|
||||
// * Reset value: 0x00000000
|
||||
// *
|
||||
// * ISR2 Register - status of irq [95:64].
|
||||
// */
|
||||
// typedef union _hw_gpc_isr2
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_isr2_bitfields
|
||||
// {
|
||||
// unsigned ISR2 : 32; //!< [31:0] IRQ[95:64] status, read only
|
||||
// } B;
|
||||
// } hw_gpc_isr2_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_ISR2 register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_ISR2_ADDR (REGS_GPC_BASE + 0x1c)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_ISR2 (*(volatile hw_gpc_isr2_t *) HW_GPC_ISR2_ADDR)
|
||||
// #define HW_GPC_ISR2_RD() (HW_GPC_ISR2.U)
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_ISR2 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_ISR2, field ISR2[31:0] (RO)
|
||||
// *
|
||||
// * IRQ[95:64] status, read only
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_ISR2_ISR2 (0) //!< Bit position for GPC_ISR2_ISR2.
|
||||
// #define BM_GPC_ISR2_ISR2 (0xffffffff) //!< Bit mask for GPC_ISR2_ISR2.
|
||||
|
||||
// //! @brief Get value of GPC_ISR2_ISR2 from a register value.
|
||||
// #define BG_GPC_ISR2_ISR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR2_ISR2) >> BP_GPC_ISR2_ISR2)
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_ISR3 - IRQ status resister 3
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_ISR3 - IRQ status resister 3 (RO)
|
||||
// *
|
||||
// * Reset value: 0x00000000
|
||||
// *
|
||||
// * ISR3 Register - status of irq [127:96].
|
||||
// */
|
||||
// typedef union _hw_gpc_isr3
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_isr3_bitfields
|
||||
// {
|
||||
// unsigned ISR3 : 32; //!< [31:0] IRQ[127:96] status, read only
|
||||
// } B;
|
||||
// } hw_gpc_isr3_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_ISR3 register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_ISR3_ADDR (REGS_GPC_BASE + 0x20)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_ISR3 (*(volatile hw_gpc_isr3_t *) HW_GPC_ISR3_ADDR)
|
||||
// #define HW_GPC_ISR3_RD() (HW_GPC_ISR3.U)
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_ISR3 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_ISR3, field ISR3[31:0] (RO)
|
||||
// *
|
||||
// * IRQ[127:96] status, read only
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_ISR3_ISR3 (0) //!< Bit position for GPC_ISR3_ISR3.
|
||||
// #define BM_GPC_ISR3_ISR3 (0xffffffff) //!< Bit mask for GPC_ISR3_ISR3.
|
||||
|
||||
// //! @brief Get value of GPC_ISR3_ISR3 from a register value.
|
||||
// #define BG_GPC_ISR3_ISR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR3_ISR3) >> BP_GPC_ISR3_ISR3)
|
||||
// //@}
|
||||
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
// // HW_GPC_ISR4 - IRQ status resister 4
|
||||
// //-------------------------------------------------------------------------------------------
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// /*!
|
||||
// * @brief HW_GPC_ISR4 - IRQ status resister 4 (RO)
|
||||
// *
|
||||
// * Reset value: 0x00000000
|
||||
// *
|
||||
// * ISR4 Register - status of irq [159:128].
|
||||
// */
|
||||
// typedef union _hw_gpc_isr4
|
||||
// {
|
||||
// reg32_t U;
|
||||
// struct _hw_gpc_isr4_bitfields
|
||||
// {
|
||||
// unsigned ISR4 : 32; //!< [31:0] IRQ[159:128] status, read only
|
||||
// } B;
|
||||
// } hw_gpc_isr4_t;
|
||||
// #endif
|
||||
|
||||
// /*!
|
||||
// * @name Constants and macros for entire GPC_ISR4 register
|
||||
// */
|
||||
// //@{
|
||||
// #define HW_GPC_ISR4_ADDR (REGS_GPC_BASE + 0x24)
|
||||
|
||||
// #ifndef __LANGUAGE_ASM__
|
||||
// #define HW_GPC_ISR4 (*(volatile hw_gpc_isr4_t *) HW_GPC_ISR4_ADDR)
|
||||
// #define HW_GPC_ISR4_RD() (HW_GPC_ISR4.U)
|
||||
// #endif
|
||||
// //@}
|
||||
|
||||
// /*
|
||||
// * constants & macros for individual GPC_ISR4 bitfields
|
||||
// */
|
||||
|
||||
// /*! @name Register GPC_ISR4, field ISR4[31:0] (RO)
|
||||
// *
|
||||
// * IRQ[159:128] status, read only
|
||||
// */
|
||||
// //@{
|
||||
// #define BP_GPC_ISR4_ISR4 (0) //!< Bit position for GPC_ISR4_ISR4.
|
||||
// #define BM_GPC_ISR4_ISR4 (0xffffffff) //!< Bit mask for GPC_ISR4_ISR4.
|
||||
|
||||
// //! @brief Get value of GPC_ISR4_ISR4 from a register value.
|
||||
// #define BG_GPC_ISR4_ISR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR4_ISR4) >> BP_GPC_ISR4_ISR4)
|
||||
// //@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_gpc_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All GPC module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
// typedef struct _hw_gpc
|
||||
// {
|
||||
// volatile hw_gpc_cntr_t CNTR; //!< GPC Interface control register
|
||||
// volatile hw_gpc_pgr_t PGR; //!< GPC Power Gating Register
|
||||
// volatile hw_gpc_imr1_t IMR1; //!< IRQ masking register 1
|
||||
// volatile hw_gpc_imr2_t IMR2; //!< IRQ masking register 2
|
||||
// volatile hw_gpc_imr3_t IMR3; //!< IRQ masking register 3
|
||||
// volatile hw_gpc_imr4_t IMR4; //!< IRQ masking register 4
|
||||
// volatile hw_gpc_isr1_t ISR1; //!< IRQ status resister 1
|
||||
// volatile hw_gpc_isr2_t ISR2; //!< IRQ status resister 2
|
||||
// volatile hw_gpc_isr3_t ISR3; //!< IRQ status resister 3
|
||||
// volatile hw_gpc_isr4_t ISR4; //!< IRQ status resister 4
|
||||
// } hw_gpc_t;
|
||||
// #pragma pack()
|
||||
|
||||
// //! @brief Macro to access all GPC registers.
|
||||
// //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
// //! use the '&' operator, like <code>&HW_GPC</code>.
|
||||
// #define HW_GPC (*(hw_gpc_t *) REGS_GPC_BASE)
|
||||
#endif
|
||||
|
||||
#endif // __HW_GPC_REGISTERS_H__
|
||||
// v18/121106/1.2.2
|
||||
// EOF
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef __SDK_TYPES_H__
|
||||
#define __SDK_TYPES_H__
|
||||
|
||||
//! @addtogroup sdk_common
|
||||
//! @{
|
||||
|
||||
/*!
|
||||
* @file sdk_types.h
|
||||
* @brief Basic types used throughout the SDK.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @name Alternate Boolean constants
|
||||
//@{
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
//@}
|
||||
|
||||
//! @brief
|
||||
#define NONE_CHAR (0xFF)
|
||||
|
||||
//! @brief A parameter was out of range or otherwise invalid.
|
||||
#define INVALID_PARAMETER (-1)
|
||||
|
||||
//! @name Min/max macros
|
||||
//@{
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//! @brief Computes the number of elements in an array.
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
//! @brief Debug print utility.
|
||||
//!
|
||||
//! This print function will only output text when the @a DEBUG macro is defined.
|
||||
static inline void debug_printf(const char* format, ...)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
vprintf(format, args);
|
||||
va_end(args);
|
||||
#endif
|
||||
}
|
||||
|
||||
//! @name Test results
|
||||
typedef enum _test_return {
|
||||
TEST_NOT_STARTED = -3, // present in the menu, but not run
|
||||
TEST_NOT_IMPLEMENTED = -2, // present in the menu, but not functional
|
||||
TEST_FAILED = -1,
|
||||
TEST_PASSED = 0,
|
||||
TEST_BYPASSED = 2, // user elected to exit the test before it was run
|
||||
TEST_NOT_PRESENT = 3, // not present in the menu.
|
||||
TEST_CONTINUE = 4 // proceed with the test. opposite of TEST_BYPASSED
|
||||
} test_return_t;
|
||||
|
||||
//! @name Return codes
|
||||
//@{
|
||||
#define SUCCESS (0)
|
||||
#define FAIL (1)
|
||||
#define ERROR_GENERIC (-1)
|
||||
#define ERROR_OUT_OF_MEMORY (-2)
|
||||
//@}
|
||||
|
||||
//! @brief Possible types of displays.
|
||||
enum display_type {
|
||||
DISP_DEV_NULL = 0,
|
||||
DISP_DEV_TFTLCD,
|
||||
DISP_DEV_LVDS,
|
||||
DISP_DEV_VGA,
|
||||
DISP_DEV_HDMI,
|
||||
DISP_DEV_TV,
|
||||
DISP_DEV_MIPI,
|
||||
};
|
||||
|
||||
//! @}
|
||||
|
||||
#endif // __SDK_TYPES_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
+220
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_MEMORY_MAP_H
|
||||
#define _SOC_MEMORY_MAP_H
|
||||
|
||||
// NOTE: THIS FILE IS GOING AWAY.
|
||||
//
|
||||
// DEVELOPERS - PLEASE USE register/*.h MACROS TO ACCESS REGSITERS.
|
||||
//
|
||||
|
||||
// clang-format off
|
||||
#define BOARD_SABRE_LITE
|
||||
#define CHIP_MX6DQ 1
|
||||
|
||||
#define DRIVER_MAPPING_OFFSET 0x50000000
|
||||
#define USERLAND_MMIO_P2V(a) (DRIVER_MAPPING_OFFSET + a)
|
||||
|
||||
#define BAAD_STATUS 0xbaadbaad
|
||||
#define GOOD_STATUS 0x900d900d
|
||||
|
||||
// CPU Memory Map
|
||||
#define MMDC0_ARB_BASE_ADDR 0x80000000
|
||||
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
|
||||
#define MMDC1_ARB_BASE_ADDR 0xC0000000
|
||||
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
|
||||
#define OCRAM_ARB_BASE_ADDR 0x00900000
|
||||
#define OCRAM_ARB_END_ADDR 0x0091FFFF
|
||||
#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
|
||||
|
||||
// Blocks connected via pl301periph
|
||||
// s_e_N ports
|
||||
#define ROMCP_ARB_BASE_ADDR 0x00000000
|
||||
#define ROMCP_ARB_END_ADDR 0x00017FFF
|
||||
#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
|
||||
#define GPU_2D_ARB_BASE_ADDR 0x02200000
|
||||
#define GPU_2D_ARB_END_ADDR 0x02203FFF
|
||||
#define OPENVG_ARB_BASE_ADDR 0x02204000
|
||||
#define OPENVG_ARB_END_ADDR 0x02207FFF
|
||||
// GPV - PL301 configuration ports
|
||||
#define GPV0_BASE_ADDR 0x00B00000
|
||||
#define GPV1_BASE_ADDR 0x00C00000
|
||||
#define GPV2_BASE_ADDR 0x00D00000
|
||||
// s_g_N ports
|
||||
#define AIPS1_ARB_PHY_BASE_ADDR 0x02000000
|
||||
#define AIPS1_ARB_PHY_END_ADDR 0x020FFFFF
|
||||
#define AIPS2_ARB_PHY_BASE_ADDR 0x02100000
|
||||
#define AIPS2_ARB_PHY_END_ADDR 0x021FFFFF
|
||||
|
||||
#define AIPS1_ARB_BASE_ADDR USERLAND_MMIO_P2V(AIPS1_ARB_PHY_BASE_ADDR)
|
||||
#define AIPS1_ARB_END_ADDR USERLAND_MMIO_P2V(AIPS1_ARB_PHY_END_ADDR)
|
||||
#define AIPS2_ARB_BASE_ADDR USERLAND_MMIO_P2V(AIPS2_ARB_PHY_BASE_ADDR)
|
||||
#define AIPS2_ARB_END_ADDR USERLAND_MMIO_P2V(AIPS2_ARB_PHY_END_ADDR)
|
||||
|
||||
// #define SATA_ARB_BASE_ADDR 0x02200000
|
||||
// #define SATA_ARB_END_ADDR 0x02203FFF
|
||||
// #define OPENVG_ARB_BASE_ADDR 0x02204000
|
||||
// #define OPENVG_ARB_END_ADDR 0x02207FFF
|
||||
#define WEIM_ARB_BASE_ADDR 0x08000000
|
||||
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
|
||||
|
||||
// CoreSight (ARM Debug)
|
||||
// ***** TO UPDATE *****
|
||||
#define DEBUG_ROM_BASE_ADDR 0x02140000
|
||||
#define ETB_BASE_ADDR 0x02141000
|
||||
#define EXT_CTI_BASE_ADDR 0x02142000
|
||||
#define TPIU_BASE_ADDR 0x02143000
|
||||
#define FUNNEL_BASE_ADDR 0x02144000
|
||||
#define CORTEX_ROM_TABLE 0x0214F000
|
||||
#define CORTEX_DEBUG_UNIT 0x02150000
|
||||
#define CORE0_DEBUG_UNIT 0x02150000
|
||||
#define PMU0_BASE_ADDR 0x02151000
|
||||
#define CORE1_DEBUG_UNIT 0x02152000
|
||||
#define PMU1_BASE_ADDR 0x02153000
|
||||
#define CORE2_DEBUG_UNIT 0x02154000
|
||||
#define PMU2_BASE_ADDR 0x02155000
|
||||
#define CORE3_DEBUG_UNIT 0x02156000
|
||||
#define PMU3_BASE_ADDR 0x02157000
|
||||
#define CTI0_BASE_ADDR 0x02158000
|
||||
#define CTI1_BASE_ADDR 0x02159000
|
||||
#define CTI2_BASE_ADDR 0x0215A000
|
||||
#define CTI3_BASE_ADDR 0x0215B000
|
||||
#define PTM0_BASE_ADDR 0x0215C000
|
||||
#define PTM_BASE_ADDR 0x0215C000
|
||||
#define PTM1_BASE_ADDR 0x0215D000
|
||||
#define PTM2_BASE_ADDR 0x0215E000
|
||||
#define PTM3_BASE_ADDR 0x0215F000
|
||||
// *********************
|
||||
|
||||
// Legacy Defines
|
||||
#define CSD0_DDR_BASE_ADDR MMDC0_ARB_BASE_ADDR
|
||||
#define CSD1_DDR_BASE_ADDR 0xC0000000
|
||||
#define CS0_BASE_ADDR WEIM_ARB_BASE_ADDR
|
||||
// Defines for Blocks connected via AIPS (SkyBlue)
|
||||
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
|
||||
#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
|
||||
|
||||
//slots 0,7 of SDMA reserved, therefore left unused in IPMUX3
|
||||
#define SPDIF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00004000) // 0x02004000
|
||||
#define ECSPI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00008000) // 0x02008000
|
||||
#define ECSPI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0000C000) // 0x0200C000
|
||||
#define ECSPI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00010000) // 0x02010000
|
||||
#define ECSPI4_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00014000) // 0x02014000
|
||||
#define UART5_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00018000) //slot 6
|
||||
#define UART1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00020000) // 0x02020000
|
||||
#define UART2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00024000) //slot 9
|
||||
#define SSI1_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00028000) // 0x02028000
|
||||
#define SSI2_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0002C000) // 0x0202C000
|
||||
#define SSI3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00030000) // 0x02030000
|
||||
#define UART3_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00034000) //slot 13
|
||||
#define UART4_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00038000) //slot 14
|
||||
#define SPBA_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0003C000) // 0x0203C000 haku
|
||||
#define VPU_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00040000) //slot 33, global en[1], til 0x7BFFF
|
||||
|
||||
// AIPS_TZ#1- On Platform
|
||||
#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x0007C000) // 0x0207C000
|
||||
|
||||
// AIPS_TZ#1- Off Platform
|
||||
#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x00080000) // 0x02080000
|
||||
//#define USBOH3_BASE_ADDR AIPS1_BASE_ADDR
|
||||
|
||||
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00000000) // 0x02080000
|
||||
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00004000) // 0x02084000
|
||||
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00008000) // 0x02088000
|
||||
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000C000) // 0x0208C000
|
||||
#define DBGMON_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00010000) // 0x02090000
|
||||
#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00014000) // 0x02094000
|
||||
#define GPT_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00018000) // 0x02098000
|
||||
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0001C000) // 0x0209C000
|
||||
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00020000) // 0x020A0000
|
||||
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00024000) // 0x020A4000
|
||||
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00028000) // 0x020A8000
|
||||
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0002C000) // 0x020AC000
|
||||
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00030000)
|
||||
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00034000)
|
||||
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00038000) // 0x020B8000
|
||||
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0003C000) // 0x020BC000
|
||||
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00040000) // 0x020C0000
|
||||
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00044000) // 0x020C4000
|
||||
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00048000) // 0x020C8000 same as CCM_ANALOG above
|
||||
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0004C000) // 0x020CC000
|
||||
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00050000) // 0x020D0000
|
||||
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00054000) // 0x020D4000
|
||||
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00058000) // 0x020D8000
|
||||
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0005C000) // 0x020DC000 same as DVFS below
|
||||
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00060000) // 0x020E0000
|
||||
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00064000) // 0x020E4000 (was DCIC1)
|
||||
#define SPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00068000) // 0x020E8000 (was DCIC2)
|
||||
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0006C000) // 0x020EC000
|
||||
#define EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00070000) // 0x020F0000
|
||||
#define SDMA_IPS_HOST_BASE_ADDR SDMA_BASE_ADDR
|
||||
#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00074000) // 0x020F4000
|
||||
#define ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x00078000) // 0x020F8000
|
||||
#define DCP_BASE_ADDRESS (AIPS1_OFF_BASE_ADDR + 0x0007C000) // 0x020FC000
|
||||
|
||||
// AIPS_TZ#2- On Platform
|
||||
#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x0007C000) // 0x0217C000
|
||||
|
||||
// AIPS_TZ#2- Off Platform
|
||||
#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x00080000) // 0x02180000
|
||||
|
||||
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
|
||||
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
|
||||
|
||||
#define USBO2H_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00000000)
|
||||
#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00004000)
|
||||
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00008000) // 0x02188000
|
||||
#define MSHC_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000C000)
|
||||
//For ESDHC became Usdhc, temporarily allowing both new and old names
|
||||
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00010000) // 0x02190000
|
||||
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00014000) // 0x02194000
|
||||
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00018000) // 0x02198000
|
||||
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0001C000) // 0x0219C000
|
||||
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00020000) // 0x021A0000
|
||||
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00024000) // 0x021A4000
|
||||
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00028000) // 0x021A8000
|
||||
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00078000)
|
||||
//AIPS2_OFF_BASE_ADDR
|
||||
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0002C000) // 0x021AC000
|
||||
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00030000) // 0x021B0000
|
||||
#define RNGB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00034000) // 0x021B4000
|
||||
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00038000) // 0x021B8000
|
||||
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0003C000) // 0x021BC000
|
||||
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00040000) // 0x021C0000
|
||||
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00044000) // 0x021C4000
|
||||
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00048000) // 0x021C8000
|
||||
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00050000) // 0x021D0000
|
||||
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00058000) // 0x021D8000
|
||||
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x00078000)
|
||||
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0007C000)
|
||||
// clang-format
|
||||
|
||||
#endif //_SOC_MEMORY_MAP_H
|
||||
Reference in New Issue
Block a user