Support imx6q-sabrelite userland timer driver.
This commit is contained in:
TXuian
@@ -0,0 +1,28 @@
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ifeq ($(BOARD), imx6q-sabrelite)
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toolchain ?= arm-none-eabi-
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endif
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ifeq ($(BOARD), zynq7000-zc702)
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toolchain ?= arm-xilinx-eabi-
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endif
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cc = ${toolchain}gcc
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ld = ${toolchain}g++
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objdump = ${toolchain}objdump
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user_ldflags = -N -Ttext 0
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cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
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c_useropts = -O0
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INC_DIR = -I$(KERNEL_ROOT)/services/app \
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-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
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-I$(KERNEL_ROOT)/services/lib/serial \
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-I$(KERNEL_ROOT)/services/drivers/$(BOARD)/include \
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-I$(KERNEL_ROOT)/services/drivers/$(BOARD)/enet \
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-I$(KERNEL_ROOT)/services/lib/usyscall \
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-I$(KERNEL_ROOT)/services/lib/ipc
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all: gpio.o imx6dq_gpio_map.o
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@mv $^ $(KERNEL_ROOT)/services/app
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%.o: %.c
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@echo "cc $^"
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@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^
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@@ -0,0 +1,260 @@
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/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file gpio.c
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* @brief Driver to control the GPIO module.
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* @ingroup diag_gpio
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*/
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#include "gpio.h"
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#include "gpio_map.h"
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#include "regsgpio.h"
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#include "regsiomuxc.h"
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#include "sdk_types.h"
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#include "libserial.h"
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int32_t gpio_get_port_count(void)
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{
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return HW_GPIO_INSTANCE_COUNT;
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}
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int gpio_set_gpio(int32_t port, int32_t pin)
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{
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// Validate port and pin before indexing into the map arrays.
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if (port < 1 || port > HW_GPIO_INSTANCE_COUNT || pin < 0 || pin > 31) {
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debug_printf("Invalid GPIO port or pin number.\n");
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return INVALID_PARAMETER;
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}
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// Look up mux register address.
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uint32_t addr = k_gpio_mux_registers[port - 1][pin];
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if (!addr) {
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return INVALID_PARAMETER;
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}
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volatile uint32_t* reg = (volatile uint32_t*)addr;
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// Switch mux to ALT5, which is always GPIO mode. We're just using this register's
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// BM_ and BF_ macros because they are convenient, and is present on all three mx6.
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*reg = (*reg & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE)
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| BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_V(ALT5);
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return SUCCESS;
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}
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int32_t gpio_set_direction(int32_t port, int32_t pin, int32_t dir)
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{
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uint32_t oldVal = 0, newVal = 0;
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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oldVal = HW_GPIO_GDIR_RD(port);
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if (dir == GPIO_GDIR_INPUT)
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newVal = oldVal & (~(1 << pin));
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else
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newVal = oldVal | (1 << pin);
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HW_GPIO_GDIR_WR(port, newVal);
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return 0; // SUCCESS;
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}
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int32_t gpio_get_direction(int32_t port, int32_t pin)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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return (HW_GPIO_GDIR_RD(port) >> pin) & 1;
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}
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int32_t gpio_set_level(int32_t port, int32_t pin, uint32_t level)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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uint32_t mask = 1 << pin;
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int32_t dir = HW_GPIO_GDIR_RD(port) & mask ? GPIO_GDIR_OUTPUT : GPIO_GDIR_INPUT;
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if (dir != GPIO_GDIR_OUTPUT) {
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printf("GPIO_PORT%d_%d is not configured to be output!\n", port, pin);
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return -1;
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}
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uint32_t value = HW_GPIO_DR_RD(port); // read current value
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if (level == GPIO_LOW_LEVEL) // fix it up
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value &= ~mask;
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else if (level == GPIO_HIGH_LEVEL)
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value |= mask;
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HW_GPIO_DR_WR(port, value); // write new value
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return 0; // SUCCESS;
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}
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int32_t gpio_get_level(int32_t port, int32_t pin)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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uint32_t mask = 1 << pin;
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return HW_GPIO_DR_RD(port) & mask ? GPIO_HIGH_LEVEL : GPIO_LOW_LEVEL;
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}
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int32_t gpio_set_interrupt_config(int32_t port, int32_t pin, int32_t config)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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if (pin < 16) {
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// GPIOs 0-15 use ICR1 register
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uint32_t value = HW_GPIO_ICR1_RD(port); // read current value
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uint32_t field_offset = pin * 2; // fields are 2 bits wide
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value &= ~(BM_GPIO_ICR1_ICR0 << field_offset); // clear specified field
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value |= config << field_offset; // set specified field
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HW_GPIO_ICR1_WR(port, value); // write new value
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} else {
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// GPIOs 16-31 use ICR2 register
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uint32_t value = HW_GPIO_ICR2_RD(port); // read current value
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uint32_t field_offset = (pin - 16) * 2; // fields are 2 bits wide
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value &= ~(BM_GPIO_ICR2_ICR16 << field_offset); // clear specified field
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value |= config << field_offset; // set specified field
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HW_GPIO_ICR1_WR(port, value); // write new value
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}
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return 0; // SUCCESS;
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}
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int32_t gpio_set_interrupt_mask(int32_t port, int32_t pin, int32_t mask)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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uint32_t value = HW_GPIO_IMR_RD(port);
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if (mask == GPIO_IMR_MASKED)
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value &= ~(1 << pin);
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else
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value |= 1 << pin;
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HW_GPIO_GDIR_WR(port, value);
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return 0; // SUCCESS;
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}
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int32_t gpio_get_interrupt_status(int32_t port, int32_t pin)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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return HW_GPIO_ISR_RD(port) & (1 << pin) ? GPIO_ISR_ASSERTED : GPIO_ISR_NOT_ASSERTED;
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}
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int32_t gpio_clear_interrupt(int32_t port, int32_t pin)
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{
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if ((port > HW_GPIO_INSTANCE_COUNT) || (port < 1)) {
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debug_printf("Invalid GPIO Instance GPIO_PORT%d parameter. GPIO_PORT1~GPIO_PORT%d is allowed.\n",
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port, HW_GPIO_INSTANCE_COUNT);
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return INVALID_PARAMETER;
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}
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if ((pin > 31) || (pin < 0)) {
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debug_printf("Invalid GPIO Pin %d parameter. Pin 0~31 is allowed.\n", pin);
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return INVALID_PARAMETER;
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}
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uint32_t value = HW_GPIO_ISR_RD(port);
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value |= 1 << pin;
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HW_GPIO_ISR_WR(port, value);
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return 0; // SUCCESS;
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}
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@@ -0,0 +1,271 @@
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/*
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* Copyright (c) 2013, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#include "gpio_map.h"
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#include "regsiomuxc.h"
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// First subscript is bank, second is pin within the bank. There are always 32 pin
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// entries per bank. If a pin does not have an assigned GPIO, its address is 0.
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const uint32_t k_gpio_mux_registers[HW_GPIO_INSTANCE_COUNT][GPIO_PIN_COUNT] = {
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// Bank 1
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{
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_ADDR, // Pin 0
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_ADDR, // Pin 1
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_ADDR, // Pin 2
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_ADDR, // Pin 3
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_ADDR, // Pin 4
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_ADDR, // Pin 5
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_ADDR, // Pin 6
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_ADDR, // Pin 7
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_ADDR, // Pin 8
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HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_ADDR, // Pin 9
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_ADDR, // Pin 10
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_ADDR, // Pin 11
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_ADDR, // Pin 12
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_ADDR, // Pin 13
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_ADDR, // Pin 14
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HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_ADDR, // Pin 15
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_ADDR, // Pin 16
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_ADDR, // Pin 17
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_ADDR, // Pin 18
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_ADDR, // Pin 19
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_ADDR, // Pin 20
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HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_ADDR, // Pin 21
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_ADDR, // Pin 22
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_ADDR, // Pin 23
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_ADDR, // Pin 24
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_ADDR, // Pin 25
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_ADDR, // Pin 26
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_ADDR, // Pin 27
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_ADDR, // Pin 28
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_ADDR, // Pin 29
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_ADDR, // Pin 30
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HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_ADDR, // Pin 31
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},
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// Bank 2
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{
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_ADDR, // Pin 0
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_ADDR, // Pin 1
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_ADDR, // Pin 2
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_ADDR, // Pin 3
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_ADDR, // Pin 4
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_ADDR, // Pin 5
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_ADDR, // Pin 6
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HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_ADDR, // Pin 7
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_ADDR, // Pin 8
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_ADDR, // Pin 9
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_ADDR, // Pin 10
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_ADDR, // Pin 11
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_ADDR, // Pin 12
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_ADDR, // Pin 13
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_ADDR, // Pin 14
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HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_ADDR, // Pin 15
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_ADDR, // Pin 16
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_ADDR, // Pin 17
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_ADDR, // Pin 18
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_ADDR, // Pin 19
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_ADDR, // Pin 20
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_ADDR, // Pin 21
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_ADDR, // Pin 22
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_ADDR, // Pin 23
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_ADDR, // Pin 24
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_ADDR, // Pin 25
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_ADDR, // Pin 26
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HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_ADDR, // Pin 27
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_ADDR, // Pin 28
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_ADDR, // Pin 29
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_ADDR, // Pin 30
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_ADDR, // Pin 31
|
||||
},
|
||||
// Bank 3
|
||||
{
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_ADDR, // Pin 0
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_ADDR, // Pin 1
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_ADDR, // Pin 2
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_ADDR, // Pin 3
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_ADDR, // Pin 4
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_ADDR, // Pin 5
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_ADDR, // Pin 6
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_ADDR, // Pin 7
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_ADDR, // Pin 8
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_ADDR, // Pin 9
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_ADDR, // Pin 10
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_ADDR, // Pin 11
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_ADDR, // Pin 12
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_ADDR, // Pin 13
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_ADDR, // Pin 14
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_ADDR, // Pin 15
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_ADDR, // Pin 16
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_ADDR, // Pin 17
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_ADDR, // Pin 18
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_ADDR, // Pin 19
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_ADDR, // Pin 20
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_ADDR, // Pin 21
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_ADDR, // Pin 22
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_ADDR, // Pin 23
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_ADDR, // Pin 24
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_ADDR, // Pin 25
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_ADDR, // Pin 26
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_ADDR, // Pin 27
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_ADDR, // Pin 28
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_ADDR, // Pin 29
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_ADDR, // Pin 30
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_ADDR, // Pin 31
|
||||
},
|
||||
// Bank 4
|
||||
{
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_ADDR, // Pin 5
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_ADDR, // Pin 6
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_ADDR, // Pin 7
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_ADDR, // Pin 8
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_ADDR, // Pin 9
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_ADDR, // Pin 10
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_ADDR, // Pin 11
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_ADDR, // Pin 12
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_ADDR, // Pin 13
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_ADDR, // Pin 14
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_ADDR, // Pin 15
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_ADDR, // Pin 16
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_ADDR, // Pin 17
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_ADDR, // Pin 18
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_ADDR, // Pin 19
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_ADDR, // Pin 20
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_ADDR, // Pin 21
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_ADDR, // Pin 22
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_ADDR, // Pin 23
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_ADDR, // Pin 24
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_ADDR, // Pin 25
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_ADDR, // Pin 26
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_ADDR, // Pin 27
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_ADDR, // Pin 28
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_ADDR, // Pin 29
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_ADDR, // Pin 30
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_ADDR, // Pin 31
|
||||
},
|
||||
// Bank 5
|
||||
{
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_ADDR, // Pin 0
|
||||
0, // Unassigned GPIO pin 1
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_ADDR, // Pin 2
|
||||
0, // Unassigned GPIO pin 3
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_ADDR, // Pin 4
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_ADDR, // Pin 5
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_ADDR, // Pin 6
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_ADDR, // Pin 7
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_ADDR, // Pin 8
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_ADDR, // Pin 9
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_ADDR, // Pin 10
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_ADDR, // Pin 11
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_ADDR, // Pin 12
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_ADDR, // Pin 13
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_ADDR, // Pin 14
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_ADDR, // Pin 15
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_ADDR, // Pin 16
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_ADDR, // Pin 17
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_ADDR, // Pin 18
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_ADDR, // Pin 19
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_ADDR, // Pin 20
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_ADDR, // Pin 21
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_ADDR, // Pin 22
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_ADDR, // Pin 23
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_ADDR, // Pin 24
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_ADDR, // Pin 25
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_ADDR, // Pin 26
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_ADDR, // Pin 27
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_ADDR, // Pin 28
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_ADDR, // Pin 29
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_ADDR, // Pin 30
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_ADDR, // Pin 31
|
||||
},
|
||||
// Bank 6
|
||||
{
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_ADDR, // Pin 0
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_ADDR, // Pin 1
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_ADDR, // Pin 2
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_ADDR, // Pin 3
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_ADDR, // Pin 4
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_ADDR, // Pin 5
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_ADDR, // Pin 6
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_ADDR, // Pin 7
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_ADDR, // Pin 8
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_ADDR, // Pin 9
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_ADDR, // Pin 10
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_ADDR, // Pin 11
|
||||
0, // Unassigned GPIO pin 12
|
||||
0, // Unassigned GPIO pin 13
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_ADDR, // Pin 14
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_ADDR, // Pin 15
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_ADDR, // Pin 16
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_ADDR, // Pin 17
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_ADDR, // Pin 18
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_ADDR, // Pin 19
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_ADDR, // Pin 20
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_ADDR, // Pin 21
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_ADDR, // Pin 22
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_ADDR, // Pin 23
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_ADDR, // Pin 24
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_ADDR, // Pin 25
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_ADDR, // Pin 26
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_ADDR, // Pin 27
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_ADDR, // Pin 28
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_ADDR, // Pin 29
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_ADDR, // Pin 30
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_ADDR, // Pin 31
|
||||
},
|
||||
// Bank 7
|
||||
{
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_ADDR, // Pin 0
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_ADDR, // Pin 1
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_ADDR, // Pin 2
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_ADDR, // Pin 3
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_ADDR, // Pin 4
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_ADDR, // Pin 5
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_ADDR, // Pin 6
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_ADDR, // Pin 7
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_ADDR, // Pin 8
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_ADDR, // Pin 9
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_ADDR, // Pin 10
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_ADDR, // Pin 11
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_ADDR, // Pin 12
|
||||
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_ADDR, // Pin 13
|
||||
0, // Unassigned GPIO pin 14
|
||||
0, // Unassigned GPIO pin 15
|
||||
0, // Unassigned GPIO pin 16
|
||||
0, // Unassigned GPIO pin 17
|
||||
0, // Unassigned GPIO pin 18
|
||||
0, // Unassigned GPIO pin 19
|
||||
0, // Unassigned GPIO pin 20
|
||||
0, // Unassigned GPIO pin 21
|
||||
0, // Unassigned GPIO pin 22
|
||||
0, // Unassigned GPIO pin 23
|
||||
0, // Unassigned GPIO pin 24
|
||||
0, // Unassigned GPIO pin 25
|
||||
0, // Unassigned GPIO pin 26
|
||||
0, // Unassigned GPIO pin 27
|
||||
0, // Unassigned GPIO pin 28
|
||||
0, // Unassigned GPIO pin 29
|
||||
0, // Unassigned GPIO pin 30
|
||||
0, // Unassigned GPIO pin 31
|
||||
},
|
||||
};
|
||||
|
||||
// v1/121109/1.2.3
|
||||
// EOF
|
||||
Reference in New Issue
Block a user