1、feat support ch438 function on aiit-riscv64-board and xidatong-riscv64； 2、support uart3 and uart4 on xidatong-arm32 board； 3、delete useless H file on xidatong-riscv64 board。

it is OK

APP_Framework/Applications/sensor_app/altitude_bmp180.c

@@ -30,7 +30,7 @@ void AltitudeBmp180(void)
     int32 altitude;
     struct SensorQuantity *p_altitude = SensorQuantityFind(SENSOR_QUANTITY_BMP180_ALTITUDE, SENSOR_QUANTITY_ALTITUDE);
     SensorQuantityOpen(p_altitude);
-    altitude = SensorQuantityRead(p_altitude);
+    altitude = SensorQuantityReadValue(p_altitude);
 
     printf("Altitude Pressure : %d Pa\n", altitude);
 

APP_Framework/Applications/sensor_app/ch4_as830.c

@@ -31,6 +31,6 @@ void Ch4As830(void)
 {
     struct SensorQuantity *ch4 = SensorQuantityFind(SENSOR_QUANTITY_AS830_CH4, SENSOR_QUANTITY_CH4);
     SensorQuantityOpen(ch4);
-    printf("CH4 : %d %%LTL\n", SensorQuantityRead(ch4));
+    printf("CH4 : %d %%LTL\n", SensorQuantityReadValue(ch4));
     SensorQuantityClose(ch4);
 }

APP_Framework/Applications/sensor_app/co2_g8s.c

@@ -31,6 +31,6 @@ void Co2G8s(void)
 {
     struct SensorQuantity *co2 = SensorQuantityFind(SENSOR_QUANTITY_G8S_CO2, SENSOR_QUANTITY_CO2);
     SensorQuantityOpen(co2);
-    printf("CO2 : %d ppm\n", SensorQuantityRead(co2));
+    printf("CO2 : %d ppm\n", SensorQuantityReadValue(co2));
     SensorQuantityClose(co2);
 }

APP_Framework/Applications/sensor_app/co2_zg09.c

@@ -31,6 +31,6 @@ void Co2Zg09(void)
 {
     struct SensorQuantity *co2 = SensorQuantityFind(SENSOR_QUANTITY_ZG09_CO2, SENSOR_QUANTITY_CO2);
     SensorQuantityOpen(co2);
-    printf("CO2 : %d ppm\n", SensorQuantityRead(co2));
+    printf("CO2 : %d ppm\n", SensorQuantityReadValue(co2));
     SensorQuantityClose(co2);
 }

APP_Framework/Applications/sensor_app/hcho_tb600b_wq_hcho1os.c

@@ -34,7 +34,7 @@ void HchoTb600bHcho1os(void)
     SensorQuantityOpen(hcho);
     int32_t result = 0;
 
-    result = SensorQuantityRead(hcho);
+    result = SensorQuantityReadValue(hcho);
 
     printf("tvoc concentration is : %dppb\n", result);
     SensorQuantityClose(hcho);

APP_Framework/Applications/sensor_app/humidity_hs300x.c

@@ -35,7 +35,7 @@ void HumiHs300x(void)
     struct SensorQuantity *humi = SensorQuantityFind(SENSOR_QUANTITY_HS300X_HUMIDITY, SENSOR_QUANTITY_HUMI);
     SensorQuantityOpen(humi);
     for (i = 0; i < 100; i ++) {
-        humidity = SensorQuantityRead(humi);
+        humidity = SensorQuantityReadValue(humi);
         printf("Humidity : %d.%d %%RH\n", humidity/10, humidity%10);
         PrivTaskDelay(5000);
     }

APP_Framework/Applications/sensor_app/iaq_tb600b_iaq10.c

@@ -40,7 +40,7 @@ void IaqTb600bIaq10(void)
     SensorQuantityOpen(iaq);
     int32_t result = 0;
 
-    result = SensorQuantityRead(iaq);
+    result = SensorQuantityReadValue(iaq);
 
     printf("Gas concentration is : %dppb\n", result);
     SensorQuantityClose(iaq);

APP_Framework/Applications/sensor_app/pm10_0_ps5308.c

@@ -33,6 +33,6 @@ void Pm100Ps5308(void)
     struct SensorQuantity *pm10_0 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM10, SENSOR_QUANTITY_PM);
     SensorQuantityOpen(pm10_0);
     PrivTaskDelay(2000);
-    printf("PM10 : %d ug/m³\n", SensorQuantityRead(pm10_0));
+    printf("PM10 : %d ug/m³\n", SensorQuantityReadValue(pm10_0));
     SensorQuantityClose(pm10_0);
 }

APP_Framework/Applications/sensor_app/pm1_0_ps5308.c

@@ -33,6 +33,6 @@ void Pm10Ps5308(void)
     struct SensorQuantity *pm1_0 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM1_0, SENSOR_QUANTITY_PM);
     SensorQuantityOpen(pm1_0);
     PrivTaskDelay(2000);
-    printf("PM1.0 : %d ug/m³\n", SensorQuantityRead(pm1_0));
+    printf("PM1.0 : %d ug/m³\n", SensorQuantityReadValue(pm1_0));
     SensorQuantityClose(pm1_0);
 }

APP_Framework/Applications/sensor_app/pm2_5_ps5308.c

@@ -33,6 +33,6 @@ void Pm25Ps5308(void)
     struct SensorQuantity *pm2_5 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM2_5, SENSOR_QUANTITY_PM);
     SensorQuantityOpen(pm2_5);
     PrivTaskDelay(2000);
-    printf("PM2.5 : %d ug/m³\n", SensorQuantityRead(pm2_5));
+    printf("PM2.5 : %d ug/m³\n", SensorQuantityReadValue(pm2_5));
     SensorQuantityClose(pm2_5);
 }

APP_Framework/Applications/sensor_app/temperature_hs300x.c

@@ -35,7 +35,7 @@ void TempHs300x(void)
     struct SensorQuantity *temp = SensorQuantityFind(SENSOR_QUANTITY_HS300X_TEMPERATURE, SENSOR_QUANTITY_TEMP);
     SensorQuantityOpen(temp);
     for (i = 0; i < 100; i ++) {
-        temperature = SensorQuantityRead(temp);
+        temperature = SensorQuantityReadValue(temp);
         if (temperature > 0)
             printf("Temperature : %d.%d ℃\n", temperature/10, temperature%10);
         else

APP_Framework/Applications/sensor_app/tvoc_tb600b_tvoc10.c

@@ -34,7 +34,7 @@ void TvocTb600bTvoc10(void)
     SensorQuantityOpen(tvoc);
     int32_t result = 0;
 
-    result = SensorQuantityRead(tvoc);
+    result = SensorQuantityReadValue(tvoc);
 
     printf("tvoc concentration is : %dppb\n", result);
     SensorQuantityClose(tvoc);

APP_Framework/Applications/sensor_app/voice_d124.c

@@ -30,7 +30,7 @@ void VoiceD124(void)
     struct SensorQuantity *voice = SensorQuantityFind(SENSOR_QUANTITY_D124_VOICE, SENSOR_QUANTITY_VOICE);
     SensorQuantityOpen(voice);
     PrivTaskDelay(2000);
-    uint16 result = SensorQuantityRead(voice);
+    uint16 result = SensorQuantityReadValue(voice);
     printf("voice : %d.%d dB\n", result/(10*voice->value.decimal_places), result%(10*voice->value.decimal_places));
     SensorQuantityClose(voice);
 }

APP_Framework/Applications/sensor_app/winddirection_qs_fx.c

@@ -30,7 +30,7 @@ void WindDirectionQsFx(void)
     struct SensorQuantity *wind_direction = SensorQuantityFind(SENSOR_QUANTITY_QS_FX_WINDDIRECTION, SENSOR_QUANTITY_WINDDIRECTION);
     SensorQuantityOpen(wind_direction);
     PrivTaskDelay(2000);
-    uint16 result = SensorQuantityRead(wind_direction);
+    uint16 result = SensorQuantityReadValue(wind_direction);
     printf("wind direction : %d degree\n", result);
     SensorQuantityClose(wind_direction);
 }

APP_Framework/Applications/sensor_app/windspeed_qs_fs.c

@@ -30,7 +30,7 @@ void WindSpeedQsFs(void)
     struct SensorQuantity *wind_speed = SensorQuantityFind(SENSOR_QUANTITY_QS_FS_WINDSPEED, SENSOR_QUANTITY_WINDSPEED);
     SensorQuantityOpen(wind_speed);
     PrivTaskDelay(2000);
-    uint16 result = SensorQuantityRead(wind_speed);
+    uint16 result = SensorQuantityReadValue(wind_speed);
     printf("wind speed : %d.%d m/s\n", result/10, result%10);
     SensorQuantityClose(wind_speed);
 }

APP_Framework/Framework/connection/lora/e220/e220.c

@@ -624,9 +624,9 @@ static void LoraOpen(void)
 
     E220Open(adapter);
 }
+#ifdef ADD_RTTHREAD_FETURES
 MSH_CMD_EXPORT(LoraOpen,Lora open test sample);
 
-#ifdef ADD_RTTHREAD_FETURES
 static void LoraRead(void *parameter)
 {
 	int RevLen;

APP_Framework/Framework/sensor/sensor.c

@@ -314,7 +314,7 @@ int SensorQuantityClose(struct SensorQuantity *quant)
  * @param quant - sensor quantity pointer
  * @return quantity value
  */
-int SensorQuantityRead(struct SensorQuantity *quant)
+int SensorQuantityReadValue(struct SensorQuantity *quant)
 {
     if (!quant)
         return -1;
@@ -332,6 +332,29 @@ int SensorQuantityRead(struct SensorQuantity *quant)
     return result;
 }
 
+/**
+ * @description: Read quantity decimal point
+ * @param quant - sensor quantity pointer
+ * @return decimal point num, 0: 0 1: 0.1 2: 0.01 3: 0.001
+ */
+int SensorQuantityReadDecimalPoint(struct SensorQuantity *quant)
+{
+    if (!quant)
+        return -1;
+
+    int decimal_point = 0;
+    struct SensorDevice *sdev = quant->sdev;
+
+    if (!sdev)
+        return -1;
+
+    if (quant->ReadValue != NULL) {
+        decimal_point = quant->ReadDecimalPoint(quant);
+    }
+
+    return decimal_point;
+}
+
 /**
  * @description: Configure quantity mode
  * @param quant - sensor quantity pointer

APP_Framework/Framework/sensor/sensor.h

@@ -44,20 +44,29 @@ extern "C" {
 #endif
 
 /* Sensor ability */
-#define SENSOR_ABILITY_CO2      ((uint32_t)(1 << SENSOR_QUANTITY_CO2))
-#define SENSOR_ABILITY_TEMP     ((uint32_t)(1 << SENSOR_QUANTITY_TEMP))
-#define SENSOR_ABILITY_HUMI     ((uint32_t)(1 << SENSOR_QUANTITY_HUMI))
-#define SENSOR_ABILITY_HCHO     ((uint32_t)(1 << SENSOR_QUANTITY_HCHO))
-#define SENSOR_ABILITY_CO       ((uint32_t)(1 << SENSOR_QUANTITY_CO))
-#define SENSOR_ABILITY_PM       ((uint32_t)(1 << SENSOR_QUANTITY_PM))
-#define SENSOR_ABILITY_VOICE    ((uint32_t)(1 << SENSOR_QUANTITY_VOICE))
-#define SENSOR_ABILITY_CH4      ((uint32_t)(1 << SENSOR_QUANTITY_CH4))
-#define SENSOR_ABILITY_IAQ      ((uint32_t)(1 << SENSOR_QUANTITY_IAQ))
-#define SENSOR_ABILITY_TVOC     ((uint32_t)(1 << SENSOR_QUANTITY_TVOC))
-#define SENSOR_ABILITY_HCHO     ((uint32_t)(1 << SENSOR_QUANTITY_HCHO))
+#define SENSOR_ABILITY_CO2              ((uint32_t)(1 << SENSOR_QUANTITY_CO2))
+#define SENSOR_ABILITY_TEMP             ((uint32_t)(1 << SENSOR_QUANTITY_TEMP))
+#define SENSOR_ABILITY_HUMI             ((uint32_t)(1 << SENSOR_QUANTITY_HUMI))
+#define SENSOR_ABILITY_HCHO             ((uint32_t)(1 << SENSOR_QUANTITY_HCHO))
+#define SENSOR_ABILITY_CO               ((uint32_t)(1 << SENSOR_QUANTITY_CO))
+#define SENSOR_ABILITY_PM               ((uint32_t)(1 << SENSOR_QUANTITY_PM))
+#define SENSOR_ABILITY_VOICE            ((uint32_t)(1 << SENSOR_QUANTITY_VOICE))
+#define SENSOR_ABILITY_CH4              ((uint32_t)(1 << SENSOR_QUANTITY_CH4))
+#define SENSOR_ABILITY_IAQ              ((uint32_t)(1 << SENSOR_QUANTITY_IAQ))
+#define SENSOR_ABILITY_TVOC             ((uint32_t)(1 << SENSOR_QUANTITY_TVOC))
+#define SENSOR_ABILITY_HCHO             ((uint32_t)(1 << SENSOR_QUANTITY_HCHO))
 #define SENSOR_ABILITY_WINDSPEED        ((uint32_t)(1 << SENSOR_QUANTITY_WINDSPEED))
 #define SENSOR_ABILITY_WINDDIRECTION    ((uint32_t)(1 << SENSOR_QUANTITY_WINDDIRECTION))
-#define SENSOR_ABILITY_ALTITUDE ((uint32_t)(1 << SENSOR_QUANTITY_ALTITUDE))
+#define SENSOR_ABILITY_ALTITUDE         ((uint32_t)(1 << SENSOR_QUANTITY_ALTITUDE))
+#define SENSOR_ABILITY_O3               ((uint32_t)(1 << SENSOR_QUANTITY_O3))
+#define SENSOR_ABILITY_O2               ((uint32_t)(1 << SENSOR_QUANTITY_O2))
+#define SENSOR_ABILITY_NO2              ((uint32_t)(1 << SENSOR_QUANTITY_NO2))
+#define SENSOR_ABILITY_SO2              ((uint32_t)(1 << SENSOR_QUANTITY_SO2))
+#define SENSOR_ABILITY_NH3              ((uint32_t)(1 << SENSOR_QUANTITY_NH3))
+#define SENSOR_ABILITY_CH20             ((uint32_t)(1 << SENSOR_QUANTITY_CH20))
+#define SENSOR_ABILITY_C2H5OH           ((uint32_t)(1 << SENSOR_QUANTITY_C2H5OH))
+#define SENSOR_ABILITY_AQS              ((uint32_t)(1 << SENSOR_QUANTITY_AQS))
+#define SENSOR_ABILITY_PM1              ((uint32_t)(1 << SENSOR_QUANTITY_PM1))
 
 struct SensorProductInfo {
     uint32_t ability;           /* Bitwise OR of sensor ability */
@@ -76,16 +85,17 @@ struct SensorDone {
 };
 
 struct SensorDevice {
-    char *name;                             /* Name of sensor */
-    struct SensorProductInfo *info;         /* Sensor model info */
+    char *name;                               /* Name of sensor */
+    struct SensorProductInfo *info;           /* Sensor model info */
     struct SensorDone *done;
-    int fd;                                 /* File descriptor */
-    int status;                             /* Sensor work mode */
+    int fd;                                   /* File descriptor */
+    int status;                               /* Sensor work mode */
     uint8_t buffer[SENSOR_RECEIVE_BUFFSIZE];  /* Buffer for read data */
 
-    int ref_cnt;                            /* Reference count */
-    DoublelistType quant_list;          /* Sensor quantity link */
-    struct DoublelistNode link;      /* Sensors link node */
+    int ref_cnt;                              /* Reference count */
+    DoublelistType quant_list;                /* Sensor quantity link */
+    struct DoublelistNode link;               /* Sensors link node */
+    void *private_data;                       /* user define private data */
 };
 
 enum SensorQuantityType {
@@ -102,7 +112,17 @@ enum SensorQuantityType {
     SENSOR_QUANTITY_WINDSPEED,
     SENSOR_QUANTITY_WINDDIRECTION,
     SENSOR_QUANTITY_ALTITUDE,
+    SENSOR_QUANTITY_O3,
+    SENSOR_QUANTITY_O2,
+    SENSOR_QUANTITY_NO2,
+    SENSOR_QUANTITY_SO2,
+    SENSOR_QUANTITY_NH3,
+    SENSOR_QUANTITY_CH20,
+    SENSOR_QUANTITY_C2H5OH,
+    SENSOR_QUANTITY_AQS,
+    SENSOR_QUANTITY_PM1,
     /* ...... */
+    SENSIR_QUANTITY_INTEGRATION,
     SENSOR_QUANTITY_END,
 };
 
@@ -122,6 +142,7 @@ struct SensorQuantity {
     struct SensorDevice *sdev;
 
     int32_t (*ReadValue)(struct SensorQuantity *quant);
+    int32_t (*ReadDecimalPoint)(struct SensorQuantity *quant);
 
     struct DoublelistNode quant_link;
     struct DoublelistNode link;
@@ -135,7 +156,8 @@ int SensorQuantityRegister(struct SensorQuantity *quant);
 int SensorQuantityUnregister(struct SensorQuantity *quant);
 int SensorQuantityOpen(struct SensorQuantity *quant);
 int SensorQuantityClose(struct SensorQuantity *quant);
-int SensorQuantityRead(struct SensorQuantity *quant);
+int SensorQuantityReadValue(struct SensorQuantity *quant);
+int SensorQuantityReadDecimalPoint(struct SensorQuantity *quant);
 int SensorQuantityControl(struct SensorQuantity *quant, int cmd);
 
 uint32_t Crc16(uint8_t * data, uint8_t length);

Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h

@@ -31,260 +31,245 @@
 /* chip definition */
 /* CH438serial port0 register address */
 
-#define REG_RBR0_ADDR        0x00      /* serial port0receive buffer register address */
-#define REG_THR0_ADDR        0x00      /* serial port0send hold register address */
-#define REG_IER0_ADDR          0x01      /* serial port0interrupt enable register address */
-#define REG_IIR0_ADDR           0x02      /* serial port0interrupt identifies register address */
-#define REG_FCR0_ADDR        0x02      /* serial port0FIFO controls register address */
-#define REG_LCR0_ADDR         0x03      /* serial port0circuit control register address */
-#define REG_MCR0_ADDR        0x04      /* serial port0MODEM controls register address */
-#define REG_LSR0_ADDR         0x05      /* serial port0line status register address */
-#define REG_MSR0_ADDR        0x06      /* serial port0address of MODEM status register */
-#define REG_SCR0_ADDR         0x07      /* serial port0the user can define the register address */
-#define REG_DLL0_ADDR         0x00      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM0_ADDR        0x01      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR0_ADDR            0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR            0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR            0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR            0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR            0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR            0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR            0x04      /* serial port0MODEM controls register address */
+#define REG_LSR0_ADDR            0x05      /* serial port0line status register address */
+#define REG_MSR0_ADDR            0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR            0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR            0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR            0x01      /* Baud rate divisor latch high 8-bit byte address */
 
 /* CH438serial port1 register address */
 
-#define REG_RBR1_ADDR       0x10      /* serial port1receive buffer register address */
-#define REG_THR1_ADDR       0x10      /* serial port1send hold register address */
-#define REG_IER1_ADDR         0x11      /* serial port1interrupt enable register address */
-#define REG_IIR1_ADDR          0x12      /* serial port1interrupt identifies register address */
-#define REG_FCR1_ADDR       0x12      /* serial port1FIFO controls register address */
-#define REG_LCR1_ADDR       0x13      /* serial port1circuit control register address */
-#define REG_MCR1_ADDR      0x14      /* serial port1MODEM controls register address */
-#define REG_LSR1_ADDR       0x15      /* serial port1line status register address */
-#define REG_MSR1_ADDR      0x16      /* serial port1address of MODEM status register */
-#define REG_SCR1_ADDR       0x17      /* serial port1the user can define the register address */
-#define REG_DLL1_ADDR       0x10      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM1_ADDR      0x11      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR1_ADDR            0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR            0x10      /* serial port1send hold register address */
+#define REG_IER1_ADDR            0x11      /* serial port1interrupt enable register address */
+#define REG_IIR1_ADDR            0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR            0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR            0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR            0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR            0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR            0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR            0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR            0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR            0x11      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port2 register address */
 
-#define REG_RBR2_ADDR       0x20      /* serial port2receive buffer register address */
-#define REG_THR2_ADDR       0x20      /* serial port2send hold register address */
-#define REG_IER2_ADDR         0x21      /* serial port2interrupt enable register address */
-#define REG_IIR2_ADDR          0x22      /* serial port2interrupt identifies register address */
-#define REG_FCR2_ADDR       0x22      /* serial port2FIFO controls register address */
-#define REG_LCR2_ADDR       0x23      /* serial port2circuit control register address */
-#define REG_MCR2_ADDR      0x24      /* serial port2MODEM controls register address */
-#define REG_LSR2_ADDR       0x25      /* serial port2line status register address */
-#define REG_MSR2_ADDR      0x26      /* serial port2address of MODEM status register */
-#define REG_SCR2_ADDR       0x27      /* serial port2the user can define the register address */
-#define REG_DLL2_ADDR       0x20      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM2_ADDR      0x21      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR2_ADDR            0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR            0x20      /* serial port2send hold register address */
+#define REG_IER2_ADDR            0x21      /* serial port2interrupt enable register address */
+#define REG_IIR2_ADDR            0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR            0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR            0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR            0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR            0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR            0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR            0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR            0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR            0x21      /* Baud rate divisor latch high 8-bit byte address */
 
 
 
 /* CH438serial port3 register address */
 
-#define REG_RBR3_ADDR       0x30      /* serial port3receive buffer register address */
-#define REG_THR3_ADDR       0x30      /* serial port3send hold register address */
-#define REG_IER3_ADDR         0x31      /* serial port3interrupt enable register address */
-#define REG_IIR3_ADDR          0x32      /* serial port3interrupt identifies register address */
-#define REG_FCR3_ADDR       0x32      /* serial port3FIFO controls register address */
-#define REG_LCR3_ADDR       0x33      /* serial port3circuit control register address */
-#define REG_MCR3_ADDR      0x34      /* serial port3MODEM controls register address */
-#define REG_LSR3_ADDR       0x35      /* serial port3line status register address */
-#define REG_MSR3_ADDR      0x36      /* serial port3address of MODEM status register */
-#define REG_SCR3_ADDR       0x37      /* serial port3the user can define the register address */
-#define REG_DLL3_ADDR       0x30      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM3_ADDR      0x31      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR3_ADDR            0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR            0x30      /* serial port3send hold register address */
+#define REG_IER3_ADDR            0x31      /* serial port3interrupt enable register address */
+#define REG_IIR3_ADDR            0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR            0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR            0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR            0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR            0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR            0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR            0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR            0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR            0x31      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port4 register address */
 
-#define REG_RBR4_ADDR       0x08      /* serial port4receive buffer register address */
-#define REG_THR4_ADDR       0x08      /* serial port4send hold register address */
-#define REG_IER4_ADDR         0x09      /* serial port4interrupt enable register address */
-#define REG_IIR4_ADDR          0x0A      /* serial port4interrupt identifies register address */
-#define REG_FCR4_ADDR       0x0A      /* serial port4FIFO controls register address */
-#define REG_LCR4_ADDR       0x0B      /* serial port4circuit control register address */
-#define REG_MCR4_ADDR      0x0C      /* serial port4MODEM controls register address */
-#define REG_LSR4_ADDR       0x0D      /* serial port4line status register address */
-#define REG_MSR4_ADDR      0x0E      /* serial port4address of MODEM status register */
-#define REG_SCR4_ADDR       0x0F      /* serial port4the user can define the register address */
-#define REG_DLL4_ADDR       0x08      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM4_ADDR      0x09      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR4_ADDR            0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR            0x08      /* serial port4send hold register address */
+#define REG_IER4_ADDR            0x09      /* serial port4interrupt enable register address */
+#define REG_IIR4_ADDR            0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR            0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR            0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR            0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR            0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR            0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR            0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR            0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR            0x09      /* Baud rate divisor latch high 8-bit byte address */
 
 
 
 /* CH438serial port5 register address */
 
-#define REG_RBR5_ADDR       0x18      /* serial port5receive buffer register address */
-#define REG_THR5_ADDR       0x18      /* serial port5send hold register address */
-#define REG_IER5_ADDR         0x19      /* serial port5interrupt enable register address */
-#define REG_IIR5_ADDR          0x1A      /* serial port5interrupt identifies register address */
-#define REG_FCR5_ADDR       0x1A      /* serial port5FIFO controls register address */
-#define REG_LCR5_ADDR       0x1B      /* serial port5circuit control register address */
-#define REG_MCR5_ADDR      0x1C      /* serial port5MODEM controls register address */
-#define REG_LSR5_ADDR       0x1D      /* serial port5line status register address */
-#define REG_MSR5_ADDR      0x1E      /* serial port5address of MODEM status register */
-#define REG_SCR5_ADDR       0x1F      /* serial port5the user can define the register address */
-#define REG_DLL5_ADDR       0x18      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM5_ADDR      0x19      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR5_ADDR            0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR            0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR            0x19      /* serial port5interrupt enable register address */
+#define REG_IIR5_ADDR            0x1A      /* serial port5interrupt identifies register address */
+#define REG_FCR5_ADDR            0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR            0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR            0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR            0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR            0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR            0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR            0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR            0x19      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port6 register address */
 
-#define REG_RBR6_ADDR       0x28      /* serial port6receive buffer register address */
-#define REG_THR6_ADDR       0x28      /* serial port6send hold register address */
-#define REG_IER6_ADDR         0x29      /* serial port6interrupt enable register address */
-#define REG_IIR6_ADDR          0x2A      /* serial port6interrupt identifies register address */
-#define REG_FCR6_ADDR       0x2A      /* serial port6FIFO controls register address */
-#define REG_LCR6_ADDR       0x2B      /* serial port6circuit control register address */
-#define REG_MCR6_ADDR      0x2C      /* serial port6MODEM controls register address */
-#define REG_LSR6_ADDR       0x2D      /* serial port6line status register address */
-#define REG_MSR6_ADDR      0x2E      /* serial port6address of MODEM status register */
-#define REG_SCR6_ADDR       0x2F      /* serial port6the user can define the register address */
-#define REG_DLL6_ADDR       0x28      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM6_ADDR      0x29      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR6_ADDR            0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR            0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR            0x29      /* serial port6interrupt enable register address */
+#define REG_IIR6_ADDR            0x2A      /* serial port6interrupt identifies register address */
+#define REG_FCR6_ADDR            0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR            0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR            0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR            0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR            0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR            0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR            0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR            0x29      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port7 register address */
 
-#define REG_RBR7_ADDR       0x38      /* serial port7receive buffer register address */
-#define REG_THR7_ADDR       0x38      /* serial port7send hold register address */
-#define REG_IER7_ADDR         0x39      /* serial port7interrupt enable register address */
-#define REG_IIR7_ADDR          0x3A      /* serial port7interrupt identifies register address */
-#define REG_FCR7_ADDR       0x3A      /* serial port7FIFO controls register address */
-#define REG_LCR7_ADDR       0x3B      /* serial port7circuit control register address */
-#define REG_MCR7_ADDR      0x3C      /* serial port7MODEM controls register address */
-#define REG_LSR7_ADDR       0x3D      /* serial port7line status register address */
-#define REG_MSR7_ADDR      0x3E      /* serial port7address of MODEM status register */
-#define REG_SCR7_ADDR       0x3F      /* serial port7the user can define the register address */
-#define REG_DLL7_ADDR       0x38      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM7_ADDR      0x39      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_RBR7_ADDR            0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR            0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR            0x39      /* serial port7interrupt enable register address */
+#define REG_IIR7_ADDR            0x3A      /* serial port7interrupt identifies register address */
+#define REG_FCR7_ADDR            0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR            0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR            0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR            0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR            0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR            0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR            0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR            0x39      /* Baud rate divisor latch high 8-bit byte address */
 
 
-#define REG_SSR_ADDR        0x4F       /* pecial status register address */
+#define REG_SSR_ADDR             0x4F       /* pecial status register address */
 
 
 /* IER register bit */
 
-#define BIT_IER_RESET                0x80      /* The bit is 1 soft reset serial port */
-#define BIT_IER_LOWPOWER    0x40      /* The bit is 1 close serial port internal reference clock */
-#define BIT_IER_SLP                     0x20      /* serial port0 is SLP, 1 close clock vibrator  */
-#define BIT_IER1_CK2X                0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
-#define BIT_IER_IEMODEM         0x08      /* The bit is 1 allows MODEM input status to interrupt */
-#define BIT_IER_IELINES             0x04      /* The bit is 1 allow receiving line status to be interrupted */
-#define BIT_IER_IETHRE              0x02      /* The bit is 1 allows the send hold register to break in mid-air */
-#define BIT_IER_IERECV               0x01      /* The bit is 1 allows receiving data interrupts */
+#define BIT_IER_RESET            0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER         0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP              0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X            0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM          0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES          0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE           0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV           0x01      /* The bit is 1 allows receiving data interrupts */
 
 /* IIR register bit */
 
-#define BIT_IIR_FIFOENS1    0x80
-#define BIT_IIR_FIFOENS0    0x40      /* The two is 1 said use FIFO */
+#define BIT_IIR_FIFOENS1         0x80
+#define BIT_IIR_FIFOENS0         0x40      /* The two is 1 said use FIFO */
 
 /* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
 1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
-#define BIT_IIR_IID3        0x08
-#define BIT_IIR_IID2        0x04
-#define BIT_IIR_IID1        0x02
-#define BIT_IIR_NOINT  0x01
+#define BIT_IIR_IID3             0x08
+#define BIT_IIR_IID2             0x04
+#define BIT_IIR_IID1             0x02
+#define BIT_IIR_NOINT            0x01
 
 /* FCR register bit */
 
 /* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
-#define BIT_FCR_RECVTG1     0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
-#define BIT_FCR_RECVTG0     0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG1          0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0          0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
 
-#define BIT_FCR_TFIFORST    0x04      /* The bit is 1 empty the data sent in FIFO */
-#define BIT_FCR_RFIFORST    0x02      /* The bit is 1 empty the data sent in FIFO */
-#define BIT_FCR_FIFOEN         0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
+#define BIT_FCR_TFIFORST         0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST         0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_FIFOEN           0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
 
 /* LCR register bit */
 
-#define BIT_LCR_DLAB              0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
-#define BIT_LCR_BREAKEN     0x40      /* 1 forces a BREAK line interval*/
+#define BIT_LCR_DLAB             0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN          0x40      /* 1 forces a BREAK line interval*/
 
 /* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
-#define BIT_LCR_PARMODE1    0x20      /* Sets the parity bit format */
-#define BIT_LCR_PARMODE0    0x10      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE1         0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0         0x10      /* Sets the parity bit format */
 
-#define BIT_LCR_PAREN         0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
-#define BIT_LCR_STOPBIT     0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+#define BIT_LCR_PAREN            0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT          0x04      /* If is 1, then two stop bits, is 0, a stop bit */
 
 /* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
-#define BIT_LCR_WORDSZ1     0x02      /* Set the word length length */
-#define BIT_LCR_WORDSZ0     0x01
+#define BIT_LCR_WORDSZ1          0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0          0x01
 
 /* MCR register bit */
 
-#define BIT_MCR_AFE            0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
-#define BIT_MCR_LOOP        0x10      /* Is the test mode of 1 enabling internal loop */
-#define BIT_MCR_OUT2        0x08      /* 1 Allows an interrupt request for the serial port output  */
-#define BIT_MCR_OUT1        0x04      /* The MODEM control bit defined for the user */
-#define BIT_MCR_RTS            0x02      /* The bit is 1 RTS pin  output  effective  */
-#define BIT_MCR_DTR            0x01      /* The bit is 1 DTR pin  output  effective  */
+#define BIT_MCR_AFE              0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP             0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2             0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1             0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS              0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR              0x01      /* The bit is 1 DTR pin  output  effective  */
 
 /* LSR register bit */
 
-#define BIT_LSR_RFIFOERR    0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_RFIFOERR         0x80      /* 1 said There is at least one error in receiving FIFO */
 #define BIT_LSR_TEMT             0x40      /* 1 said THR and TSR are empty */
-#define BIT_LSR_THRE              0x20      /* 1 said THR is empty*/
-#define BIT_LSR_BREAKINT    0x10      /* The bit is 1 said the BREAK line interval was detected*/
-#define BIT_LSR_FRAMEERR   0x08      /* The bit is 1 said error reading data frame */
-#define BIT_LSR_PARERR         0x04      /* The bit is 1 said parity error */
-#define BIT_LSR_OVERR           0x02      /*  1 said receive FIFO buffer overflow */
-#define BIT_LSR_DATARDY      0x01      /* The bit is 1 said receive data received in FIFO */
+#define BIT_LSR_THRE             0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT         0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR         0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR           0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_OVERR            0x02      /*  1 said receive FIFO buffer overflow */
+#define BIT_LSR_DATARDY          0x01      /* The bit is 1 said receive data received in FIFO */
 
 /* MSR register bit */
 
-#define BIT_MSR_DCD         0x80      /* The bit is 1 said DCD pin  effective  */
-#define BIT_MSR_RI              0x40      /* The bit is 1 said RI pin  effective  */
-#define BIT_MSR_DSR         0x20      /* The bit is 1 said DSR pin  effective  */
-#define BIT_MSR_CTS          0x10      /* The bit is 1 said CTS pin  effective  */
-#define BIT_MSR_DDCD      0x08      /* The bit is 1 said DCD pin The input state has changed */
-#define BIT_MSR_TERI        0x04      /* The bit is 1 said RI pin The input state has changed */
-#define BIT_MSR_DDSR      0x02      /* The bit is 1 said DSR pin The input state has changed */
-#define BIT_MSR_DCTS       0x01      /* The bit is 1 said CTS pin The input state has changed */
+#define BIT_MSR_DCD              0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_RI               0x40      /* The bit is 1 said RI pin  effective  */
+#define BIT_MSR_DSR              0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS              0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD             0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI             0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR             0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS             0x01      /* The bit is 1 said CTS pin The input state has changed */
 
 /* Interrupt status code */
 
-#define INT_NOINT                          0x01      /* There is no interruption */
-#define INT_THR_EMPTY               0x02      /* THR empty interruption */
-#define INT_RCV_OVERTIME        0x0C      /* Receive timeout interrupt */
-#define INT_RCV_SUCCESS          0x04      /* Interrupts are available to receive data */
-#define INT_RCV_LINES                 0x06      /* Receiving line status interrupted */
-#define INT_MODEM_CHANGE    0x00      /* MODEM input changes interrupt */
+#define INT_NOINT                    0x01      /* There is no interruption */
+#define INT_THR_EMPTY                0x02      /* THR empty interruption */
+#define INT_RCV_OVERTIME             0x0C      /* Receive timeout interrupt */
+#define INT_RCV_SUCCESS              0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES                0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE             0x00      /* MODEM input changes interrupt */
 
-#define CH438_IIR_FIFOS_ENABLED 0xC0  /* use FIFO */
+#define CH438_IIR_FIFOS_ENABLED      0xC0  /* use FIFO */
 
-#define Fpclk           1843200         /* Define the internal clock frequency  */
+#define Fpclk                 1843200         /* Define the internal clock frequency  */
 
-#if 0
-#define CH438_D0_PIN	GET_PIN(E,2)
-#define CH438_D1_PIN	GET_PIN(E,3)
-#define CH438_D2_PIN	GET_PIN(E,4)
-#define CH438_D3_PIN	GET_PIN(E,5)
-#define CH438_D4_PIN	GET_PIN(E,6)
-#define CH438_D5_PIN	GET_PIN(F,6)
-#define CH438_D6_PIN	GET_PIN(F,7)
-#define CH438_D7_PIN	GET_PIN(F,8)
-#define CH438_NWR_PIN	GET_PIN(C,4)
-#define CH438_NRD_PIN	GET_PIN(C,5)
-#define CH438_NCS_PIN	GET_PIN(B,1)
-#define CH438_ALE_PIN	GET_PIN(B,2)
-#define CH438_INT_PIN	GET_PIN(C,13)
-#endif
 #define CH438_D0_PIN	      1
 #define CH438_D1_PIN	      2
 #define CH438_D2_PIN	      3
 #define CH438_D3_PIN	      4
 #define CH438_D4_PIN	      5
-#define CH438_D5_PIN	    18
-#define CH438_D6_PIN	    19
-#define CH438_D7_PIN	    20
-#define CH438_NWR_PIN	44
-#define CH438_NRD_PIN	 45
-#define CH438_NCS_PIN	  47
-#define CH438_ALE_PIN	  48
-#define CH438_INT_PIN	     7
-#define	DIR_485CH1_PIN	 22	//485ch1 = ext_uart3
-#define	DIR_485CH2_PIN	 21	//485ch2 = ext_uart2
-#define	DIR_485CH3_PIN	123	//485ch3 = ext_uart7
+#define CH438_D5_PIN	      18
+#define CH438_D6_PIN	      19
+#define CH438_D7_PIN	      20
+#define CH438_NWR_PIN	      44
+#define CH438_NRD_PIN	      45
+#define CH438_NCS_PIN	      47
+#define CH438_ALE_PIN	      48
+#define CH438_INT_PIN	      7
+#define	DIR_485CH1_PIN	      22	//485ch1 = ext_uart3
+#define	DIR_485CH2_PIN	      21	//485ch2 = ext_uart2
+#define	DIR_485CH3_PIN	      123	//485ch3 = ext_uart7
 
 void CH438RegTest(unsigned char num);
 void Set485Input(uint8 ch_no);

Ubiquitous/XiZi/board/aiit-riscv64-board/board.c

@@ -173,7 +173,6 @@ struct InitSequenceDesc _board_init[] =
 	{ "io_config", IoConfigInit },
 #endif
 #ifdef BSP_USING_CH438
-
     { "hw_extuart", HwCh438Init },
 #endif
 #ifdef BSP_USING_SPI

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Kconfig

@@ -39,98 +39,5 @@ if BSP_USING_CH438
     config CH438_DEVICE_NAME_7
         string
         default "extuart_dev7"
-
-    config BSP_CH438_ALE_PIN
-        int "ALE pin number for ch438"
-        default 23
-
-    config BSP_CH438_NWR_PIN
-        int "NWR pin number for ch438"
-        default 24
-
-    config BSP_CH438_NRD_PIN
-        int "NRD pin number for ch438"
-        default 25
-        
-    config BSP_CH438_D0_PIN
-        int "D0 pin number for ch438"
-        default 27
-        
-    config BSP_CH438_D1_PIN
-        int "D1 pin number for ch438"
-        default 28
-        
-    config BSP_CH438_D2_PIN
-        int "D2 pin number for ch438"
-        default 29
-        
-    config BSP_CH438_D3_PIN
-        int "D3 pin number for ch438"
-        default 30
-        
-    config BSP_CH438_D4_PIN
-        int "D4 pin number for ch438"
-        default 31
-        
-    config BSP_CH438_D5_PIN
-        int "D5 pin number for ch438"
-        default 32
-        
-    config BSP_CH438_D6_PIN
-        int "D6 pin number for ch438"
-        default 33
-        
-    config BSP_CH438_D7_PIN
-        int "D7 pin number for ch438"
-        default 34
-        
-    config BSP_CH438_INT_PIN
-        int "INT pin number for ch438"
-        default 35
-        
-    config BSP_485_dir
-        int "485 direction pin number for ch438"
-        default 18
-        
-
-    menuconfig BSP_USING_4G_OR_NB
-        bool "Select using the ec200t(4G) or bc28(NB-IOT)"
-        default y
-        if BSP_USING_4G_OR_NB
-            choice
-                prompt "Select using the ec200t(4G) or bc28(NB-IOT)"
-                default BSP_USING_4G
-                config BSP_USING_4G
-                    bool "Using ec200t(4G)"
-                config BSP_USING_NBIOT
-                    bool "Using bc26(NB-IOT)"
-            endchoice
-
-
-            if BSP_USING_4G
-                config BSP_4G_STATUS
-                    int "STATUS pin number for ec200t"
-                    default 21
-                config BSP_4G_POWERKEY
-                    int "POWERKEY pin number for ec200t"
-                    default 37
-            endif
-
-            if BSP_USING_NBIOT
-                config BSP_NB_RESET
-                    int "RESET pin number for bc28"
-                    default 21
-            endif
-        endif
-
-    menuconfig BSP_USING_WIFI_HFA21
-        bool "Using the hfa21(WIFI)"
-        default y
-        if BSP_USING_WIFI_HFA21
-            config BSP_WIFI_RST
-                int "RESET pin number for hfa21"
-                default 22
-        endif
-
 endif
 

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/drv_io_config.c

@@ -89,6 +89,21 @@ static struct io_config
    
     IOCONFIG(15, FUNC_GPIO3),
     IOCONFIG(17, FUNC_GPIO4),
+
+#ifdef BSP_USING_CH438
+    IOCONFIG(BSP_CH438_ALE_PIN,  HS_GPIO(FPIOA_CH438_ALE)),      
+    IOCONFIG(BSP_CH438_NWR_PIN,  HS_GPIO(FPIOA_CH438_NWR)),      
+    IOCONFIG(BSP_CH438_NRD_PIN,  HS_GPIO(FPIOA_CH438_NRD)),      
+    IOCONFIG(BSP_CH438_INT_PIN,  HS_GPIO(FPIOA_CH438_INT)),      
+    IOCONFIG(BSP_CH438_D0_PIN,  HS_GPIO(FPIOA_CH438_D0)),      
+    IOCONFIG(BSP_CH438_D1_PIN,  HS_GPIO(FPIOA_CH438_D1)),      
+    IOCONFIG(BSP_CH438_D2_PIN,  HS_GPIO(FPIOA_CH438_D2)),      
+    IOCONFIG(BSP_CH438_D3_PIN,  HS_GPIO(FPIOA_CH438_D3)),      
+    IOCONFIG(BSP_CH438_D4_PIN,  HS_GPIO(FPIOA_CH438_D4)),      
+    IOCONFIG(BSP_CH438_D5_PIN,  HS_GPIO(FPIOA_CH438_D5)),      
+    IOCONFIG(BSP_CH438_D6_PIN,  HS_GPIO(FPIOA_CH438_D6)),      
+    IOCONFIG(BSP_CH438_D7_PIN,  HS_GPIO(FPIOA_CH438_D7))
+#endif
 };
 
 static int PrintIoConfig()

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h

@@ -29,230 +29,232 @@
 
 /* CH438serial port0 register address */
 
-#define REG_RBR0_ADDR        0x00      /* serial port0receive buffer register address */
-#define REG_THR0_ADDR        0x00      /* serial port0send hold register address */
-#define REG_IER0_ADDR          0x01      /* serial port0interrupt enable register address */
-#define REG_IIR0_ADDR           0x02      /* serial port0interrupt identifies register address */
-#define REG_FCR0_ADDR        0x02      /* serial port0FIFO controls register address */
-#define REG_LCR0_ADDR        0x03      /* serial port0circuit control register address */
-#define REG_MCR0_ADDR       0x04      /* serial port0MODEM controls register address */
+#define REG_RBR0_ADDR         0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR         0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR         0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR         0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR         0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR         0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR         0x04      /* serial port0MODEM controls register address */
 #define REG_LSR0_ADDR         0x05      /* serial port0line status register address */
-#define REG_MSR0_ADDR       0x06      /* serial port0address of MODEM status register */
-#define REG_SCR0_ADDR        0x07      /* serial port0the user can define the register address */
-#define REG_DLL0_ADDR        0x00      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM0_ADDR       0x01      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_MSR0_ADDR         0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR         0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR         0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR         0x01      /* Baud rate divisor latch high 8-bit byte address */
 
 /* CH438serial port1 register address */
 
-#define REG_RBR1_ADDR       0x10      /* serial port1receive buffer register address */
-#define REG_THR1_ADDR       0x10      /* serial port1send hold register address */
+#define REG_RBR1_ADDR         0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR         0x10      /* serial port1send hold register address */
 #define REG_IER1_ADDR         0x11      /* serial port1interrupt enable register address */
-#define REG_IIR1_ADDR          0x12      /* serial port1interrupt identifies register address */
-#define REG_FCR1_ADDR       0x12      /* serial port1FIFO controls register address */
-#define REG_LCR1_ADDR       0x13      /* serial port1circuit control register address */
-#define REG_MCR1_ADDR      0x14      /* serial port1MODEM controls register address */
-#define REG_LSR1_ADDR       0x15      /* serial port1line status register address */
-#define REG_MSR1_ADDR      0x16      /* serial port1address of MODEM status register */
-#define REG_SCR1_ADDR       0x17      /* serial port1the user can define the register address */
-#define REG_DLL1_ADDR       0x10      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM1_ADDR      0x11      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_IIR1_ADDR         0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR         0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR         0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR         0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR         0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR         0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR         0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR         0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR         0x11      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port2 register address */
 
-#define REG_RBR2_ADDR       0x20      /* serial port2receive buffer register address */
-#define REG_THR2_ADDR       0x20      /* serial port2send hold register address */
+#define REG_RBR2_ADDR         0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR         0x20      /* serial port2send hold register address */
 #define REG_IER2_ADDR         0x21      /* serial port2interrupt enable register address */
-#define REG_IIR2_ADDR          0x22      /* serial port2interrupt identifies register address */
-#define REG_FCR2_ADDR       0x22      /* serial port2FIFO controls register address */
-#define REG_LCR2_ADDR       0x23      /* serial port2circuit control register address */
-#define REG_MCR2_ADDR      0x24      /* serial port2MODEM controls register address */
-#define REG_LSR2_ADDR       0x25      /* serial port2line status register address */
-#define REG_MSR2_ADDR      0x26      /* serial port2address of MODEM status register */
-#define REG_SCR2_ADDR       0x27      /* serial port2the user can define the register address */
-#define REG_DLL2_ADDR       0x20      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM2_ADDR      0x21      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_IIR2_ADDR         0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR         0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR         0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR         0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR         0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR         0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR         0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR         0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR         0x21      /* Baud rate divisor latch high 8-bit byte address */
 
 
 
 /* CH438serial port3 register address */
 
-#define REG_RBR3_ADDR       0x30      /* serial port3receive buffer register address */
-#define REG_THR3_ADDR       0x30      /* serial port3send hold register address */
+#define REG_RBR3_ADDR         0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR         0x30      /* serial port3send hold register address */
 #define REG_IER3_ADDR         0x31      /* serial port3interrupt enable register address */
-#define REG_IIR3_ADDR          0x32      /* serial port3interrupt identifies register address */
-#define REG_FCR3_ADDR       0x32      /* serial port3FIFO controls register address */
-#define REG_LCR3_ADDR       0x33      /* serial port3circuit control register address */
-#define REG_MCR3_ADDR      0x34      /* serial port3MODEM controls register address */
-#define REG_LSR3_ADDR       0x35      /* serial port3line status register address */
-#define REG_MSR3_ADDR      0x36      /* serial port3address of MODEM status register */
-#define REG_SCR3_ADDR       0x37      /* serial port3the user can define the register address */
-#define REG_DLL3_ADDR       0x30      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM3_ADDR      0x31      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_IIR3_ADDR         0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR         0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR         0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR         0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR         0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR         0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR         0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR         0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR         0x31      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port4 register address */
 
-#define REG_RBR4_ADDR       0x08      /* serial port4receive buffer register address */
-#define REG_THR4_ADDR       0x08      /* serial port4send hold register address */
+#define REG_RBR4_ADDR         0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR         0x08      /* serial port4send hold register address */
 #define REG_IER4_ADDR         0x09      /* serial port4interrupt enable register address */
-#define REG_IIR4_ADDR          0x0A      /* serial port4interrupt identifies register address */
-#define REG_FCR4_ADDR       0x0A      /* serial port4FIFO controls register address */
-#define REG_LCR4_ADDR       0x0B      /* serial port4circuit control register address */
-#define REG_MCR4_ADDR      0x0C      /* serial port4MODEM controls register address */
-#define REG_LSR4_ADDR       0x0D      /* serial port4line status register address */
-#define REG_MSR4_ADDR      0x0E      /* serial port4address of MODEM status register */
-#define REG_SCR4_ADDR       0x0F      /* serial port4the user can define the register address */
-#define REG_DLL4_ADDR       0x08      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM4_ADDR      0x09      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_IIR4_ADDR         0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR         0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR         0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR         0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR         0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR         0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR         0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR         0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR         0x09      /* Baud rate divisor latch high 8-bit byte address */
 
 
 
 /* CH438serial port5 register address */
 
-#define REG_RBR5_ADDR       0x18      /* serial port5receive buffer register address */
-#define REG_THR5_ADDR       0x18      /* serial port5send hold register address */
-#define REG_IER5_ADDR         0x19      /* serial port5interrupt enable register address */
+#define REG_RBR5_ADDR          0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR          0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR          0x19      /* serial port5interrupt enable register address */
 #define REG_IIR5_ADDR          0x1A      /* serial port5interrupt identifies register address */
-#define REG_FCR5_ADDR       0x1A      /* serial port5FIFO controls register address */
-#define REG_LCR5_ADDR       0x1B      /* serial port5circuit control register address */
-#define REG_MCR5_ADDR      0x1C      /* serial port5MODEM controls register address */
-#define REG_LSR5_ADDR       0x1D      /* serial port5line status register address */
-#define REG_MSR5_ADDR      0x1E      /* serial port5address of MODEM status register */
-#define REG_SCR5_ADDR       0x1F      /* serial port5the user can define the register address */
-#define REG_DLL5_ADDR       0x18      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM5_ADDR      0x19      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_FCR5_ADDR          0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR          0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR          0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR          0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR          0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR          0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR          0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR          0x19      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port6 register address */
 
-#define REG_RBR6_ADDR       0x28      /* serial port6receive buffer register address */
-#define REG_THR6_ADDR       0x28      /* serial port6send hold register address */
-#define REG_IER6_ADDR         0x29      /* serial port6interrupt enable register address */
+#define REG_RBR6_ADDR          0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR          0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR          0x29      /* serial port6interrupt enable register address */
 #define REG_IIR6_ADDR          0x2A      /* serial port6interrupt identifies register address */
-#define REG_FCR6_ADDR       0x2A      /* serial port6FIFO controls register address */
-#define REG_LCR6_ADDR       0x2B      /* serial port6circuit control register address */
-#define REG_MCR6_ADDR      0x2C      /* serial port6MODEM controls register address */
-#define REG_LSR6_ADDR       0x2D      /* serial port6line status register address */
-#define REG_MSR6_ADDR      0x2E      /* serial port6address of MODEM status register */
-#define REG_SCR6_ADDR       0x2F      /* serial port6the user can define the register address */
-#define REG_DLL6_ADDR       0x28      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM6_ADDR      0x29      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_FCR6_ADDR          0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR          0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR          0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR          0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR          0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR          0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR          0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR          0x29      /* Baud rate divisor latch high 8-bit byte address */
 
 
 /* CH438serial port7 register address */
 
-#define REG_RBR7_ADDR       0x38      /* serial port7receive buffer register address */
-#define REG_THR7_ADDR       0x38      /* serial port7send hold register address */
-#define REG_IER7_ADDR         0x39      /* serial port7interrupt enable register address */
+#define REG_RBR7_ADDR          0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR          0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR          0x39      /* serial port7interrupt enable register address */
 #define REG_IIR7_ADDR          0x3A      /* serial port7interrupt identifies register address */
-#define REG_FCR7_ADDR       0x3A      /* serial port7FIFO controls register address */
-#define REG_LCR7_ADDR       0x3B      /* serial port7circuit control register address */
-#define REG_MCR7_ADDR      0x3C      /* serial port7MODEM controls register address */
-#define REG_LSR7_ADDR       0x3D      /* serial port7line status register address */
-#define REG_MSR7_ADDR      0x3E      /* serial port7address of MODEM status register */
-#define REG_SCR7_ADDR       0x3F      /* serial port7the user can define the register address */
-#define REG_DLL7_ADDR       0x38      /* Baud rate divisor latch low 8-bit byte address */
-#define REG_DLM7_ADDR      0x39      /* Baud rate divisor latch high 8-bit byte address */
+#define REG_FCR7_ADDR          0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR          0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR          0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR          0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR          0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR          0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR          0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR          0x39      /* Baud rate divisor latch high 8-bit byte address */
 
 
-#define REG_SSR_ADDR        0x4F       /* pecial status register address */
+#define REG_SSR_ADDR           0x4F       /* pecial status register address */
 
 
 /* IER register bit */
 
-#define BIT_IER_RESET                0x80      /* The bit is 1 soft reset serial port */
-#define BIT_IER_LOWPOWER    0x40      /* The bit is 1 close serial port internal reference clock */
-#define BIT_IER_SLP                     0x20      /* serial port0 is SLP, 1 close clock vibrator  */
-#define BIT_IER1_CK2X                0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
-#define BIT_IER_IEMODEM         0x08      /* The bit is 1 allows MODEM input status to interrupt */
-#define BIT_IER_IELINES             0x04      /* The bit is 1 allow receiving line status to be interrupted */
-#define BIT_IER_IETHRE              0x02      /* The bit is 1 allows the send hold register to break in mid-air */
-#define BIT_IER_IERECV               0x01      /* The bit is 1 allows receiving data interrupts */
+#define BIT_IER_RESET          0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER       0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP            0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X          0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM        0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES        0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE         0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV         0x01      /* The bit is 1 allows receiving data interrupts */
 
 /* IIR register bit */
 
-#define BIT_IIR_FIFOENS1    0x80
-#define BIT_IIR_FIFOENS0    0x40      /* The two is 1 said use FIFO */
+#define BIT_IIR_FIFOENS1       0x80
+#define BIT_IIR_FIFOENS0       0x40      /* The two is 1 said use FIFO */
 
 /* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
 1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
-#define BIT_IIR_IID3        0x08
-#define BIT_IIR_IID2        0x04
-#define BIT_IIR_IID1        0x02
-#define BIT_IIR_NOINT  0x01
+#define BIT_IIR_IID3           0x08
+#define BIT_IIR_IID2           0x04
+#define BIT_IIR_IID1           0x02
+#define BIT_IIR_NOINT          0x01
 
 /* FCR register bit */
 
 /* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
-#define BIT_FCR_RECVTG1     0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
-#define BIT_FCR_RECVTG0     0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG1        0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0        0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
 
-#define BIT_FCR_TFIFORST    0x04      /* The bit is 1 empty the data sent in FIFO */
-#define BIT_FCR_RFIFORST    0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_TFIFORST       0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST       0x02      /* The bit is 1 empty the data sent in FIFO */
 #define BIT_FCR_FIFOEN         0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
 
 /* LCR register bit */
 
-#define BIT_LCR_DLAB              0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
-#define BIT_LCR_BREAKEN     0x40      /* 1 forces a BREAK line interval*/
+#define BIT_LCR_DLAB            0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN         0x40      /* 1 forces a BREAK line interval*/
 
 /* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
-#define BIT_LCR_PARMODE1    0x20      /* Sets the parity bit format */
-#define BIT_LCR_PARMODE0    0x10      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE1        0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0        0x10      /* Sets the parity bit format */
 
-#define BIT_LCR_PAREN         0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
-#define BIT_LCR_STOPBIT     0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+#define BIT_LCR_PAREN           0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT         0x04      /* If is 1, then two stop bits, is 0, a stop bit */
 
 /* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
-#define BIT_LCR_WORDSZ1     0x02      /* Set the word length length */
-#define BIT_LCR_WORDSZ0     0x01
+#define BIT_LCR_WORDSZ1         0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0         0x01
 
 /* MCR register bit */
 
-#define BIT_MCR_AFE            0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
-#define BIT_MCR_LOOP        0x10      /* Is the test mode of 1 enabling internal loop */
-#define BIT_MCR_OUT2        0x08      /* 1 Allows an interrupt request for the serial port output  */
-#define BIT_MCR_OUT1        0x04      /* The MODEM control bit defined for the user */
-#define BIT_MCR_RTS            0x02      /* The bit is 1 RTS pin  output  effective  */
-#define BIT_MCR_DTR           0x01      /* The bit is 1 DTR pin  output  effective  */
+#define BIT_MCR_AFE             0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP            0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2            0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1            0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS             0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR             0x01      /* The bit is 1 DTR pin  output  effective  */
 
 /* LSR register bit */
 
-#define BIT_LSR_RFIFOERR    0x80      /* 1 said There is at least one error in receiving FIFO */
-#define BIT_LSR_TEMT             0x40      /* 1 said THR and TSR are empty */
-#define BIT_LSR_THRE              0x20      /* 1 said THR is empty*/
-#define BIT_LSR_BREAKINT    0x10      /* The bit is 1 said the BREAK line interval was detected*/
-#define BIT_LSR_FRAMEERR   0x08      /* The bit is 1 said error reading data frame */
-#define BIT_LSR_PARERR         0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_RFIFOERR        0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_TEMT            0x40      /* 1 said THR and TSR are empty */
+#define BIT_LSR_THRE            0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT        0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR        0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR          0x04      /* The bit is 1 said parity error */
 #define BIT_LSR_OVERR           0x02      /*  1 said receive FIFO buffer overflow */
-#define BIT_LSR_DATARDY       0x01      /* The bit is 1 said receive data received in FIFO */
+#define BIT_LSR_DATARDY         0x01      /* The bit is 1 said receive data received in FIFO */
 
 /* MSR register bit */
 
-#define BIT_MSR_DCD         0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_DCD             0x80      /* The bit is 1 said DCD pin  effective  */
 #define BIT_MSR_RI              0x40      /* The bit is 1 said RI pin  effective  */
-#define BIT_MSR_DSR         0x20      /* The bit is 1 said DSR pin  effective  */
-#define BIT_MSR_CTS          0x10      /* The bit is 1 said CTS pin  effective  */
-#define BIT_MSR_DDCD      0x08      /* The bit is 1 said DCD pin The input state has changed */
-#define BIT_MSR_TERI        0x04      /* The bit is 1 said RI pin The input state has changed */
-#define BIT_MSR_DDSR      0x02      /* The bit is 1 said DSR pin The input state has changed */
-#define BIT_MSR_DCTS       0x01      /* The bit is 1 said CTS pin The input state has changed */
+#define BIT_MSR_DSR             0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS             0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD            0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI            0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR            0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS            0x01      /* The bit is 1 said CTS pin The input state has changed */
 
 /* Interrupt status code */
 
-#define INT_NOINT                          0x01      /* There is no interruption */
-#define INT_THR_EMPTY               0x02      /* THR empty interruption */
+#define INT_NOINT               0x01      /* There is no interruption */
+#define INT_THR_EMPTY           0x02      /* THR empty interruption */
 #define INT_RCV_OVERTIME        0x0C      /* Receive timeout interrupt */
-#define INT_RCV_SUCCESS          0x04      /* Interrupts are available to receive data */
-#define INT_RCV_LINES                  0x06      /* Receiving line status interrupted */
-#define INT_MODEM_CHANGE    0x00      /* MODEM input changes interrupt */
+#define INT_RCV_SUCCESS         0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES           0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE        0x00      /* MODEM input changes interrupt */
 
-#define CH438_IIR_FIFOS_ENABLED 0xC0  /* use FIFO */
+#define CH438_IIR_FIFOS_ENABLED 0xC0      /* use FIFO */
 
 
 #define Fpclk 1843200         /* Define the internal clock frequency  */
 
+#define CH438_RECV_TIMEOUT 1000000 * 1000
+
 void Set485Input(uint8 ch_no);
 void Set485Output(uint8 ch_no);
 

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/drv_io_config.h

@@ -50,6 +50,34 @@ enum HS_GPIO_CONFIG
     GPIO_ALLOC_START /* index of gpio driver start */
 };
 
+#ifdef BSP_USING_CH438
+#define FPIOA_CH438_ALE   12
+#define FPIOA_CH438_NWR   13
+#define FPIOA_CH438_NRD   14
+#define FPIOA_CH438_D0    15
+#define FPIOA_CH438_D1    16
+#define FPIOA_CH438_D2    17
+#define FPIOA_CH438_D3    18
+#define FPIOA_CH438_D4    19
+#define FPIOA_CH438_D5    20
+#define FPIOA_CH438_D6    21
+#define FPIOA_CH438_D7    22
+#define FPIOA_CH438_INT   23
+
+#define BSP_CH438_ALE_PIN   24
+#define BSP_CH438_NWR_PIN   25
+#define BSP_CH438_NRD_PIN   26
+#define BSP_CH438_D0_PIN    27
+#define BSP_CH438_D1_PIN    28
+#define BSP_CH438_D2_PIN    29
+#define BSP_CH438_D3_PIN    30
+#define BSP_CH438_D4_PIN    31
+#define BSP_CH438_D5_PIN    32
+#define BSP_CH438_D6_PIN    33
+#define BSP_CH438_D7_PIN    34
+#define BSP_CH438_INT_PIN   35
+#endif
+
 extern int IoConfigInit(void);
 
 #endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Kconfig

@@ -13,10 +13,30 @@ menuconfig BSP_USING_UART_HS
             default "uart0_dev0"   
     endif
 
+menuconfig BSP_USING_UART1
+    bool "Enable UART1"
+    default n
+    if BSP_USING_UART1
+        config BSP_UART1_TXD_PIN
+            int "uart1 TXD pin number"
+            default 19
+        config BSP_UART1_RXD_PIN
+            int "uart1 RXD pin number"
+            default 18
+        config SERIAL_BUS_NAME_1
+            string "serial bus 1 name"
+            default "uart1"
+        config SERIAL_DRV_NAME_1
+            string "serial bus 1 driver name"
+            default "uart1_drv"
+        config SERIAL_1_DEVICE_NAME_0
+                string "serial bus 1 device 0 name"
+                default "uart1_dev1"   
+    endif
 
 menuconfig BSP_USING_UART2
     bool "Enable UART2"
-    default y
+    default n
     if BSP_USING_UART2
         config BSP_UART2_TXD_PIN
             int "uart2 TXD pin number"
@@ -37,7 +57,7 @@ menuconfig BSP_USING_UART2
 
 menuconfig BSP_USING_UART3
     bool "Enable UART3"
-    default y
+    default n
     if BSP_USING_UART3
         config BSP_UART3_TXD_PIN
             int "uart3 TXD pin number"

Ubiquitous/XiZi/board/kd233/Kconfig

@@ -44,20 +44,6 @@ menu "kd233 feature"
                 default 0x80100000
         endmenu
 
-        menu "config hardware resources for connection"
-            if CONNECTION_INDUSTRIAL_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/uart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/uart3_dev3"
-            endif
-
-        endmenu
-
         menu "config board peripheral"
             config MOUNT_SDCARD
                 bool "mount cd card"

Ubiquitous/XiZi/board/kd233/board.c

@@ -78,11 +78,13 @@ int MountSDCard(void)
 
     if (NONE == SpiSdInit(spi_bus, SPI_1_DEVICE_NAME_0, SPI_1_DRV_NAME, SPI_SD_NAME)) {
         KPrintf("MountSDCard SpiSdInit error!\n");
-        return 0;
+        return -1;
     }
     
-    if (EOK == MountFilesystem(SPI_BUS_NAME_1, SPI_SD_NAME, SPI_1_DRV_NAME, FSTYPE_FATFS, "/"))
+    if (EOK == MountFilesystem(SPI_BUS_NAME_1, SPI_SD_NAME, SPI_1_DRV_NAME, FSTYPE_FATFS, "/")) {
         KPrintf("SPI SD card fatfs mounted\n");
+        return -1;
+    }
 
     return 0;
 }

Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/ch438/connect_ch438.c

@@ -33,7 +33,7 @@ static void Ch438Irq(void *parameter)
 /**
  * The time delay function.
  *
- * @param microseconds.
+ * @param us.
  */
 static void ImxrtUdelay(uint32 us)
 {

Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/common/pin_mux.c

@@ -1095,6 +1095,37 @@ void BOARD_InitUartPins(void)
         0x10B0u);
 #endif
 
+#ifdef BSP_USING_LPUART3
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
+        0U);
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
+        0U);
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
+        0x10B0u);
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
+        0x10B0u);
+#endif
+
+
+#ifdef BSP_USING_LPUART4
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B1_00_LPUART4_TX,
+        0U);
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B1_01_LPUART4_RX,
+        0U);
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B1_00_LPUART4_TX,
+        0x10B0u);
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B1_01_LPUART4_RX,
+        0x10B0u);
+#endif
+
 #ifdef BSP_USING_LPUART8
     IOMUXC_SetPinMux(
         IOMUXC_GPIO_AD_B1_10_LPUART8_TX,

Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/uart/Kconfig

@@ -28,6 +28,36 @@ config BSP_USING_LPUART2
                 default "uart2_dev2"   
     endif
 
+config BSP_USING_LPUART3
+    bool "Enable LPUART3"
+    default y
+    if BSP_USING_LPUART3
+        config SERIAL_BUS_NAME_3
+            string "serial bus 3 name"
+            default "uart3"
+        config SERIAL_DRV_NAME_3
+            string "serial bus 3 driver name"
+            default "uart3_drv"
+        config SERIAL_3_DEVICE_NAME_0
+                string "serial bus 3 device name"
+                default "uart3_dev3"   
+    endif
+
+config BSP_USING_LPUART4
+    bool "Enable LPUART4"
+    default n
+    if BSP_USING_LPUART4
+        config SERIAL_BUS_NAME_4
+            string "serial bus 4 name"
+            default "uart4"
+        config SERIAL_DRV_NAME_4
+            string "serial bus 4 driver name"
+            default "uart4_drv"
+        config SERIAL_4_DEVICE_NAME_0
+                string "serial bus 4 device name"
+                default "uart4_dev4"   
+    endif
+
 config BSP_USING_LPUART8
     bool "Enable LPUART8"
     default n

Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/uart/connect_uart.c

@@ -66,6 +66,40 @@ void LPUART2_IRQHandler(int irqn, void *arg)
 DECLARE_HW_IRQ(UART2_IRQn, LPUART2_IRQHandler, NONE);
 #endif
 
+#ifdef BSP_USING_LPUART3
+struct SerialBus serial_bus_3;
+struct SerialDriver serial_driver_3;
+struct SerialHardwareDevice serial_device_3;
+
+void LPUART3_IRQHandler(int irqn, void* arg)
+{
+
+    DisableIRQ(LPUART3_IRQn);
+
+    UartIsr(&serial_bus_3, &serial_driver_3, &serial_device_3);
+    EnableIRQ(LPUART3_IRQn);
+
+}
+DECLARE_HW_IRQ(LPUART3_IRQn, LPUART3_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_LPUART4
+struct SerialBus serial_bus_4;
+struct SerialDriver serial_driver_4;
+struct SerialHardwareDevice serial_device_4;
+
+void LPUART4_IRQHandler(int irqn, void* arg)
+{
+
+    DisableIRQ(LPUART4_IRQn);
+
+    UartIsr(&serial_bus_4, &serial_driver_4, &serial_device_4);
+    EnableIRQ(LPUART4_IRQn);
+
+}
+DECLARE_HW_IRQ(LPUART4_IRQn, LPUART4_IRQHandler, NONE);
+#endif
+
 #ifdef BSP_USING_LPUART8
 struct SerialBus serial_bus_8;
 struct SerialDriver serial_driver_8;
@@ -443,6 +477,72 @@ int Imxrt1052HwUartInit(void)
     }  
 #endif
 
+#ifdef BSP_USING_LPUART3
+    static struct SerialCfgParam serial_cfg_3;
+    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
+
+    static struct SerialDevParam serial_dev_param_3;
+    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
+
+    serial_driver_3.drv_done = &drv_done;
+    serial_driver_3.configure = &SerialDrvConfigure;
+    serial_device_3.hwdev_done = &hwdev_done;
+
+    serial_cfg_3.data_cfg = data_cfg_init;
+
+    serial_cfg_3.hw_cfg.private_data = (void*)LPUART3;
+    serial_cfg_3.hw_cfg.serial_irq_interrupt = LPUART3_IRQn;
+    serial_driver_3.private_data = (void*)&serial_cfg_3;
+
+    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_3.haldev.private_data = (void*)&serial_dev_param_3;
+
+    ret = BoardSerialBusInit(&serial_bus_3, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
+    if (EOK != ret) {
+        KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_3, (void*)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
+        return ERROR;
+    }
+#endif
+
+#ifdef BSP_USING_LPUART4
+    static struct SerialCfgParam serial_cfg_4;
+    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
+
+    static struct SerialDevParam serial_dev_param_4;
+    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
+
+    serial_driver_4.drv_done = &drv_done;
+    serial_driver_4.configure = &SerialDrvConfigure;
+    serial_device_4.hwdev_done = &hwdev_done;
+
+    serial_cfg_4.data_cfg = data_cfg_init;
+
+    serial_cfg_4.hw_cfg.private_data = (void*)LPUART4;
+    serial_cfg_4.hw_cfg.serial_irq_interrupt = LPUART4_IRQn;
+    serial_driver_4.private_data = (void*)&serial_cfg_4;
+
+    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_4.haldev.private_data = (void*)&serial_dev_param_4;
+
+    ret = BoardSerialBusInit(&serial_bus_4, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
+    if (EOK != ret) {
+        KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_4, (void*)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
+        return ERROR;
+    }
+#endif
+
 #ifdef BSP_USING_LPUART8
     static struct SerialCfgParam serial_cfg_8;
     memset(&serial_cfg_8, 0, sizeof(struct SerialCfgParam));

Ubiquitous/XiZi/board/xidatong-riscv64/board.c

@@ -56,8 +56,8 @@ extern void entry(void);
 extern void SecondaryCpuCStart(void);
 extern int IoConfigInit(void);
 extern int HwI2cInit(void);
-extern int HwLcdInit(void);
 extern int HwTouchInit(void);
+extern int HwCh438Init(void);
 
 #if defined(FS_VFS) && defined (MOUNT_SDCARD)
 #include <iot-vfs.h>
@@ -158,12 +158,12 @@ struct InitSequenceDesc _board_init[] =
     { "hw_pin", HwGpioInit },
 	{ "io_config", IoConfigInit },
 #endif
+#ifdef BSP_USING_CH438
+    { "hw_extuart", HwCh438Init },
+#endif
 #ifdef BSP_USING_I2C
     { "hw_i2c", HwI2cInit },
 #endif
-#ifdef BSP_USING_LCD
-	{ "hw_lcd", HwLcdInit },
-#endif
 #ifdef BSP_USING_TOUCH
     {"touch", HwTouchInit },
 #endif
@@ -222,7 +222,4 @@ void HwCpuReset(void)
     sysctl->soft_reset.soft_reset = 1;
     while(RET_TRUE);
 }
-
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),Reboot, HwCpuReset,  reset machine );
-
-

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Kconfig

@@ -1,3 +1,10 @@
+menuconfig BSP_USING_CH438
+bool "Using CH438 device"
+default n
+if BSP_USING_CH438
+source "$BSP_DIR/third_party_driver/ch438/Kconfig"
+endif
+
 menuconfig BSP_USING_DMA
 bool "Using DMA device"
 default y
@@ -32,7 +39,7 @@ endif
 
 menuconfig BSP_USING_PLIC
 bool "Using PLIC device"
-default n
+default y
 if BSP_USING_PLIC
 source "$BSP_DIR/third_party_driver/plic/Kconfig"
 endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/Makefile

@@ -1,5 +1,9 @@
 SRC_FILES := sleep.c
 
+ifeq ($(CONFIG_BSP_USING_CH438),y)
+  SRC_DIR += ch438
+endif
+
 ifeq ($(CONFIG_BSP_USING_DMA),y)
   SRC_DIR += dma
 endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Kconfig

@@ -0,0 +1,39 @@
+config CH438_BUS_NAME
+    string
+    default "extuart"
+
+config CH438_DRIVER_NAME
+    string
+    default "extuart_drv"
+
+config CH438_DEVICE_NAME_0
+    string
+    default "extuart_dev0"
+
+config CH438_DEVICE_NAME_1
+    string
+    default "extuart_dev1"
+
+config CH438_DEVICE_NAME_2
+    string
+    default "extuart_dev2"
+
+config CH438_DEVICE_NAME_3
+    string
+    default "extuart_dev3"
+
+config CH438_DEVICE_NAME_4
+    string
+    default "extuart_dev4"
+
+config CH438_DEVICE_NAME_5
+    string
+    default "extuart_dev5"
+
+config CH438_DEVICE_NAME_6
+    string
+    default "extuart_dev6"
+
+config CH438_DEVICE_NAME_7
+    string
+    default "extuart_dev7"

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_ch438.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/ch438/connect_ch438.c

@@ -0,0 +1,732 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_ch438.c
+* @brief support to register ch438 pointer and function
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-08-24
+*/
+
+#include <connect_ch438.h>
+#include <drv_io_config.h>
+#include <gpiohs.h>
+#include <sleep.h>
+
+static uint8 offset_addr[] = {0x00, 0x10, 0x20, 0x30, 0x08, 0x18, 0x28, 0x38};		/* Offset address of serial port number */
+static uint8 interrupt_num[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
+
+static void CH438SetOutput(void)
+{
+	gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT);
+}
+
+static void CH438SetInput(void)
+{
+	gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP);
+	gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP);
+}
+
+uint8 ReadCH438Data(uint8 addr)
+{
+	uint8 dat = 0;
+
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);	
+
+	CH438SetOutput();
+	usleep(1);
+	
+	if(addr &0x80)	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW);	
+	if(addr &0x40)	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW);	
+	if(addr &0x20)	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW);	
+	if(addr &0x10)	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW);	
+	if(addr &0x08)	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW);	
+	if(addr &0x04)	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW);	
+	if(addr &0x02)	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW);	
+	if(addr &0x01)	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW);	
+		
+	usleep(1);
+
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_LOW);	
+
+	usleep(1);		
+
+	CH438SetInput();
+	usleep(1);
+	
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_LOW);	
+	
+	usleep(1);	
+	
+	dat = 0;
+	if (gpiohs_get_pin(FPIOA_CH438_D7))	dat |= 0x80;
+	if (gpiohs_get_pin(FPIOA_CH438_D6))	dat |= 0x40;
+	if (gpiohs_get_pin(FPIOA_CH438_D5))	dat |= 0x20;
+	if (gpiohs_get_pin(FPIOA_CH438_D4))	dat |= 0x10;
+	if (gpiohs_get_pin(FPIOA_CH438_D3))	dat |= 0x08;
+	if (gpiohs_get_pin(FPIOA_CH438_D2))	dat |= 0x04;
+	if (gpiohs_get_pin(FPIOA_CH438_D1))	dat |= 0x02;
+	if (gpiohs_get_pin(FPIOA_CH438_D0))	dat |= 0x01;
+	
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);	
+
+	usleep(1);
+
+	return dat;
+}
+	
+static void WriteCH438Data(uint8 addr, uint8 dat)
+{
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);	
+
+	CH438SetOutput();
+	usleep(1);	
+	
+	if(addr & 0x80)	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW);	
+	if(addr & 0x40)	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW);	
+	if(addr & 0x20)	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW);	
+	if(addr & 0x10)	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW);	
+	if(addr & 0x08)	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW);	
+	if(addr & 0x04)	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW);	
+	if(addr & 0x02)	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW);	
+	if(addr & 0x01)	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW);	
+	
+	usleep(1);	
+	
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_LOW);	
+	usleep(1);
+	
+	if(dat & 0x80)	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D7, GPIO_PV_LOW);	
+	if(dat & 0x40)	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D6, GPIO_PV_LOW);	
+	if(dat & 0x20)	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D5, GPIO_PV_LOW);	
+	if(dat & 0x10)	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D4, GPIO_PV_LOW);	
+	if(dat & 0x08)	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D3, GPIO_PV_LOW);	
+	if(dat & 0x04)	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D2, GPIO_PV_LOW);	
+	if(dat & 0x02)	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D1, GPIO_PV_LOW);	
+	if(dat & 0x01)	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_HIGH);	else	gpiohs_set_pin(FPIOA_CH438_D0, GPIO_PV_LOW);	
+	
+	usleep(1);	
+
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_LOW);	
+
+	usleep(1);	
+	
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);	
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);	
+	
+	usleep(1);	
+
+	CH438SetInput();
+
+	return;
+}
+
+static void WriteCH438Block(uint8 mAddr, uint8 mLen, uint8 *mBuf)   
+{
+    while (mLen--) {
+		WriteCH438Data(mAddr, *mBuf++);
+	}
+}
+
+void CH438UartSend(uint8 ext_uart_no, uint8 *Data, uint8 Num)
+{
+	uint8 REG_LSR_ADDR,REG_THR_ADDR;
+	
+	REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+			
+   while (1) {
+       while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0);
+
+       if (Num <= 128) {
+           WriteCH438Block(REG_THR_ADDR, Num, Data);
+           break;
+       } else {
+           WriteCH438Block(REG_THR_ADDR, 128, Data);
+           Num -= 128;
+           Data += 128;
+       }
+   }
+}
+
+uint8 CH438UartRecv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
+{
+    x_size_t rcv_num = 0;
+	uint8 dat = 0;
+	uint8 REG_LSR_ADDR, REG_RBR_ADDR;
+	uint8 *read_buffer;
+	x_size_t buffer_index = 0;
+	
+	REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+
+	read_buffer = buf;
+			
+	while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0);
+
+    while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) {
+		dat = ReadCH438Data(REG_RBR_ADDR);
+
+		*read_buffer = dat;
+		read_buffer++;
+		buffer_index++;
+
+		if (BUFFSIZE == buffer_index) {
+			buffer_index = 0;
+			read_buffer = buf;
+		}
+			
+        rcv_num = rcv_num + 1;
+		--size;
+    }
+
+    return rcv_num;
+}
+
+void CH438PortInit(uint8 ext_uart_no, uint32 BaudRate)
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);             /* Reset the serial port */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    div = (Fpclk >> 4) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */
+
+    WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0);
+
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV);
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST);
+}
+
+void CH438PortInitParityCheck(uint8 ext_uart_no, uint32	BaudRate)
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    div = (Fpclk >> 4) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 |  BIT_FCR_FIFOEN);/* Set FIFO mode */
+
+    WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0);
+
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV);
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST);
+}
+
+void CH438PortDisable(uint8 ext_uart_no, uint32 BaudRate)
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);             /* Reset the serial port */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    div = (Fpclk >> 4) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN );/* Set FIFO mode */
+
+    WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0);
+
+    WriteCH438Data(REG_IER_ADDR, 0);
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST);
+}
+
+void CH438Port6Init(uint8 ext_uart_no, uint32 BaudRate)
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    //div = ( 22118400 >> 4 ) / BaudRate;
+	div = ( 44236800 >> 4 ) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */
+
+    WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0);
+
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV | BIT_IER1_CK2X);
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST);
+}
+
+static uint32 Ch438Configure(struct SerialCfgParam *ext_serial_cfg)
+{
+	NULL_PARAM_CHECK(ext_serial_cfg);
+
+	switch (ext_serial_cfg->data_cfg.port_configure)
+	{
+		case PORT_CFG_INIT:
+			CH438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;
+		case PORT_CFG_PARITY_CHECK:
+			CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;
+		case PORT_CFG_DISABLE:
+			CH438PortDisable(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;		
+		case PORT_CFG_DIV:
+			CH438Port6Init(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;	
+		default:
+			KPrintf("Ch438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure);
+			return ERROR;
+			break;
+	}
+
+	return EOK;
+}
+
+static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg)
+{
+	NULL_PARAM_CHECK(serial_drv);
+
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);
+
+	return Ch438Configure(ext_serial_cfg);
+}
+
+static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+	struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+    case OPE_INT:
+        ret = Ch438Init(serial_drv, ext_serial_cfg);
+        break;
+    default:
+        break;
+    }
+
+    return ret;
+}
+
+static uint32 Ch438WriteData(void *dev, struct BusBlockWriteParam *write_param)
+{
+	NULL_PARAM_CHECK(dev);
+	NULL_PARAM_CHECK(write_param);
+
+	struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
+	struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+	CH438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
+
+	return EOK;
+}
+
+static uint32 Ch438ReadData(void *dev, struct BusBlockReadParam *read_param)
+{
+	NULL_PARAM_CHECK(dev);
+	NULL_PARAM_CHECK(read_param);
+
+	uint32 rcv_cnt = 0;
+	uint8 rcv_num = 0;
+	uint8 gInterruptStatus;
+	uint8 InterruptStatus;
+	static uint8 dat;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	uint8 REG_LSR_ADDR;
+	uint8 REG_MSR_ADDR;
+
+	struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
+	struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->private_data;
+
+	do {
+		rcv_cnt++;
+
+		if (rcv_cnt > CH438_RECV_TIMEOUT) {
+			break;
+		}
+
+		dat = ReadCH438Data(REG_IER0_ADDR);
+		dat = ReadCH438Data(REG_IIR0_ADDR);
+		dat = ReadCH438Data(REG_LCR0_ADDR);
+		dat = ReadCH438Data(REG_MCR0_ADDR);
+		dat = ReadCH438Data(REG_LSR0_ADDR);
+		dat = ReadCH438Data(REG_MSR0_ADDR);
+		dat = ReadCH438Data(REG_FCR0_ADDR);
+		gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
+		
+		if (gInterruptStatus) { 
+			if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) {   /* Detect which serial port is interrupted */ 
+				REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
+				REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
+				REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
+				REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
+				REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
+				REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
+				REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
+				REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
+				REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
+				REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
+				REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
+
+				/* The interrupted state of a read serial port */	
+				InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f;
+							
+				switch( InterruptStatus )
+				{
+					case INT_NOINT:	
+						break;
+					case INT_THR_EMPTY:					
+						break;
+					case INT_RCV_OVERTIME:	/* Receiving timeout interruption, triggered when no further data is available four data times after receiving a frame*/
+					case INT_RCV_SUCCESS:	/* Interrupts are available to receive data */
+						rcv_num = CH438UartRecv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
+						read_param->read_length = rcv_num;
+						break;
+					case INT_RCV_LINES:		/* Receiving line status interrupted */
+						ReadCH438Data(REG_LSR_ADDR);
+						break;
+					case INT_MODEM_CHANGE:	/* MODEM input changes interrupt */
+						ReadCH438Data(REG_MSR_ADDR);
+						break;
+					default:
+						break;
+				}
+			}
+		}
+	} while (0 == (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]));
+
+	return rcv_num;
+}
+
+static const struct SerialDevDone dev_done = 
+{
+    NONE,
+    NONE,
+    Ch438WriteData,
+    Ch438ReadData,
+};
+
+static void Ch438InitDefault(struct SerialDriver *serial_drv)
+{
+	CH438SetOutput();
+
+ 	gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT);
+	gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT);
+	// gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
+
+	// gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
+	// gpiohs_set_pin_edge(FPIOA_CH438_INT, GPIO_PE_FALLING);
+	// gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, NONE);
+	
+	gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);
+	gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);
+	gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);
+}
+
+static uint32 Ch438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name)
+{
+	x_err_t ret = EOK;
+	serial_dev->dev_done = &dev_done;
+	serial_dev->ext_serial_mode = RET_TRUE;
+    ret = SerialDeviceRegister(serial_dev, NONE, dev_name);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+    ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+	return ret;
+}
+
+int HwCh438Init(void)
+{
+    static struct SerialBus serial_bus;
+    static struct SerialDriver serial_drv;
+
+    x_err_t ret = EOK;
+    
+    ret = SerialBusInit(&serial_bus, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Serial bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    serial_drv.configure = &Ch438DrvConfigure;
+    ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Serial driver init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Serial driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_0;
+	static struct SerialDevParam dev_param_0;
+	dev_param_0.ext_uart_no = 0;
+	serial_dev_0.private_data = (void *)&dev_param_0;
+	ret = Ch438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_1;
+	static struct SerialDevParam dev_param_1;
+	dev_param_1.ext_uart_no = 1;
+	serial_dev_1.private_data = (void *)&dev_param_1;
+	ret = Ch438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_2;
+	static struct SerialDevParam dev_param_2;
+	dev_param_2.ext_uart_no = 2;
+	serial_dev_2.private_data = (void *)&dev_param_2;
+	ret = Ch438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_3;
+	static struct SerialDevParam dev_param_3;
+	dev_param_3.ext_uart_no = 3;
+	serial_dev_3.private_data = (void *)&dev_param_3;
+	ret = Ch438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_4;
+	static struct SerialDevParam dev_param_4;
+	dev_param_4.ext_uart_no = 4;
+	serial_dev_4.private_data = (void *)&dev_param_4;
+	ret = Ch438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_5;
+	static struct SerialDevParam dev_param_5;
+	dev_param_5.ext_uart_no = 5;
+	serial_dev_5.private_data = (void *)&dev_param_5;
+	ret = Ch438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_6;
+	static struct SerialDevParam dev_param_6;
+	dev_param_6.ext_uart_no = 6;
+	serial_dev_6.private_data = (void *)&dev_param_6;
+	ret = Ch438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_7;
+	static struct SerialDevParam dev_param_7;
+	dev_param_7.ext_uart_no = 7;
+	serial_dev_7.private_data = (void *)&dev_param_7;
+	ret = Ch438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7);
+    if (ret != EOK) {
+        KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	Ch438InitDefault(&serial_drv);
+
+    return ret;
+}

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/gpio/drv_io_config.c

@@ -11,7 +11,7 @@
 /**
 * @file drv_io_config.c
 * @brief support xidatong-riscv64-board io configure
-* @version 1.0 
+* @version 2.0 
 * @author AIIT XUOS Lab
 * @date 2022-07-25
 */
@@ -79,7 +79,22 @@ static struct io_config
     IOCONFIG(BSP_I2C_SCL, FUNC_GPIO4),
 #endif
 #ifdef BSP_USING_TOUCH
-    IOCONFIG(BSP_TOUCH_TP_INT, HS_GPIO(FPIOA_TOUCH_TP_INT))
+    IOCONFIG(BSP_TOUCH_TP_INT, HS_GPIO(FPIOA_TOUCH_TP_INT)),
+#endif
+
+#ifdef BSP_USING_CH438
+    IOCONFIG(BSP_CH438_ALE_PIN,  HS_GPIO(FPIOA_CH438_ALE)),      
+    IOCONFIG(BSP_CH438_NWR_PIN,  HS_GPIO(FPIOA_CH438_NWR)),      
+    IOCONFIG(BSP_CH438_NRD_PIN,  HS_GPIO(FPIOA_CH438_NRD)),      
+    IOCONFIG(BSP_CH438_INT_PIN,  HS_GPIO(FPIOA_CH438_INT)),      
+    IOCONFIG(BSP_CH438_D0_PIN,  HS_GPIO(FPIOA_CH438_D0)),      
+    IOCONFIG(BSP_CH438_D1_PIN,  HS_GPIO(FPIOA_CH438_D1)),      
+    IOCONFIG(BSP_CH438_D2_PIN,  HS_GPIO(FPIOA_CH438_D2)),      
+    IOCONFIG(BSP_CH438_D3_PIN,  HS_GPIO(FPIOA_CH438_D3)),      
+    IOCONFIG(BSP_CH438_D4_PIN,  HS_GPIO(FPIOA_CH438_D4)),      
+    IOCONFIG(BSP_CH438_D5_PIN,  HS_GPIO(FPIOA_CH438_D5)),      
+    IOCONFIG(BSP_CH438_D6_PIN,  HS_GPIO(FPIOA_CH438_D6)),      
+    IOCONFIG(BSP_CH438_D7_PIN,  HS_GPIO(FPIOA_CH438_D7))
 #endif
 };
 
@@ -97,13 +112,9 @@ static int PrintIoConfig()
     KPrintf("└───────┴────────────────────────┘\n");
     return 0;
 }
-
-
-
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
                                                 io,PrintIoConfig,print io config);
 
-
 int IoConfigInit(void)
 {
     int count = sizeof(io_config) / sizeof(io_config[0]);

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_ch438.h

@@ -0,0 +1,257 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_ch438.h
+* @brief define xidatong-riscv64-board ch438 function and struct
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-08-26
+*/
+
+#ifndef CONNECT_CH438_H
+#define CONNECT_CH438_H
+
+#include <device.h>
+
+#define BUFFSIZE	255
+
+/******************************************************************************************/
+
+/* CH438serial port0 register address */
+
+#define REG_RBR0_ADDR         0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR         0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR         0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR         0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR         0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR         0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR         0x04      /* serial port0MODEM controls register address */
+#define REG_LSR0_ADDR         0x05      /* serial port0line status register address */
+#define REG_MSR0_ADDR         0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR         0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR         0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR         0x01      /* Baud rate divisor latch high 8-bit byte address */
+
+/* CH438serial port1 register address */
+
+#define REG_RBR1_ADDR         0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR         0x10      /* serial port1send hold register address */
+#define REG_IER1_ADDR         0x11      /* serial port1interrupt enable register address */
+#define REG_IIR1_ADDR         0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR         0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR         0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR         0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR         0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR         0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR         0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR         0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR         0x11      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port2 register address */
+
+#define REG_RBR2_ADDR         0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR         0x20      /* serial port2send hold register address */
+#define REG_IER2_ADDR         0x21      /* serial port2interrupt enable register address */
+#define REG_IIR2_ADDR         0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR         0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR         0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR         0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR         0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR         0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR         0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR         0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR         0x21      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port3 register address */
+
+#define REG_RBR3_ADDR         0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR         0x30      /* serial port3send hold register address */
+#define REG_IER3_ADDR         0x31      /* serial port3interrupt enable register address */
+#define REG_IIR3_ADDR         0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR         0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR         0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR         0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR         0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR         0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR         0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR         0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR         0x31      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port4 register address */
+
+#define REG_RBR4_ADDR         0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR         0x08      /* serial port4send hold register address */
+#define REG_IER4_ADDR         0x09      /* serial port4interrupt enable register address */
+#define REG_IIR4_ADDR         0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR         0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR         0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR         0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR         0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR         0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR         0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR         0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR         0x09      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port5 register address */
+
+#define REG_RBR5_ADDR          0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR          0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR          0x19      /* serial port5interrupt enable register address */
+#define REG_IIR5_ADDR          0x1A      /* serial port5interrupt identifies register address */
+#define REG_FCR5_ADDR          0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR          0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR          0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR          0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR          0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR          0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR          0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR          0x19      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port6 register address */
+
+#define REG_RBR6_ADDR          0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR          0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR          0x29      /* serial port6interrupt enable register address */
+#define REG_IIR6_ADDR          0x2A      /* serial port6interrupt identifies register address */
+#define REG_FCR6_ADDR          0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR          0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR          0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR          0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR          0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR          0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR          0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR          0x29      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port7 register address */
+
+#define REG_RBR7_ADDR          0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR          0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR          0x39      /* serial port7interrupt enable register address */
+#define REG_IIR7_ADDR          0x3A      /* serial port7interrupt identifies register address */
+#define REG_FCR7_ADDR          0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR          0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR          0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR          0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR          0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR          0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR          0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR          0x39      /* Baud rate divisor latch high 8-bit byte address */
+
+
+#define REG_SSR_ADDR           0x4F       /* pecial status register address */
+
+
+/* IER register bit */
+
+#define BIT_IER_RESET          0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER       0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP            0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X          0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM        0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES        0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE         0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV         0x01      /* The bit is 1 allows receiving data interrupts */
+
+/* IIR register bit */
+
+#define BIT_IIR_FIFOENS1       0x80
+#define BIT_IIR_FIFOENS0       0x40      /* The two is 1 said use FIFO */
+
+/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
+1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
+#define BIT_IIR_IID3           0x08
+#define BIT_IIR_IID2           0x04
+#define BIT_IIR_IID1           0x02
+#define BIT_IIR_NOINT          0x01
+
+/* FCR register bit */
+
+/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
+#define BIT_FCR_RECVTG1        0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0        0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+
+#define BIT_FCR_TFIFORST       0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST       0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_FIFOEN         0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
+
+/* LCR register bit */
+
+#define BIT_LCR_DLAB            0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN         0x40      /* 1 forces a BREAK line interval*/
+
+/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
+#define BIT_LCR_PARMODE1        0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0        0x10      /* Sets the parity bit format */
+
+#define BIT_LCR_PAREN           0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT         0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+
+/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
+#define BIT_LCR_WORDSZ1         0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0         0x01
+
+/* MCR register bit */
+
+#define BIT_MCR_AFE             0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP            0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2            0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1            0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS             0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR             0x01      /* The bit is 1 DTR pin  output  effective  */
+
+/* LSR register bit */
+
+#define BIT_LSR_RFIFOERR        0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_TEMT            0x40      /* 1 said THR and TSR are empty */
+#define BIT_LSR_THRE            0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT        0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR        0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR          0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_OVERR           0x02      /*  1 said receive FIFO buffer overflow */
+#define BIT_LSR_DATARDY         0x01      /* The bit is 1 said receive data received in FIFO */
+
+/* MSR register bit */
+
+#define BIT_MSR_DCD             0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_RI              0x40      /* The bit is 1 said RI pin  effective  */
+#define BIT_MSR_DSR             0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS             0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD            0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI            0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR            0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS            0x01      /* The bit is 1 said CTS pin The input state has changed */
+
+/* Interrupt status code */
+
+#define INT_NOINT               0x01      /* There is no interruption */
+#define INT_THR_EMPTY           0x02      /* THR empty interruption */
+#define INT_RCV_OVERTIME        0x0C      /* Receive timeout interrupt */
+#define INT_RCV_SUCCESS         0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES           0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE        0x00      /* MODEM input changes interrupt */
+
+#define CH438_IIR_FIFOS_ENABLED 0xC0      /* use FIFO */
+
+#define Fpclk 1843200         /* Define the internal clock frequency  */
+
+#define CH438_RECV_TIMEOUT 1000000 * 1000
+
+#endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_gpio.h

@@ -12,8 +12,8 @@
 
 /**
 * @file connect_gpio.h
-* @brief define kd233-board gpio function and struct
-* @version 1.0 
+* @brief define xidatong-riscv64-board gpio function and struct
+* @version 2.0 
 * @author AIIT XUOS Lab
 * @date 2022-07-25
 */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_hwtimer.h

@@ -1,37 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file connect_hwtimer.h
-* @brief define kd233-board hwtimer function and struct
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef CONNECT_HWTIMER_H
-#define CONNECT_HWTIMER_H
-
-#include <device.h>
-#include "hardware_hwtimer.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int HwTimerInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_i2c.h

@@ -12,8 +12,8 @@
 
 /**
 * @file connect_i2c.h
-* @brief define kd233-board i2c function and struct
-* @version 1.0 
+* @brief define xidatong-riscv64-board i2c function and struct
+* @version 2.0 
 * @author AIIT XUOS Lab
 * @date 2022-07-25
 */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_rtc.h

@@ -1,36 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file connect_rtc.h
-* @brief define kd233-board rtc function and struct
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef CONNECT_RTC_H
-#define CONNECT_RTC_H
-
-#include <device.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int HwRtcInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_spi.h

@@ -1,36 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file connect_spi.h
-* @brief define kd233-board spi function and struct
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef CONNECT_SPI_H
-#define CONNECT_SPI_H
-
-#include <device.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int HwSpiInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_touch.h

@@ -1,8 +1,19 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
 
 /**
 * @file connect_touch.h
 * @brief support xidatong-riscv64 touch function and register to bus framework
-* @version 1.0 
+* @version 2.0 
 * @author AIIT XiUOS Lab
 * @date 2022-04-25
 */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_uart.h

@@ -12,8 +12,8 @@
 
 /**
 * @file connect_uart.h
-* @brief define kd233-board uart function and struct
-* @version 1.0 
+* @brief define xidatong-riscv64-board uart function and struct
+* @version 2.0 
 * @author AIIT XUOS Lab
 * @date 2022-07-25
 */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/connect_wdt.h

@@ -1,36 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file connect_wdt.h
-* @brief define kd233-board wdt function and struct
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef CONNECT_WDT_H
-#define CONNECT_WDT_H
-
-#include <device.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int HwWdtInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/drv_io_config.h

@@ -10,8 +10,8 @@
 
 /**
 * @file drv_io_config.h
-* @brief define kd233-board io configure
-* @version 1.0 
+* @brief define xidatong-riscv64-board io configure
+* @version 2.0 
 * @author AIIT XUOS Lab
 * @date 2022-07-25
 */
@@ -50,6 +50,34 @@ enum HS_GPIO_CONFIG
     GPIO_ALLOC_START /* index of gpio driver start */
 };
 
+#ifdef BSP_USING_CH438
+#define FPIOA_CH438_ALE   12
+#define FPIOA_CH438_NWR   13
+#define FPIOA_CH438_NRD   14
+#define FPIOA_CH438_D0    15
+#define FPIOA_CH438_D1    16
+#define FPIOA_CH438_D2    17
+#define FPIOA_CH438_D3    18
+#define FPIOA_CH438_D4    19
+#define FPIOA_CH438_D5    20
+#define FPIOA_CH438_D6    21
+#define FPIOA_CH438_D7    22
+#define FPIOA_CH438_INT   23
+
+#define BSP_CH438_ALE_PIN   24
+#define BSP_CH438_NWR_PIN   25
+#define BSP_CH438_NRD_PIN   26
+#define BSP_CH438_D0_PIN    27
+#define BSP_CH438_D1_PIN    28
+#define BSP_CH438_D2_PIN    29
+#define BSP_CH438_D3_PIN    30
+#define BSP_CH438_D4_PIN    31
+#define BSP_CH438_D5_PIN    32
+#define BSP_CH438_D6_PIN    33
+#define BSP_CH438_D7_PIN    34
+#define BSP_CH438_INT_PIN   35
+#endif
+
 extern int IoConfigInit(void);
 
 #endif

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/hardware_hwtimer.h

@@ -1,171 +0,0 @@
-/* Copyright 2018 Canaan Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-* @file hardware_hwtimer.h
-* @brief add from Canaan k210 SDK
-*                https://canaan-creative.com/developer
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef __HARDWARE_HWTIMER_H__
-#define __HARDWARE_HWTIMER_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* clang-format off */
-typedef struct _timer_channel
-{
-    /* TIMER_N Load Count Register              (0x00+(N-1)*0x14) */
-    volatile uint32_t load_count;
-    /* TIMER_N Current Value Register           (0x04+(N-1)*0x14) */
-    volatile uint32_t current_value;
-    /* TIMER_N Control Register                 (0x08+(N-1)*0x14) */
-    volatile uint32_t control;
-    /* TIMER_N Interrupt Clear Register         (0x0c+(N-1)*0x14) */
-    volatile uint32_t eoi;
-    /* TIMER_N Interrupt Status Register        (0x10+(N-1)*0x14) */
-    volatile uint32_t intr_stat;
-} __attribute__((packed, aligned(4))) timer_channel_t;
-
-typedef struct _kendryte_timer
-{
-    /* TIMER_N Register                         (0x00-0x4c) */
-    volatile timer_channel_t channel[4];
-    /* reserverd                                (0x50-0x9c) */
-    volatile uint32_t resv1[20];
-    /* TIMER Interrupt Status Register          (0xa0) */
-    volatile uint32_t intr_stat;
-    /* TIMER Interrupt Clear Register           (0xa4) */
-    volatile uint32_t eoi;
-    /* TIMER Raw Interrupt Status Register      (0xa8) */
-    volatile uint32_t raw_intr_stat;
-    /* TIMER Component Version Register         (0xac) */
-    volatile uint32_t comp_version;
-    /* TIMER_N Load Count2 Register             (0xb0-0xbc) */
-    volatile uint32_t load_count2[4];
-} __attribute__((packed, aligned(4))) kendryte_timer_t;
-
-typedef enum _timer_deivce_number
-{
-    TIMER_DEVICE_0,
-    TIMER_DEVICE_1,
-    TIMER_DEVICE_2,
-    TIMER_DEVICE_MAX,
-} timer_device_number_t;
-
-typedef enum _timer_channel_number
-{
-    TIMER_CHANNEL_0,
-    TIMER_CHANNEL_1,
-    TIMER_CHANNEL_2,
-    TIMER_CHANNEL_3,
-    TIMER_CHANNEL_MAX,
-} timer_channel_number_t;
-
-/* TIMER Control Register */
-#define TIMER_CR_ENABLE             0x00000001
-#define TIMER_CR_MODE_MASK          0x00000002
-#define TIMER_CR_FREE_MODE          0x00000000
-#define TIMER_CR_USER_MODE          0x00000002
-#define TIMER_CR_INTERRUPT_MASK     0x00000004
-#define TIMER_CR_PWM_ENABLE         0x00000008
-/* clang-format on */
-
-extern volatile kendryte_timer_t *const timer[3];
-
-/**
- * @brief       Definitions for the timer callbacks
- */
-typedef int (*timer_callback_t)(void *ctx);
-
-/**
- * @brief       Set timer timeout
- *
- * @param[in]   timer           timer
- * @param[in]   channel         channel
- * @param[in]   nanoseconds     timeout
- *
- * @return      the real timeout
- */
-size_t timer_set_interval(timer_device_number_t timer_number, timer_channel_number_t channel, size_t nanoseconds);
-
-/**
- * @brief       Init timer
- *
- * @param[in]   timer       timer
- */
-void timer_init(timer_device_number_t timer_number);
-
-/**
- * @brief       [DEPRECATED] Set timer timeout function
- *
- * @param[in]   timer           timer
- * @param[in]   channel         channel
- * @param[in]   func            timeout function
- * @param[in]   priority        interrupt priority
- *
- */
-void timer_set_irq(timer_device_number_t timer_number, timer_channel_number_t channel, void(*func)(),  uint32_t priority);
-
-/**
- * @brief      Register timer interrupt user callback function
- *
- * @param[in]  device       The timer device number
- * @param[in]  channel      The channel
- * @param[in]  is_one_shot  Indicates if single shot
- * @param[in]  priority     The priority
- * @param[in]  callback     The callback function
- * @param[in]  ctx          The context
- *
- * @return     result
- *     - 0      Success
- *     - Other  Fail
- */
-int timer_irq_register(timer_device_number_t device, timer_channel_number_t channel, int is_single_shot, uint32_t priority, timer_callback_t callback, void *ctx);
-
-/**
- * @brief      Deregister timer interrupt user callback function
- *
- * @param[in]  device   The timer device number
- * @param[in]  channel  The channel
- *
- * @return     result
- *     - 0      Success
- *     - Other  Fail
- */
-int timer_irq_unregister(timer_device_number_t device, timer_channel_number_t channel);
-
-/**
- * @brief       Enable timer
- *
- * @param[in]   timer       timer
- * @param[in]   channel     channel
- * @param[in]   enable      Enable or disable
- *
- */
-void timer_set_enable(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t enable);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIMER_H__ */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/hardware_rtc.h

@@ -1,443 +0,0 @@
-/* Copyright 2018 Canaan Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-* @file hardware_rtc.h
-* @brief add from Canaan k210 SDK
-*                https://canaan-creative.com/developer
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef __HARDWARE_RTC_H__
-#define __HARDWARE_RTC_H__
-
-#include <stdint.h>
-#include <time.h>
-#include "platform.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief      RTC timer mode
- *
- *             Timer mode selector
- *             | Mode | Description            |
- *             |------|------------------------|
- *             | 0    | Timer pause            |
- *             | 1    | Timer time running     |
- *             | 2    | Timer time setting     |
- */
-typedef enum _rtc_timer_mode_e
-{
-    /* 0: Timer pause */
-    RTC_TIMER_PAUSE,
-    /* 1: Timer time running */
-    RTC_TIMER_RUNNING,
-    /* 2: Timer time setting */
-    RTC_TIMER_SETTING,
-    /* Max count of this enum*/
-    RTC_TIMER_MAX
-} rtc_timer_mode_t;
-
-/*
- * @brief      RTC tick interrupt mode
- *
- *             Tick interrupt mode selector
- *             | Mode | Description            |
- *             |------|------------------------|
- *             | 0    | Interrupt every second |
- *             | 1    | Interrupt every minute |
- *             | 2    | Interrupt every hour   |
- *             | 3    | Interrupt every day    |
- */
-typedef enum _rtc_tick_interrupt_mode_e
-{
-    /* 0: Interrupt every second */
-    RTC_INT_SECOND,
-    /* 1: Interrupt every minute */
-    RTC_INT_MINUTE,
-    /* 2: Interrupt every hour */
-    RTC_INT_HOUR,
-    /* 3: Interrupt every day */
-    RTC_INT_DAY,
-    /* Max count of this enum*/
-    RTC_INT_MAX
-} rtc_tick_interrupt_mode_t;
-
-/**
- * @brief      RTC mask structure
- *
- *             RTC mask structure for common use
- */
-typedef struct _rtc_mask
-{
-    /* Reserved */
-    uint32_t resv : 1;
-    /* Second mask */
-    uint32_t second : 1;
-    /* Minute mask */
-    uint32_t minute : 1;
-    /* Hour mask */
-    uint32_t hour : 1;
-    /* Week mask */
-    uint32_t week : 1;
-    /* Day mask */
-    uint32_t day : 1;
-    /* Month mask */
-    uint32_t month : 1;
-    /* Year mask */
-    uint32_t year : 1;
-} __attribute__((packed, aligned(1))) rtc_mask_t;
-
-/**
- * @brief       RTC register
- *
- * @note        RTC register table
- *
- * | Offset    | Name           | Description                         |
- * |-----------|----------------|-------------------------------------|
- * | 0x00      | date           | Timer date information              |
- * | 0x04      | time           | Timer time information              |
- * | 0x08      | alarm_date     | Alarm date information              |
- * | 0x0c      | alarm_time     | Alarm time information              |
- * | 0x10      | initial_count  | Timer counter initial value         |
- * | 0x14      | current_count  | Timer counter current value         |
- * | 0x18      | interrupt_ctrl | RTC interrupt settings              |
- * | 0x1c      | register_ctrl  | RTC register settings               |
- * | 0x20      | reserved0      | Reserved                            |
- * | 0x24      | reserved1      | Reserved                            |
- * | 0x28      | extended       | Timer extended information          |
- *
- */
-
-
-/**
- * @brief       Timer date information
- *
- *              No. 0 Register (0x00)
- */
-typedef struct _rtc_date
-{
-    /* Week. Range [0,6]. 0 is Sunday. */
-    uint32_t week : 3;
-    /* Reserved */
-    uint32_t resv0 : 5;
-    /* Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
-    uint32_t day : 5;
-    /* Reserved */
-    uint32_t resv1 : 3;
-    /* Month. Range [1,12] */
-    uint32_t month : 4;
-    /* Year. Range [0,99] */
-    uint32_t year : 12;
-} __attribute__((packed, aligned(4))) rtc_date_t;
-
-/**
- * @brief       Timer time information
- *
- *              No. 1 Register (0x04)
- */
-typedef struct _rtc_time
-{
-    /* Reserved */
-    uint32_t resv0 : 10;
-    /* Second. Range [0,59] */
-    uint32_t second : 6;
-    /* Minute. Range [0,59] */
-    uint32_t minute : 6;
-    /* Reserved */
-    uint32_t resv1 : 2;
-    /* Hour. Range [0,23] */
-    uint32_t hour : 5;
-    /* Reserved */
-    uint32_t resv2 : 3;
-} __attribute__((packed, aligned(4))) rtc_time_t;
-
-/**
- * @brief       Alarm date information
- *
- *              No. 2 Register (0x08)
- */
-typedef struct _rtc_alarm_date
-{
-    /* Alarm Week. Range [0,6]. 0 is Sunday. */
-    uint32_t week : 3;
-    /* Reserved */
-    uint32_t resv0 : 5;
-    /* Alarm Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
-    uint32_t day : 5;
-    /* Reserved */
-    uint32_t resv1 : 3;
-    /* Alarm Month. Range [1,12] */
-    uint32_t month : 4;
-    /* Alarm Year. Range [0,99] */
-    uint32_t year : 12;
-} __attribute__((packed, aligned(4))) rtc_alarm_date_t;
-
-/**
- * @brief       Alarm time information
- *
- *              No. 3 Register (0x0c)
- */
-typedef struct _rtc_alarm_time
-{
-    /* Reserved */
-    uint32_t resv0 : 10;
-    /* Alarm Second. Range [0,59] */
-    uint32_t second : 6;
-    /* Alarm Minute. Range [0,59] */
-    uint32_t minute : 6;
-    /* Reserved */
-    uint32_t resv1 : 2;
-    /* Alarm Hour. Range [0,23] */
-    uint32_t hour : 5;
-    /* Reserved */
-    uint32_t resv2 : 3;
-} __attribute__((packed, aligned(4))) rtc_alarm_time_t;
-
-/**
- * @brief       Timer counter initial value
- *
- *              No. 4 Register (0x10)
- */
-typedef struct _rtc_initial_count
-{
-    /* RTC counter initial value */
-    uint32_t count : 32;
-} __attribute__((packed, aligned(4))) rtc_initial_count_t;
-
-/**
- * @brief       Timer counter current value
- *
- *              No. 5 Register (0x14)
- */
-typedef struct _rtc_current_count
-{
-    /* RTC counter current value */
-    uint32_t count : 32;
-} __attribute__((packed, aligned(4))) rtc_current_count_t;
-
-/**
- * @brief      RTC interrupt settings
- *
- *             No. 6 Register (0x18)
- */
-typedef struct _rtc_interrupt_ctrl
-{
-    /* Reserved */
-    uint32_t tick_enable : 1;
-    /* Alarm interrupt enable */
-    uint32_t alarm_enable : 1;
-    /* Tick interrupt enable */
-    uint32_t tick_int_mode : 2;
-    /* Reserved */
-    uint32_t resv : 20;
-    /* Alarm compare mask for interrupt */
-    uint32_t alarm_compare_mask : 8;
-} __attribute__((packed, aligned(4))) rtc_interrupt_ctrl_t;
-
-/**
- * @brief       RTC register settings
- *
- *              No. 7 Register (0x1c)
- */
-typedef struct _rtc_register_ctrl
-{
-    /* RTC timer read enable */
-    uint32_t read_enable : 1;
-    /* RTC timer write enable */
-    uint32_t write_enable : 1;
-    /* Reserved */
-    uint32_t resv0 : 11;
-    /* RTC timer mask */
-    uint32_t TimerMask : 8;
-    /* RTC alarm mask */
-    uint32_t alarm_mask : 8;
-    /* RTC counter initial count value mask */
-    uint32_t initial_count_mask : 1;
-    /* RTC interrupt register mask */
-    uint32_t interrupt_register_mask : 1;
-    /* Reserved */
-    uint32_t resv1 : 1;
-} __attribute__((packed, aligned(4))) rtc_register_ctrl_t;
-
-/**
- * @brief       Reserved
- *
- *              No. 8 Register (0x20)
- */
-typedef struct _rtc_reserved0
-{
-    /* Reserved */
-    uint32_t resv : 32;
-} __attribute__((packed, aligned(4))) rtc_reserved0_t;
-
-/**
- * @brief      Reserved
- *
- *             No. 9 Register (0x24)
- */
-typedef struct _rtc_reserved1
-{
-    /* Reserved */
-    uint32_t resv : 32;
-} __attribute__((packed, aligned(4))) rtc_reserved1_t;
-
-/**
- * @brief      Timer extended information
- *
- *             No. 10 Register (0x28)
- */
-typedef struct _rtc_extended
-{
-    /* Century. Range [0,31] */
-    uint32_t century : 5;
-    /* Is leap year. 1 is leap year, 0 is not leap year */
-    uint32_t leap_year : 1;
-    /* Reserved */
-    uint32_t resv : 26;
-} __attribute__((packed, aligned(4))) rtc_extended_t;
-
-
-/**
- * @brief       Real-time clock struct
- *
- *              A real-time clock (RTC) is a computer clock that keeps track of
- *              the current time.
- */
-typedef struct _rtc
-{
-    /* No. 0 (0x00): Timer date information */
-    rtc_date_t date;
-    /* No. 1 (0x04): Timer time information */
-    rtc_time_t time;
-    /* No. 2 (0x08): Alarm date information */
-    rtc_alarm_date_t alarm_date;
-    /* No. 3 (0x0c): Alarm time information */
-    rtc_alarm_time_t alarm_time;
-    /* No. 4 (0x10): Timer counter initial value */
-    rtc_initial_count_t initial_count;
-    /* No. 5 (0x14): Timer counter current value */
-    rtc_current_count_t current_count;
-    /* No. 6 (0x18): RTC interrupt settings */
-    rtc_interrupt_ctrl_t interrupt_ctrl;
-    /* No. 7 (0x1c): RTC register settings */
-    rtc_register_ctrl_t register_ctrl;
-    /* No. 8 (0x20): Reserved */
-    rtc_reserved0_t reserved0;
-    /* No. 9 (0x24): Reserved */
-    rtc_reserved1_t reserved1;
-    /* No. 10 (0x28): Timer extended information */
-    rtc_extended_t extended;
-} __attribute__((packed, aligned(4))) rtc_t;
-
-
-/**
- * @brief       Real-time clock object
- */
-extern volatile rtc_t *const rtc;
-extern volatile uint32_t *const rtc_base;
-
-/**
- * @brief       Set date time to RTC
- *
- * @param[in]   year        The year
- * @param[in]   month       The month
- * @param[in]   day         The day
- * @param[in]   hour        The hour
- * @param[in]   minute      The minute
- * @param[in]   second      The second
- *
- * @return      result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_timer_set(int year, int month, int day, int hour, int minute, int second);
-
-/**
- * @brief       Get date time from RTC
- *
- * @param       year        The year
- * @param       month       The month
- * @param       day         The day
- * @param       hour        The hour
- * @param       minute      The minute
- * @param       second      The second
- *
- * @return      result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second);
-
-/**
- * @brief       Initialize RTC
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_init(void);
-
-/**
- * @brief       Set RTC in protect mode or not
- *
- * @param       enable        Enable flag
- *
- * @return      result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_protect_set(int enable);
-
-/**
- * @brief       Set RTC timer mode
- *
- * @param       timer_mode        Timer mode
- *
- */
-void rtc_timer_set_mode(rtc_timer_mode_t timer_mode);
-
-/**
- * @brief       Set RTC timer clock frequency
- *
- * @param       frequency        Frequency
- *
- * @return      result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_timer_set_clock_frequency(unsigned int frequency);
-
-/**
- * @brief       Set RTC timer clock count value
- *
- * @param       count        Count
- *
- * @return      result
- *     - 0      Success
- *     - Other  Fail
- */
-int rtc_timer_set_clock_count_value(unsigned int  count);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_RTC_H */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/hardware_spi.h

@@ -1,494 +0,0 @@
-/* Copyright 2018 Canaan Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-* @file hardware_spi.h
-* @brief add from Canaan k210 SDK
-*                https://canaan-creative.com/developer
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef __HARDWARE_SPI_H__
-#define __HARDWARE_SPI_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include "dmac.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* clang-format off */
-typedef struct _spi
-{
-    /* SPI Control Register 0                                    (0x00)*/
-    volatile uint32_t ctrlr0;
-    /* SPI Control Register 1                                    (0x04)*/
-    volatile uint32_t ctrlr1;
-    /* SPI Enable Register                                       (0x08)*/
-    volatile uint32_t ssienr;
-    /* SPI Microwire Control Register                            (0x0c)*/
-    volatile uint32_t mwcr;
-    /* SPI Slave Enable Register                                 (0x10)*/
-    volatile uint32_t ser;
-    /* SPI Baud Rate Select                                      (0x14)*/
-    volatile uint32_t baudr;
-    /* SPI Transmit FIFO Threshold Level                         (0x18)*/
-    volatile uint32_t txftlr;
-    /* SPI Receive FIFO Threshold Level                          (0x1c)*/
-    volatile uint32_t rxftlr;
-    /* SPI Transmit FIFO Level Register                          (0x20)*/
-    volatile uint32_t txflr;
-    /* SPI Receive FIFO Level Register                           (0x24)*/
-    volatile uint32_t rxflr;
-    /* SPI Status Register                                       (0x28)*/
-    volatile uint32_t sr;
-    /* SPI Interrupt Mask Register                               (0x2c)*/
-    volatile uint32_t imr;
-    /* SPI Interrupt Status Register                             (0x30)*/
-    volatile uint32_t isr;
-    /* SPI Raw Interrupt Status Register                         (0x34)*/
-    volatile uint32_t risr;
-    /* SPI Transmit FIFO Overflow Interrupt Clear Register       (0x38)*/
-    volatile uint32_t txoicr;
-    /* SPI Receive FIFO Overflow Interrupt Clear Register        (0x3c)*/
-    volatile uint32_t rxoicr;
-    /* SPI Receive FIFO Underflow Interrupt Clear Register       (0x40)*/
-    volatile uint32_t rxuicr;
-    /* SPI Multi-Master Interrupt Clear Register                 (0x44)*/
-    volatile uint32_t msticr;
-    /* SPI Interrupt Clear Register                              (0x48)*/
-    volatile uint32_t icr;
-    /* SPI DMA Control Register                                  (0x4c)*/
-    volatile uint32_t dmacr;
-    /* SPI DMA Transmit Data Level                               (0x50)*/
-    volatile uint32_t dmatdlr;
-    /* SPI DMA Receive Data Level                                (0x54)*/
-    volatile uint32_t dmardlr;
-    /* SPI Identification Register                               (0x58)*/
-    volatile uint32_t idr;
-    /* SPI DWC_ssi component version                             (0x5c)*/
-    volatile uint32_t ssic_version_id;
-    /* SPI Data Register 0-36                                    (0x60 -- 0xec)*/
-    volatile uint32_t dr[36];
-    /* SPI RX Sample Delay Register                              (0xf0)*/
-    volatile uint32_t rx_sample_delay;
-    /* SPI SPI Control Register                                  (0xf4)*/
-    volatile uint32_t spi_ctrlr0;
-    /* reserved                                                  (0xf8)*/
-    volatile uint32_t resv;
-    /* SPI XIP Mode bits                                         (0xfc)*/
-    volatile uint32_t xip_mode_bits;
-    /* SPI XIP INCR transfer opcode                              (0x100)*/
-    volatile uint32_t xip_incr_inst;
-    /* SPI XIP WRAP transfer opcode                              (0x104)*/
-    volatile uint32_t xip_wrap_inst;
-    /* SPI XIP Control Register                                  (0x108)*/
-    volatile uint32_t xip_ctrl;
-    /* SPI XIP Slave Enable Register                             (0x10c)*/
-    volatile uint32_t xip_ser;
-    /* SPI XIP Receive FIFO Overflow Interrupt Clear Register    (0x110)*/
-    volatile uint32_t xrxoicr;
-    /* SPI XIP time out register for continuous transfers        (0x114)*/
-    volatile uint32_t xip_cnt_time_out;
-    volatile uint32_t endian;
-} __attribute__((packed, aligned(4))) spi_t;
-/* clang-format on */
-
-typedef enum _spi_device_num
-{
-    SPI_DEVICE_0,
-    SPI_DEVICE_1,
-    SPI_DEVICE_2,
-    SPI_DEVICE_3,
-    SPI_DEVICE_MAX,
-} spi_device_num_t;
-
-typedef enum _spi_work_mode
-{
-    SPI_WORK_MODE_0,
-    SPI_WORK_MODE_1,
-    SPI_WORK_MODE_2,
-    SPI_WORK_MODE_3,
-} spi_work_mode_t;
-
-typedef enum _spi_frame_format
-{
-    SPI_FF_STANDARD,
-    SPI_FF_DUAL,
-    SPI_FF_QUAD,
-    SPI_FF_OCTAL
-} spi_frame_format_t;
-
-typedef enum _spi_instruction_address_trans_mode
-{
-    SPI_AITM_STANDARD,
-    SPI_AITM_ADDR_STANDARD,
-    SPI_AITM_AS_FRAME_FORMAT
-} spi_instruction_address_trans_mode_t;
-
-typedef enum _spi_transfer_mode
-{
-    SPI_TMOD_TRANS_RECV,
-    SPI_TMOD_TRANS,
-    SPI_TMOD_RECV,
-    SPI_TMOD_EEROM
-} spi_transfer_mode_t;
-
-
-typedef enum _spi_transfer_width
-{
-    SPI_TRANS_CHAR  = 0x1,
-    SPI_TRANS_SHORT = 0x2,
-    SPI_TRANS_INT   = 0x4,
-} spi_transfer_width_t;
-
-typedef enum _spi_chip_select
-{
-    SPI_CHIP_SELECT_0,
-    SPI_CHIP_SELECT_1,
-    SPI_CHIP_SELECT_2,
-    SPI_CHIP_SELECT_3,
-    SPI_CHIP_SELECT_MAX,
-} spi_chip_select_t;
-
-typedef enum
-{
-    WRITE_CONFIG,
-    READ_CONFIG,
-    WRITE_DATA_BYTE,
-    READ_DATA_BYTE,
-    WRITE_DATA_BLOCK,
-    READ_DATA_BLOCK,
-} spi_slave_command_e;
-
-typedef struct
-{
-    uint8_t cmd;
-    uint8_t err;
-    uint32_t addr;
-    uint32_t len;
-} spi_slave_command_t;
-
-typedef enum
-{
-    IDLE,
-    COMMAND,
-    TRANSFER,
-} spi_slave_status_e;
-
-typedef int (*spi_slave_receive_callback_t)(void *ctx);
-
-typedef struct _spi_slave_instance
-{
-    uint8_t int_pin;
-    uint8_t ready_pin;
-    dmac_channel_number_t dmac_channel;
-    uint8_t dfs;
-    uint8_t slv_oe;
-    uint8_t work_mode;
-    size_t data_bit_length;
-    volatile spi_slave_status_e status;
-    volatile spi_slave_command_t command;
-    volatile uint8_t *config_ptr;
-    uint32_t config_len;
-    spi_slave_receive_callback_t callback;
-} spi_slave_instance_t;
-
-typedef struct _spi_data_t
-{
-    dmac_channel_number_t tx_channel;
-    dmac_channel_number_t rx_channel;
-    uint32_t *tx_buf;
-    size_t tx_len;
-    uint32_t *rx_buf;
-    size_t rx_len;
-    spi_transfer_mode_t TransferMode;
-    bool fill_mode;
-} spi_data_t;
-
-extern volatile spi_t *const spi[4];
-
-/**
- * @brief       Set spi configuration
- *
- * @param[in]   spi_num             Spi bus number
- * @param[in]   mode                Spi mode
- * @param[in]   frame_format        Spi frame format
- * @param[in]   data_bit_length     Spi data bit length
- * @param[in]   endian              0:little-endian 1:big-endian
- *
- * @return      Void
- */
-void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
-              size_t data_bit_length, uint32_t endian);
-
-/**
- * @brief       Set multiline configuration
- *
- * @param[in]   spi_num                                 Spi bus number
- * @param[in]   instruction_length                      Instruction length
- * @param[in]   address_length                          Address length
- * @param[in]   wait_cycles                             Wait cycles
- * @param[in]   instruction_address_trans_mode          Spi transfer mode
- *
- */
-void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length,
-                           uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode);
-
-/**
- * @brief       Spi send data
- *
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   CmdBuff        Spi command buffer point
- * @param[in]   CmdLen         Spi command length
- * @param[in]   tx_buff         Spi transmit buffer point
- * @param[in]   tx_len          Spi transmit buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
-                            size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
-
-/**
- * @brief       Spi receive data
- *
- * @param[in]   spi_num             Spi bus number
- * @param[in]   chip_select         Spi chip select
- * @param[in]   CmdBuff            Spi command buffer point
- * @param[in]   CmdLen             Spi command length
- * @param[in]   rx_buff             Spi receive buffer point
- * @param[in]   rx_len              Spi receive buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
-                               size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
-
-/**
- * @brief       Spi special receive data
- *
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   CmdBuff        Spi command buffer point
- * @param[in]   CmdLen         Spi command length
- * @param[in]   rx_buff         Spi receive buffer point
- * @param[in]   rx_len          Spi receive buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
-                               size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
-
-/**
- * @brief       Spi special send data
- *
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   CmdBuff        Spi command buffer point
- * @param[in]   CmdLen         Spi command length
- * @param[in]   tx_buff         Spi transmit buffer point
- * @param[in]   tx_len          Spi transmit buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
-                            size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
-
-/**
- * @brief       Spi send data by dma
- *
- * @param[in]   channel_num     Dmac channel number
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   CmdBuff        Spi command buffer point
- * @param[in]   CmdLen         Spi command length
- * @param[in]   tx_buff         Spi transmit buffer point
- * @param[in]   tx_len          Spi transmit buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
-                                spi_chip_select_t chip_select,
-                                const uint8_t *CmdBuff, size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
-
-/**
- * @brief       Spi receive data by dma
- *
- * @param[in]   w_channel_num       Dmac write channel number
- * @param[in]   r_channel_num       Dmac read channel number
- * @param[in]   spi_num             Spi bus number
- * @param[in]   chip_select         Spi chip select
- * @param[in]   CmdBuff            Spi command buffer point
- * @param[in]   CmdLen             Spi command length
- * @param[in]   rx_buff             Spi receive buffer point
- * @param[in]   rx_len              Spi receive buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num,
-                                   dmac_channel_number_t dma_receive_channel_num,
-                                   spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
-                                   size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
-
-/**
- * @brief       Spi special send data by dma
- *
- * @param[in]   channel_num     Dmac channel number
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   CmdBuff        Spi command buffer point
- * @param[in]   CmdLen         Spi command length
- * @param[in]   tx_buff         Spi transmit buffer point
- * @param[in]   tx_len          Spi transmit buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
-                                spi_chip_select_t chip_select,
-                                const uint32_t *CmdBuff, size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
-
-/**
- * @brief       Spi special receive data by dma
- *
- * @param[in]   dma_send_channel_num        Dmac write channel number
- * @param[in]   dma_receive_channel_num     Dmac read channel number
- * @param[in]   spi_num                     Spi bus number
- * @param[in]   chip_select                 Spi chip select
- * @param[in]   CmdBuff                    Spi command buffer point
- * @param[in]   CmdLen                     Spi command length
- * @param[in]   rx_buff                     Spi receive buffer point
- * @param[in]   rx_len                      Spi receive buffer length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num,
-                                   dmac_channel_number_t dma_receive_channel_num,
-                                   spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
-                                   size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
-
-/**
- * @brief       Spi fill dma
- *
- * @param[in]   channel_num     Dmac channel number
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   tx_buff        Spi command buffer point
- * @param[in]   tx_len         Spi command length
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select,
-                       const uint32_t *tx_buff, size_t tx_len);
-
-/**
- * @brief       Spi normal send by dma
- *
- * @param[in]   channel_num     Dmac channel number
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   tx_buff         Spi transmit buffer point
- * @param[in]   tx_len          Spi transmit buffer length
- * @param[in]   stw             Spi transfer width
- *
- * @return      Result
- *     - 0      Success
- *     - Other  Fail
- */
-void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
-                              spi_chip_select_t chip_select,
-                              const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width);
-
-/**
- * @brief       Spi normal send by dma
- *
- * @param[in]   spi_num         Spi bus number
- * @param[in]   spi_clk         Spi clock rate
- *
- * @return      The real spi clock rate
- */
-uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk);
-
-/**
- * @brief       Spi full duplex send receive data by dma
- *
- * @param[in]   dma_send_channel_num          Dmac write channel number
- * @param[in]   dma_receive_channel_num       Dmac read channel number
- * @param[in]   spi_num                       Spi bus number
- * @param[in]   chip_select                   Spi chip select
- * @param[in]   tx_buf                        Spi send buffer
- * @param[in]   tx_len                        Spi send buffer length
- * @param[in]   rx_buf                        Spi receive buffer
- * @param[in]   rx_len                        Spi receive buffer length
- *
- */
-void spi_dup_send_receive_data_dma(dmac_channel_number_t dma_send_channel_num,
-                               dmac_channel_number_t dma_receive_channel_num,
-                               spi_device_num_t spi_num, spi_chip_select_t chip_select,
-                               const uint8_t *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len);
-
-/**
- * @brief       Set spi slave configuration
- *
- * @param[in]   int_pin             SPI master starts sending data interrupt.
- * @param[in]   ready_pin           SPI slave ready.
- * @param[in]   dmac_channel        Dmac channel number for block.
- * @param[in]   data_bit_length     Spi data bit length
- * @param[in]   data                SPI slave device data buffer.
- * @param[in]   len                 The length of SPI slave device data buffer.
- * @param[in]   callback            Callback of spi slave.
- *
- * @return      Void
- */
-void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t dmac_channel, size_t data_bit_length, uint8_t *data, uint32_t len, spi_slave_receive_callback_t callback);
-
-/**
- * @brief       Spi handle transfer data operations
- *
- * @param[in]   spi_num         Spi bus number
- * @param[in]   chip_select     Spi chip select
- * @param[in]   data            Spi transfer data information
- * @param[in]   cb              Spi DMA callback
- *
- */
-void spi_handle_data_dma(spi_device_num_t spi_num, spi_chip_select_t chip_select, spi_data_t data, plic_interrupt_t *cb);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __HARDWARE_SPI_H__ */

Ubiquitous/XiZi/board/xidatong-riscv64/third_party_driver/include/wdt.h

@@ -1,180 +0,0 @@
-/* Copyright 2018 Canaan Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-* @file wdt.h
-* @brief add from Canaan k210 SDK
-*                https://canaan-creative.com/developer
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2022-07-25
-*/
-
-#ifndef __WDT_H__
-#define __WDT_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <plic.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* clang-format off */
-typedef struct _wdt
-{
-    /* WDT Control Register                     (0x00) */
-    volatile uint32_t cr;
-    /* WDT Timeout Range Register               (0x04) */
-    volatile uint32_t torr;
-    /* WDT Current Counter Value Register       (0x08) */
-    volatile uint32_t ccvr;
-    /* WDT Counter Restart Register             (0x0c) */
-    volatile uint32_t crr;
-    /* WDT Interrupt Status Register            (0x10) */
-    volatile uint32_t stat;
-    /* WDT Interrupt Clear Register             (0x14) */
-    volatile uint32_t eoi;
-    /* reserverd                                (0x18) */
-    volatile uint32_t resv1;
-    /* WDT Protection level Register            (0x1c) */
-    volatile uint32_t prot_level;
-    /* reserved                                 (0x20-0xe0) */
-    volatile uint32_t resv4[49];
-    /* WDT Component Parameters Register 5      (0xe4) */
-    volatile uint32_t comp_param_5;
-    /* WDT Component Parameters Register 4      (0xe8) */
-    volatile uint32_t comp_param_4;
-    /* WDT Component Parameters Register 3      (0xec) */
-    volatile uint32_t comp_param_3;
-    /* WDT Component Parameters Register 2      (0xf0) */
-    volatile uint32_t comp_param_2;
-    /* WDT Component Parameters Register 1      (0xf4) */
-    volatile uint32_t comp_param_1;
-    /* WDT Component Version Register           (0xf8) */
-    volatile uint32_t comp_version;
-    /* WDT Component Type Register              (0xfc) */
-    volatile uint32_t comp_type;
-} __attribute__((packed, aligned(4))) wdt_t;
-
-typedef enum _wdt_device_number
-{
-    WDT_DEVICE_0,
-    WDT_DEVICE_1,
-    WDT_DEVICE_MAX,
-} wdt_device_number_t;
-
-
-#define WDT_RESET_ALL                                       0x00000000U
-#define WDT_RESET_CPU                                       0x00000001U
-
-/* WDT Control Register */
-#define WDT_CR_ENABLE                                       0x00000001U
-#define WDT_CR_RMOD_MASK                                    0x00000002U
-#define WDT_CR_RMOD_RESET                                   0x00000000U
-#define WDT_CR_RMOD_INTERRUPT                               0x00000002U
-#define WDT_CR_RPL_MASK                                     0x0000001CU
-#define WDT_CR_RPL(x)                                       ((x) << 2)
-/* WDT Timeout Range Register */
-#define WDT_TORR_TOP_MASK                                   0x000000FFU
-#define WDT_TORR_TOP(x)                                     ((x) << 4 | (x) << 0)
-/* WDT Current Counter Value Register */
-#define WDT_CCVR_MASK                                       0xFFFFFFFFU
-/* WDT Counter Restart Register */
-#define WDT_CRR_MASK                                        0x00000076U
-/* WDT Interrupt Status Register */
-#define WDT_STAT_MASK                                       0x00000001U
-/* WDT Interrupt Clear Register */
-#define WDT_EOI_MASK                                        0x00000001U
-/* WDT Protection level Register */
-#define WDT_PROT_LEVEL_MASK                                 0x00000007U
-/* WDT Component Parameter Register 5 */
-#define WDT_COMP_PARAM_5_CP_WDT_USER_TOP_MAX_MASK           0xFFFFFFFFU
-/* WDT Component Parameter Register 4 */
-#define WDT_COMP_PARAM_4_CP_WDT_USER_TOP_INIT_MAX_MASK      0xFFFFFFFFU
-/* WDT Component Parameter Register 3 */
-#define WDT_COMP_PARAM_3_CD_WDT_TOP_RST_MASK                0xFFFFFFFFU
-/* WDT Component Parameter Register 2 */
-#define WDT_COMP_PARAM_3_CP_WDT_CNT_RST_MASK                0xFFFFFFFFU
-/* WDT Component Parameter Register 1 */
-#define WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK                 0x00000001U
-#define WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK                 0x00000002U
-#define WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK                  0x00000004U
-#define WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK                   0x00000008U
-#define WDT_COMP_PARAM_1_WDT_HC_RPL_MASK                    0x00000010U
-#define WDT_COMP_PARAM_1_WDT_HC_TOP_MASK                    0x00000020U
-#define WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK               0x00000040U
-#define WDT_COMP_PARAM_1_WDT_PAUSE_MASK                     0x00000080U
-#define WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK                0x00000300U
-#define WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK                  0x00001C00U
-#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK                  0x000F0000U
-#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK             0x00F00000U
-#define WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK                 0x1F000000U
-/* WDT Component Version Register */
-#define WDT_COMP_VERSION_MASK                               0xFFFFFFFFU
-/* WDT Component Type Register */
-#define WDT_COMP_TYPE_MASK                                  0xFFFFFFFFU
-/* clang-format on */
-
-/**
- * @brief       Feed wdt
- */
-void wdt_feed(wdt_device_number_t id);
-
-/**
- * @brief       Start wdt
- *
- * @param[in]   id                  Wdt id 0 or 1
- * @param[in]   time_out_ms         Wdt trigger time
- * @param[in]   on_irq              Wdt interrupt callback
- *
- */
-void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq);
-
-/**
- * @brief       Start wdt
- *
- * @param[in]   id                 Wdt id 0 or 1
- * @param[in]   time_out_ms        Wdt trigger time
- * @param[in]   on_irq             Wdt interrupt callback
- * @param[in]   ctx                Param of callback
- *
- * @return      Wdt time
- *
- */
-uint32_t wdt_init(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq, void *ctx);
-
-/**
- * @brief       Stop wdt
- *
- * @param[in]   id      Wdt id 0 or 1
- *
- */
-void wdt_stop(wdt_device_number_t id);
-
-/**
- * @brief       Clear wdt interrupt
- *
- * @param[in]   id      Wdt id 0 or 1
- *
- */
-void wdt_clear_interrupt(wdt_device_number_t id);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WDT_H__ */

Ubiquitous/XiZi/resources/serial/dev_serial.c

@@ -829,9 +829,8 @@ int SerialDeviceRegister(struct SerialHardwareDevice *serial_device, void *seria
             serial_device->haldev.dev_done = (struct HalDevDone *)serial_device->dev_done;
         } else {
             serial_device->haldev.dev_done = (struct HalDevDone *)&dev_done;
+            serial_device->private_data = serial_param;
         }
-        
-        serial_device->private_data = serial_param;
 
         DoubleLinkListInsertNodeAfter(&serialdev_linklist, &(serial_device->haldev.dev_link));
     } else {