38 lines
1.3 KiB
Scala
38 lines
1.3 KiB
Scala
package cache.memory
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import chisel3._
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import chisel3.util._
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import cpu.CacheConfig
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class ReadOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
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val data = Output(gen)
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}
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class WriteOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
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val en = Input(Bool())
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val data = Input(gen)
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}
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class WriteOnlyMaskPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
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val en = Input(UInt(cacheConfig.bytesPerBank.W))
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val data = Input(gen)
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}
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class ReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
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val en = Input(Bool())
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val wdata = Input(gen)
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val rdata = Output(gen)
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}
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class MaskedReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
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val writeMask = Input(UInt(cacheConfig.bytesPerBank.W))
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val wdata = Input(gen)
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val rdata = Output(gen)
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}
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