65 lines
1.6 KiB
Scala
65 lines
1.6 KiB
Scala
package cache.memory
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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/** LUT ram for XPM, one port for read/write, one port for read
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* @param depth
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* how many lines there are in the bank
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* @param width
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* how wide in bits each line is
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* @param config
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* implicit configuration to control generate ram for simulation or elaboration
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*/
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class LUTRam(depth: Int, width: Int)(implicit val cpuConfig: CpuConfig) extends Module {
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require(isPow2(depth))
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val waddridth = log2Ceil(depth)
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val io = IO(new Bundle {
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val raddr = Input(UInt(waddridth.W))
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val rdata = Output(UInt(width.W))
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val waddr = Input(UInt(waddridth.W))
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val wdata = Input(UInt(width.W))
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val wen = Input(Bool())
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val writeOutput = Output(UInt(width.W))
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})
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if (cpuConfig.build) {
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val bank = Module(
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new LUTRamIP(
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wdataidth = width,
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waddridth = waddridth,
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byteWriteWidth = width,
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numberOfLines = depth
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)
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)
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bank.io.clka := clock
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bank.io.clkb := clock
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bank.io.rsta := reset
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bank.io.rstb := reset
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bank.io.regcea := false.B
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bank.io.regceb := false.B
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bank.io.ena := true.B
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bank.io.enb := true.B
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bank.io.addra := io.waddr
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bank.io.wea := io.wen
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bank.io.dina := io.wdata
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io.writeOutput := DontCare
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bank.io.addrb := io.raddr
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io.rdata := bank.io.doutb
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} else {
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val bank = RegInit(VecInit(Seq.fill(depth)(0.U(width.W))))
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io.rdata := bank(io.raddr)
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io.writeOutput := DontCare
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when(io.wen) {
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bank(io.waddr) := io.wdata
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}.otherwise {
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io.writeOutput := bank(io.waddr)
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}
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}
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}
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