411 lines
15 KiB
Scala
411 lines
15 KiB
Scala
package cpu.pipeline.execute
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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import chisel3.util.experimental.BoringUtils
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class CsrMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
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val in = Input(new Bundle {
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val pc = UInt(XLEN.W)
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val ex = new ExceptionInfo()
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val info = new InstInfo()
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val lr_wen = Bool()
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val lr_wbit = Bool()
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val lr_waddr = UInt(XLEN.W)
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})
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val out = Output(new Bundle {
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val flush = Bool()
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val target = UInt(XLEN.W)
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val lr = Bool()
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val lr_addr = UInt(XLEN.W)
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})
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}
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class CsrExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
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val in = Input(new Bundle {
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val valid = Bool()
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val pc = UInt(XLEN.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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})
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val out = Output(new Bundle {
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val rdata = UInt(XLEN.W)
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val ex = new ExceptionInfo()
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val flush = Bool()
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val target = UInt(XLEN.W)
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})
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}
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class CsrDecodeUnit extends Bundle {
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val mode = Output(Priv())
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val interrupt = Output(UInt(INT_WID.W))
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}
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class CsrTlb extends Bundle {
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val satp = Output(UInt(XLEN.W))
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val mstatus = Output(UInt(XLEN.W))
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val imode = Output(Priv())
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val dmode = Output(Priv())
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}
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class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val decodeUnit = new CsrDecodeUnit()
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val executeUnit = new CsrExecuteUnit()
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val memoryUnit = new CsrMemoryUnit()
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val tlb = new CsrTlb()
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})
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// 目前的csr只支持64位
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require(XLEN == 64, "XLEN must be 64")
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/* CSR寄存器定义 */
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// Machine Information Registers
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val mvendorid = RegInit(UInt(XLEN.W), 0.U) // 厂商ID
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val marchid = RegInit(UInt(XLEN.W), 0.U) // 架构ID
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val mimpid = RegInit(UInt(XLEN.W), 0.U) // 实现ID
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val mhartid = RegInit(UInt(XLEN.W), 0.U) // 硬件线程ID
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// Machine Trap Setup
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val mstatus_init = Wire(new Mstatus())
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mstatus_init := 0.U.asTypeOf(new Mstatus())
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mstatus_init.sxl := 2.U
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mstatus_init.uxl := 2.U
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val mstatus = RegInit(UInt(XLEN.W), mstatus_init.asUInt) // 状态寄存器
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val misa_init = Wire(new Misa())
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misa_init := 0.U.asTypeOf(new Misa())
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misa_init.mxl := 2.U
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def getMisaExt(ext: Char): UInt = { 1.U << (ext.toInt - 'a'.toInt) }
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var extensions = List('i')
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if (cpuConfig.hasMExtension) { extensions = extensions :+ 'm' }
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if (cpuConfig.hasAExtension) { extensions = extensions :+ 'a' }
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if (cpuConfig.hasSMode) { extensions = extensions :+ 's' }
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if (cpuConfig.hasUMode) { extensions = extensions :+ 'u' }
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misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i))
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val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
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val medeleg = RegInit(UInt(XLEN.W), 0.U) // 异常代理寄存器
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val mideleg = RegInit(UInt(XLEN.W), 0.U) // 中断代理寄存器
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val mie = RegInit(UInt(XLEN.W), 0.U) // 中断使能寄存器
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val mtvec = RegInit(UInt(XLEN.W), 0.U) // 中断向量基址寄存器
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val mcounteren = RegInit(UInt(XLEN.W), 0.U) // 计数器使能寄存器
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// Machine Trap Handling
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val mscratch = RegInit(UInt(XLEN.W), 0.U) // 临时寄存器
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val mepc = RegInit(UInt(XLEN.W), 0.U) // 异常程序计数器
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val mcause = RegInit(UInt(XLEN.W), 0.U) // 异常原因寄存器
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val mtval = RegInit(UInt(XLEN.W), 0.U) // 异常值寄存器
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val mipWire = WireInit(0.U.asTypeOf(new Interrupt))
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val mipReg = RegInit(UInt(XLEN.W), 0.U)
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val mipFixMask = "h77f".U(64.W)
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val mip = mipWire.asUInt | mipReg // 中断挂起寄存器
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// Machine Memory Protection
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val pmpcfg0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg3 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr3 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddrWmask = "h3fffffff".U(64.W) // 32bit physical address
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// Machine Counter/Timers
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val mcycle = RegInit(UInt(XLEN.W), 0.U) // 时钟周期计数器
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mcycle := mcycle + 1.U
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val minstret = RegInit(UInt(XLEN.W), 0.U) // 指令计数器
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// Supervisor Trap Setup
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// sstatus 状态寄存器，源自mstatus
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val sstatusWmask = "h00000000000c0122".U(XLEN.W)
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val sstatusRmask = "h80000003000de762".U(XLEN.W)
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// sedeleg 异常代理寄存器，未实现
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// sideleg 中断代理寄存器，未实现
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// sie 中断使能寄存器，源自mie
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val sieMask = "h222".U(64.W) & mideleg
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val stvec = RegInit(UInt(XLEN.W), 0.U) // 中断向量基址寄存器
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val scounteren = RegInit(UInt(XLEN.W), 0.U) // 计数器使能寄存器
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// Supervisor Trap Handling
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val sscratch = RegInit(UInt(XLEN.W), 0.U) // 临时寄存器
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val sepc = RegInit(UInt(XLEN.W), 0.U) // 异常程序计数器
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val scause = RegInit(UInt(XLEN.W), 0.U) // 异常原因寄存器
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val stval = RegInit(UInt(XLEN.W), 0.U) // 异常值寄存器
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// sip 中断挂起寄存器，源自mip
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val sipMask = "h222".U(64.W) & mideleg
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// Supervisor Protection and Translation
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val satp = RegInit(UInt(XLEN.W), 0.U) // 页表基址寄存器
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// Debug/Trace Registers (shared with Debug Mode)
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val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
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val tdata1 = RegInit(UInt(XLEN.W), 0.U) // 跟踪寄存器数据1寄存器
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val rdata = Wire(UInt(XLEN.W))
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val wdata = Wire(UInt(XLEN.W))
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// Atom LR/SC Control Bits
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val lr_wen = io.memoryUnit.in.lr_wen
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val lr_wbit = io.memoryUnit.in.lr_wbit
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val lr_waddr = io.memoryUnit.in.lr_waddr
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val lr = RegInit(Bool(), false.B)
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val lr_addr = RegInit(UInt(XLEN.W), 0.U)
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io.memoryUnit.out.lr := lr
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io.memoryUnit.out.lr_addr := lr_addr
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when(lr_wen) {
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lr := lr_wbit
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lr_addr := lr_waddr
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}
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// Side Effect
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def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = Cat(mstatusOld.fs === "b11".U, mstatus(XLEN - 2, 0))
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mstatusNew
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}
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val mstatus_wmask = Mux(
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VecInit(ModeM, ModeS, ModeU).contains(wdata.asTypeOf(new Mstatus).mpp),
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"h00000000007e19aa".U(64.W),
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"h00000000007e01aa".U(64.W)
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)
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// CSR reg map
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val mapping = Map(
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// User Counter/Timers
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MaskedRegMap(Cycle, mcycle),
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// Supervisor Trap Setup
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MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
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MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
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MaskedRegMap(Stvec, stvec),
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MaskedRegMap(Scounteren, scounteren),
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// Supervisor Trap Handling
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MaskedRegMap(Sscratch, sscratch),
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MaskedRegMap(Sepc, sepc),
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MaskedRegMap(Scause, scause),
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MaskedRegMap(Stval, stval),
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MaskedRegMap(Sip, mip, sipMask, MaskedRegMap.Unwritable, sipMask),
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// Supervisor Protection and Translation
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MaskedRegMap(Satp, satp),
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// Machine Information Registers
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MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable),
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MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable),
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MaskedRegMap(Mimpid, mimpid, 0.U, MaskedRegMap.Unwritable),
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MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable),
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// Machine Trap Setup
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MaskedRegMap(Mstatus, mstatus, mstatus_wmask),
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MaskedRegMap(Misa, misa), // MXL，EXT目前不支持可变
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MaskedRegMap(Medeleg, medeleg, "hbbff".U(XLEN.W)),
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MaskedRegMap(Mideleg, mideleg, "h222".U(XLEN.W)),
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MaskedRegMap(Mie, mie),
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MaskedRegMap(Mtvec, mtvec),
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MaskedRegMap(Mcounteren, mcounteren),
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// Machine Trap Handling
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MaskedRegMap(Mscratch, mscratch),
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MaskedRegMap(Mepc, mepc),
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MaskedRegMap(Mcause, mcause),
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MaskedRegMap(Mtval, mtval),
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MaskedRegMap(Mip, mip, 0.U, MaskedRegMap.Unwritable),
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// Machine Memory Protection
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// MaskedRegMap(Pmpcfg0, pmpcfg0),
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// MaskedRegMap(Pmpcfg1, pmpcfg1),
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// MaskedRegMap(Pmpcfg2, pmpcfg2),
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// MaskedRegMap(Pmpcfg3, pmpcfg3),
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// MaskedRegMap(PmpaddrBase + 0, pmpaddr0, pmpaddrWmask),
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// MaskedRegMap(PmpaddrBase + 1, pmpaddr1, pmpaddrWmask),
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// MaskedRegMap(PmpaddrBase + 2, pmpaddr2, pmpaddrWmask),
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// MaskedRegMap(PmpaddrBase + 3, pmpaddr3, pmpaddrWmask)
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// Debug/Trace Registers (shared with Debug Mode)
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MaskedRegMap(Tselect, tselect, 0.U, MaskedRegMap.Unwritable), // 用于通过 risc-v test
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MaskedRegMap(Tdata1, tdata1, 0.U, MaskedRegMap.Unwritable)
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)
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val mode = RegInit(Priv.m) // 当前特权模式
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// interrupts
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val mtip = io.ext_int.ti
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val meip = io.ext_int.ei
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val msip = io.ext_int.si
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mipWire.t.m := mtip
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mipWire.e.m := meip
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mipWire.s.m := msip
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val seip = meip
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val mip_raise_interrupt = WireInit(mip.asTypeOf(new Interrupt()))
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mip_raise_interrupt.e.s := mip.asTypeOf(new Interrupt).e.s | seip
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val mstatusBundle = mstatus.asTypeOf(new Mstatus())
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val ideleg = (mideleg & mip_raise_interrupt.asUInt)
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def priviledgedEnableDetect(x: Bool): Bool = Mux(
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x,
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((mode === ModeS) && mstatusBundle.ie.s) || (mode < ModeS),
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((mode === ModeM) && mstatusBundle.ie.m) || (mode < ModeM)
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)
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val interrupt_enable = Wire(Vec(INT_WID, Bool()))
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interrupt_enable.zip(ideleg.asBools).map { case (x, y) => x := priviledgedEnableDetect(y) }
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io.decodeUnit.interrupt := mie(INT_WID - 1, 0) & mip_raise_interrupt.asUInt & interrupt_enable.asUInt
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// 优先使用inst0的信息
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val mem_pc = io.memoryUnit.in.pc
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val mem_ex = io.memoryUnit.in.ex
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val mem_inst_info = io.memoryUnit.in.info
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val mem_inst = mem_inst_info.inst
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val mem_valid = mem_inst_info.valid
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val mem_addr = mem_inst(31, 20)
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val raise_exception = mem_ex.exception.asUInt.orR
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val raise_interrupt = mem_ex.interrupt.asUInt.orR
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val raise_exc_int = raise_exception || raise_interrupt
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// 不带前缀的信号为exe阶段的信号
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val valid = io.executeUnit.in.valid && !io.memoryUnit.out.flush // mem发生flush时，轻刷掉exe的信号
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val info = io.executeUnit.in.info
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val op = io.executeUnit.in.info.op
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val fusel = io.executeUnit.in.info.fusel
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val addr = io.executeUnit.in.info.inst(31, 20)
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val src1 = io.executeUnit.in.src_info.src1_data
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val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN)
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wdata := LookupTree(
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op,
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List(
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CSROpType.wrt -> src1,
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CSROpType.set -> (rdata | src1),
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CSROpType.clr -> (rdata & ~src1),
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CSROpType.wrti -> csri,
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CSROpType.seti -> (rdata | csri),
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CSROpType.clri -> (rdata & ~csri)
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)
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)
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val satp_legal = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
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val write = (valid && op =/= CSROpType.jmp) && (addr =/= Satp.U || satp_legal)
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val only_read = VecInit(CSROpType.set, CSROpType.seti, CSROpType.clr, CSROpType.clri).contains(op) && src1 === 0.U
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val illegal_mode = mode < addr(9, 8)
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val illegal_write = write && (addr(11, 10) === "b11".U) && !only_read
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val illegal_access = illegal_mode || illegal_write
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val wen = write && !illegal_access
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MaskedRegMap.generate(mapping, addr, rdata, wen, wdata)
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val illegal_addr = MaskedRegMap.isIllegalAddr(mapping, addr)
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val write_satp = (addr === Satp.U) && write
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val ipMapping = Map(
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MaskedRegMap(Mip, mipReg, mipFixMask),
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MaskedRegMap(Sip, mipReg, sipMask, MaskedRegMap.NoSideEffect, sipMask)
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)
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val rdataDummy = Wire(UInt(XLEN.W))
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MaskedRegMap.generate(ipMapping, addr, rdataDummy, wen, wdata)
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// CSR inst decode
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val ret = Wire(Bool())
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val isMret = mem_inst_info.ret(RetType.mret) && mem_valid
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val isSret = mem_inst_info.ret(RetType.sret) && mem_valid
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val isUret = mem_inst_info.ret(RetType.uret) && mem_valid
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ret := isMret || isSret || isUret
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val exceptionNO = ExcPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.exception(i), i.U, sum))
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val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
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val causeNO = (raise_interrupt << (XLEN - 1)) | Mux(raise_interrupt, interruptNO, exceptionNO)
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val deleg = Mux(raise_interrupt, mideleg, medeleg)
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val delegS = (deleg(causeNO(log2Ceil(EXC_WID) - 1, 0))) && (mode < ModeM)
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val tval_wen = raise_interrupt ||
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!raise_exception
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when(raise_exception) {
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val tval = mem_ex.tval(exceptionNO)
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when(delegS) {
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stval := tval
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}.otherwise {
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mtval := tval
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}
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}
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when(raise_exc_int) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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when(delegS) {
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scause := causeNO
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sepc := SignedExtend(mem_pc, XLEN)
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mstatusNew.spp := mode
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mstatusNew.pie.s := mstatusOld.ie.s
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mstatusNew.ie.s := false.B
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mode := ModeS
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when(tval_wen) { stval := 0.U }
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}.otherwise {
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mcause := causeNO
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mepc := SignedExtend(mem_pc, XLEN)
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mstatusNew.mpp := mode
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mstatusNew.pie.m := mstatusOld.ie.m
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mstatusNew.ie.m := false.B
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mode := ModeM
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when(tval_wen) { mtval := 0.U }
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}
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mstatus := mstatusNew.asUInt
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}
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val ret_target = Wire(UInt(XLEN.W))
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ret_target := DontCare
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val trap_target = Wire(UInt(XLEN.W))
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val tvec = Mux(delegS, stvec, mtvec)
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trap_target := (tvec(XLEN - 1, 2) << 2) + Mux(
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tvec(0) && raise_interrupt,
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(causeNO << 2),
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0.U
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)
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when(isMret) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// mstatusNew.mpp.m := ModeU
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mstatusNew.ie.m := mstatusOld.pie.m
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mode := mstatusOld.mpp
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mstatusNew.pie.m := true.B
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mstatusNew.mpp := ModeU
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mstatus := mstatusNew.asUInt
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lr := false.B
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ret_target := mepc
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}
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when(isSret) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// mstatusNew.mpp.m := ModeU
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mstatusNew.ie.s := mstatusOld.pie.s
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mode := Cat(0.U(1.W), mstatusOld.spp)
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mstatusNew.pie.s := true.B
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mstatusNew.spp := ModeU
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mstatus := mstatusNew.asUInt
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lr := false.B
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ret_target := sepc
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}
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io.tlb.imode := mode
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io.tlb.dmode := Mux(mstatusBundle.mprv, mstatusBundle.mpp, mode)
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io.tlb.satp := satp
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io.tlb.mstatus := mstatus
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io.decodeUnit.mode := mode
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||
io.executeUnit.out.ex := io.executeUnit.in.ex
|
||
io.executeUnit.out.ex.exception(illegalInstr) :=
|
||
(illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr)
|
||
io.executeUnit.out.ex.tval(illegalInstr) := io.executeUnit.in.info.inst
|
||
io.executeUnit.out.rdata := rdata
|
||
io.executeUnit.out.flush := write_satp
|
||
io.executeUnit.out.target := io.executeUnit.in.pc + 4.U
|
||
io.memoryUnit.out.flush := raise_exc_int || ret
|
||
io.memoryUnit.out.target := Mux(raise_exc_int, trap_target, ret_target)
|
||
}
|