52 lines
1.6 KiB
Scala
52 lines
1.6 KiB
Scala
package cpu.pipeline
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class Mdu extends Module {
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val io = IO(new Bundle {
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val info = Input(new Info())
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val src_info = Input(new SrcInfo())
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val result = Output(UInt(XLEN.W))
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})
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val mul = Module(new Mul()).io
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val div = Module(new Div()).io
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val valid = io.info.valid
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val op = io.info.op
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val is_div = MDUOpType.isDiv(op)
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val is_w = MDUOpType.isWordOp(op)
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val src1 = io.src_info.src1_data
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val src2 = io.src_info.src2_data
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val zeroExtend = ZeroExtend(_: UInt, XLEN + 1)
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val signedExtend = SignedExtend(_: UInt, XLEN + 1)
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val srcMulConvertTable = Seq(
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MDUOpType.mul -> (zeroExtend, zeroExtend),
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MDUOpType.mulh -> (signedExtend, signedExtend),
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MDUOpType.mulhsu -> (signedExtend, zeroExtend),
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MDUOpType.mulhu -> (zeroExtend, zeroExtend)
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)
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mul.src1 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._1(src1))))
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mul.src2 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._2(src2))))
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val srcDivConvertFunc = (x: UInt) =>
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Mux(is_w, Mux(MDUOpType.isDivSign(op), SignedExtend(x(31, 0), XLEN), ZeroExtend(x(31, 0), XLEN)), x)
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div.src1 := srcDivConvertFunc(src1)
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div.src2 := srcDivConvertFunc(src2)
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div.signed := MDUOpType.isDivSign(op)
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val mul_result = Mux(op(1, 0) === MDUOpType.mul, mul.result(XLEN - 1, 0), mul.result(2 * XLEN - 1, XLEN))
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val div_result = Mux(op(1), div.result(2 * XLEN - 1, XLEN), div.result(XLEN - 1, 0))
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val result = Mux(is_div, div_result, mul_result)
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io.result := Mux(is_w, SignedExtend(result(31, 0), XLEN), result)
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}
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