fix(icache): 修复取指bug

chisel/playground/src/Core.scala

@@ -43,7 +43,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   ctrl.executeUnit <> executeUnit.ctrl
   ctrl.memoryUnit <> memoryUnit.ctrl
   ctrl.writeBackUnit <> writeBackUnit.ctrl
-  ctrl.cacheCtrl.iCache_stall := io.inst.stall
+  ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall
   ctrl.cacheCtrl.dCache_stall := io.data.stall
 
   fetchUnit.memory <> memoryUnit.fetchUnit
@@ -142,6 +142,6 @@ class Core(implicit val config: CpuConfig) extends Module {
   io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
     memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
   io.inst.req    := !instFifo.full && !reset.asBool
-  io.inst.ready := ctrl.fetchUnit.allow_to_go
+  io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go
   io.data.ready := ctrl.memoryUnit.allow_to_go
 }

chisel/playground/src/cache/ICache.scala

@@ -14,21 +14,19 @@ class ICache(implicit config: CpuConfig) extends Module {
     val axi = new ICache_AXIInterface()
   })
 
-  val s_idle :: s_read :: s_finishwait :: Nil = Enum(3)
+  val s_idle :: s_uncached :: s_save :: Nil = Enum(3)
   val status                                = RegInit(s_idle)
 
-  io.cpu.inst_valid.map(_ := status === s_finishwait)
-  val read_next_addr = (status === s_idle || status === s_finishwait)
-  io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
+  val read_next_addr = (status === s_idle || status === s_save)
   val addr_err       = io.cpu.addr(read_next_addr)(63, 32).orR
-  val raddr    = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
+  val pc             = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
 
   // default
   val arvalid = RegInit(false.B)
   val araddr  = RegInit(0.U(32.W))
   io.axi.ar.id    := 0.U
   io.axi.ar.addr  := araddr
-  io.axi.ar.len   := (config.instFetchNum - 1).U
+  io.axi.ar.len   := 0.U
   io.axi.ar.size  := 2.U
   io.axi.ar.lock  := 0.U
   io.axi.ar.burst := BURST_INCR.U
@@ -36,54 +34,57 @@ class ICache(implicit config: CpuConfig) extends Module {
   io.axi.ar.prot  := 0.U
   io.axi.ar.cache := 0.U
 
-  val rdata = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U(32.W))))
+  val rready = RegInit(false.B)
+  val saved = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U.asTypeOf(new Bundle {
+    val inst  = UInt(32.W)
+    val valid = Bool()
+  }))))
   io.axi.r.ready := true.B
 
   val acc_err = RegInit(false.B)
-
-  io.cpu.inst.map(_ := 0.U)
   io.cpu.acc_err      := acc_err
-  io.cpu.stall      := false.B
-  io.cpu.inst       := rdata
+  io.cpu.icache_stall := false.B
+  (0 until config.instFetchNum).foreach(i => {
+    io.cpu.inst(i)       := saved(i).inst
+    io.cpu.inst_valid(i) := saved(i).valid
+  })
+  io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
 
   switch(status) {
     is(s_idle) {
-      when(io.cpu.req) {
-        when(addr_err) {
-          acc_err := true.B
-          status  := s_finishwait
-        }.otherwise {
-          araddr  := raddr
-          arvalid := true.B
-          status  := s_read
-        }
-      }
-    }
-    is(s_read) {
-      when(io.axi.ar.ready) {
-        arvalid := false.B
-      }
-      when(io.axi.r.valid) {
-        rdata(0) := Mux(araddr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
-        rdata(1) := Mux(araddr(2), 0.U, io.axi.r.data(63, 32))
-        acc_err  := io.axi.r.resp =/= RESP_OKEY.U
-        status   := s_finishwait
-      }
-    }
-    is(s_finishwait) {
-      when(io.cpu.ready) {
       acc_err := false.B
       when(io.cpu.req) {
         when(addr_err) {
           acc_err := true.B
-            status  := s_finishwait
+          status  := s_save
         }.otherwise {
-            araddr  := raddr
+          araddr         := pc
           arvalid        := true.B
-            status  := s_read
+          io.axi.ar.len  := 0.U
+          io.axi.ar.size := 2.U
+          status         := s_uncached
         }
       }
     }
+    is(s_uncached) {
+      when(io.axi.ar.valid) {
+        when(io.axi.ar.ready) {
+          arvalid := false.B
+          rready  := true.B
+        }
+      }.elsewhen(io.axi.r.valid && io.axi.r.ready) {
+        saved(0).inst  := Mux(araddr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
+        saved(0).valid := true.B
+        acc_err        := io.axi.r.resp =/= RESP_OKEY.U
+        rready         := false.B
+        status         := s_save
+      }
+    }
+    is(s_save) {
+      when(io.cpu.cpu_ready && !io.cpu.icache_stall) {
+        status := s_idle
+        (0 until config.instFetchNum).foreach(i => saved(i).valid := false.B)
+      }
     }
   }
 }

chisel/playground/src/defines/Bundles.scala

@@ -109,7 +109,7 @@ class WriteBackCtrl extends Bundle {
 class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   // read inst request from cpu
   val req       = Output(Bool())
-  val ready   = Output(Bool()) // !cpu_stall
+  val cpu_ready = Output(Bool()) // !cpu_stall
   val addr      = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
   val fence_i   = Output(Bool())
 
@@ -118,7 +118,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   val inst_valid   = Input(Vec(config.instFetchNum, Bool()))
   val acc_err      = Input(Bool())
   val addr_err     = Input(Bool())
-  val stall      = Input(Bool()) // icache_stall
+  val icache_stall = Input(Bool()) // icache_stall
 }
 
 // cpu to dcache