feat: 增加mtval相关信号

chisel/playground/src/pipeline/decoder/DecoderUnit.scala

@@ -122,7 +122,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst0.ex.exception.map(_             := false.B)
   io.executeStage.inst0.ex.exception(illegalInstr)     := !info(0).inst_legal
   io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
-  io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
+  io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(1, 0).orR ||
+    io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
   io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
     info(0).op === CSROpType.jmp
   io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
@@ -131,10 +132,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     info(0).op === CSROpType.jmp && priv_mode === ModeS && info(0).fusel === FuType.csr
   io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
     info(0).op === CSROpType.jmp && priv_mode === ModeU && info(0).fusel === FuType.csr
-  io.executeStage.inst0.ex.tval := Mux(
+  io.executeStage.inst0.ex.tval := MuxCase(
-    io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned),
+    0.U,
-    io.instFifo.inst(0).pc,
+    Seq(
-    0.U
+      pc(0)(1, 0).orR                                        -> pc(0),
+      (io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
+    )
   )
 
   io.executeStage.inst0.jb_info.jump_regiser     := jumpCtrl.out.jump_register
@@ -160,7 +163,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst1.ex.exception.map(_             := false.B)
   io.executeStage.inst1.ex.exception(illegalInstr)     := !info(1).inst_legal
   io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
-  io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
+  io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR ||
+    io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
   io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
     info(1).op === CSROpType.jmp
   io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
@@ -170,10 +174,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
     info(1).op === CSROpType.jmp && priv_mode === ModeU && info(1).fusel === FuType.csr
 
-  io.executeStage.inst1.ex.tval := Mux(
+  io.executeStage.inst1.ex.tval := MuxCase(
-    io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
+    0.U,
-    io.instFifo.inst(1).pc,
+    Seq(
-    0.U
+      pc(1)(1, 0).orR                                        -> pc(1),
+      (io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
+    )
   )
 
 }

chisel/playground/src/pipeline/execute/Csr.scala

@@ -273,12 +273,31 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val interruptNO   = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
   val causeNO       = (has_interrupt << (XLEN - 1)) | Mux(has_interrupt, interruptNO, exceptionNO)
 
+  val has_instrPageFault      = mem_ex.exception(instrPageFault)
+  val has_loadPageFault       = mem_ex.exception(loadPageFault)
+  val has_storePageFault      = mem_ex.exception(storePageFault)
+  val has_loadAddrMisaligned  = mem_ex.exception(loadAddrMisaligned)
+  val has_storeAddrMisaligned = mem_ex.exception(storeAddrMisaligned)
+  val has_instrAddrMisaligned = mem_ex.exception(instrAddrMisaligned)
+
   val tval_wen = has_interrupt ||
-    !(mem_ex.exception(instrPageFault) ||
+    !(has_instrPageFault ||
-      mem_ex.exception(loadPageFault) ||
+      has_loadPageFault ||
-      mem_ex.exception(storePageFault) ||
+      has_storePageFault ||
-      mem_ex.exception(loadAddrMisaligned) ||
+      has_instrAddrMisaligned ||
-      mem_ex.exception(storeAddrMisaligned))
+      has_loadAddrMisaligned ||
+      has_storeAddrMisaligned)
+
+  when(
+    has_instrPageFault ||
+      has_loadPageFault ||
+      has_storePageFault ||
+      has_instrAddrMisaligned ||
+      has_loadAddrMisaligned ||
+      has_storeAddrMisaligned
+  ) {
+    mtval := SignedExtend(mem_ex.tval, XLEN)
+  }
 
   when(has_exc_int) {
     val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))

chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala

@@ -78,6 +78,11 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     io.inst(i).ex.out                                := io.inst(i).ex.in
     io.inst(i).ex.out.exception(loadAddrMisaligned)  := !store_inst && !addr_aligned(i)
     io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
+    io.inst(i).ex.out.tval                           := Mux(
+      io.inst(i).ex.in.exception.asUInt.orR,
+      io.inst(i).ex.in.tval,
+      mem_addr(i)
+    )
   }
   io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
     !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -150,6 +150,15 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
       )
     )
   )
+  io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
+    io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
+  io.memoryStage.inst0.ex.tval := MuxCase(
+    io.executeStage.inst0.ex.tval,
+    Seq(
+      (io.executeStage.inst0.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst0.ex.tval,
+      (io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR)    -> io.fetchUnit.target
+    )
+  )
 
   io.memoryStage.inst1.pc                        := io.executeStage.inst1.pc
   io.memoryStage.inst1.info                      := io.executeStage.inst1.info
@@ -172,6 +181,15 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
       )
     )
   )
+  io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
+    io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
+  io.memoryStage.inst1.ex.tval := MuxCase(
+    io.executeStage.inst1.ex.tval,
+    Seq(
+      (io.executeStage.inst1.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst1.ex.tval,
+      (io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR)    -> io.fetchUnit.target
+    )
+  )
 
   io.decoderUnit.forward(0).exe.wen      := io.memoryStage.inst0.info.reg_wen
   io.decoderUnit.forward(0).exe.waddr    := io.memoryStage.inst0.info.reg_waddr