feat: 增加mtval相关信号
This commit is contained in:
Liphen
parent
8a3e85b201
commit
fb799d5e7f
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@ -119,10 +119,11 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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decoder(0).io.out.info.imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal
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io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
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io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal
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io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
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io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(1, 0).orR ||
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io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
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io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
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info(0).op === CSROpType.jmp
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io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
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@ -131,10 +132,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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info(0).op === CSROpType.jmp && priv_mode === ModeS && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeU && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.tval := Mux(
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io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned),
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io.instFifo.inst(0).pc,
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0.U
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io.executeStage.inst0.ex.tval := MuxCase(
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0.U,
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Seq(
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pc(0)(1, 0).orR -> pc(0),
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(io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
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)
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)
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io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
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@ -157,10 +160,11 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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decoder(1).io.out.info.imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal
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io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
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io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal
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io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
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io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR ||
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io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
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io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
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info(1).op === CSROpType.jmp
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io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
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@ -170,10 +174,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeU && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.tval := Mux(
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io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
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io.instFifo.inst(1).pc,
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0.U
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io.executeStage.inst1.ex.tval := MuxCase(
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0.U,
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Seq(
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pc(1)(1, 0).orR -> pc(1),
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(io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
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)
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)
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}
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@ -12,8 +12,8 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
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val inst = Vec(
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config.fuNum,
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new Bundle {
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val pc = UInt(PC_WID.W)
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val ex = new ExceptionInfo()
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val pc = UInt(PC_WID.W)
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val ex = new ExceptionInfo()
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val info = new InstInfo()
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}
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)
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@ -26,10 +26,10 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
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class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
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val in = Input(new Bundle {
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val valid = Bool()
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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val valid = Bool()
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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})
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val out = Output(new Bundle {
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val rdata = UInt(DATA_WID.W)
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@ -219,7 +219,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val mem_addr = mem_inst(31, 20)
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// 不带前缀的信号为exe阶段的信号
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val valid = io.executeUnit.in.valid
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val info = io.executeUnit.in.info
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val info = io.executeUnit.in.info
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val op = io.executeUnit.in.info.op
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val fusel = io.executeUnit.in.info.fusel
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val addr = io.executeUnit.in.info.inst(31, 20)
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@ -273,12 +273,31 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
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val causeNO = (has_interrupt << (XLEN - 1)) | Mux(has_interrupt, interruptNO, exceptionNO)
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val has_instrPageFault = mem_ex.exception(instrPageFault)
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val has_loadPageFault = mem_ex.exception(loadPageFault)
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val has_storePageFault = mem_ex.exception(storePageFault)
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val has_loadAddrMisaligned = mem_ex.exception(loadAddrMisaligned)
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val has_storeAddrMisaligned = mem_ex.exception(storeAddrMisaligned)
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val has_instrAddrMisaligned = mem_ex.exception(instrAddrMisaligned)
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val tval_wen = has_interrupt ||
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!(mem_ex.exception(instrPageFault) ||
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mem_ex.exception(loadPageFault) ||
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mem_ex.exception(storePageFault) ||
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mem_ex.exception(loadAddrMisaligned) ||
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mem_ex.exception(storeAddrMisaligned))
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!(has_instrPageFault ||
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has_loadPageFault ||
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has_storePageFault ||
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has_instrAddrMisaligned ||
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has_loadAddrMisaligned ||
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has_storeAddrMisaligned)
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when(
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has_instrPageFault ||
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has_loadPageFault ||
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has_storePageFault ||
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has_instrAddrMisaligned ||
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has_loadAddrMisaligned ||
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has_storeAddrMisaligned
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) {
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mtval := SignedExtend(mem_ex.tval, XLEN)
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}
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when(has_exc_int) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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@ -78,6 +78,11 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
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io.inst(i).ex.out := io.inst(i).ex.in
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io.inst(i).ex.out.exception(loadAddrMisaligned) := !store_inst && !addr_aligned(i)
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io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
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io.inst(i).ex.out.tval := Mux(
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io.inst(i).ex.in.exception.asUInt.orR,
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io.inst(i).ex.in.tval,
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mem_addr(i)
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)
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}
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io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
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!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
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@ -76,12 +76,12 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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)
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// input accessMemCtrl
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accessMemCtrl.inst(0).info := io.executeStage.inst0.info
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accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
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accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
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accessMemCtrl.inst(1).info := io.executeStage.inst1.info
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accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
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accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
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accessMemCtrl.inst(0).info := io.executeStage.inst0.info
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accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
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accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
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accessMemCtrl.inst(1).info := io.executeStage.inst1.info
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accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
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accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
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// input fu
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fu.ctrl <> io.ctrl.fu
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@ -90,8 +90,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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!MDUOpType.isDiv(io.executeStage.inst0.info.op)
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fu.inst(0).div_en := io.executeStage.inst0.info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst0.info.op)
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fu.inst(0).info := io.executeStage.inst0.info
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fu.inst(0).src_info := io.executeStage.inst0.src_info
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fu.inst(0).info := io.executeStage.inst0.info
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fu.inst(0).src_info := io.executeStage.inst0.src_info
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fu.inst(0).ex.in :=
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Mux(io.executeStage.inst0.info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
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fu.inst(1).pc := io.executeStage.inst1.pc
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@ -99,7 +99,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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!MDUOpType.isDiv(io.executeStage.inst1.info.op)
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fu.inst(1).div_en := io.executeStage.inst1.info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst1.info.op)
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fu.inst(1).info := io.executeStage.inst1.info
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fu.inst(1).info := io.executeStage.inst1.info
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fu.inst(1).src_info := io.executeStage.inst1.src_info
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fu.inst(1).ex.in := io.executeStage.inst1.ex
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fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
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@ -121,16 +121,16 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.ctrl.fu_stall := fu.stall_req
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io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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io.memoryStage.inst0.mem.info := accessMemCtrl.mem.out.info
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io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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io.memoryStage.inst0.mem.info := accessMemCtrl.mem.out.info
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io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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io.memoryStage.inst0.info := io.executeStage.inst0.info
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io.memoryStage.inst0.info := io.executeStage.inst0.info
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io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
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io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
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io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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@ -150,9 +150,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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)
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)
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)
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io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
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io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
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io.memoryStage.inst0.ex.tval := MuxCase(
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io.executeStage.inst0.ex.tval,
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Seq(
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(io.executeStage.inst0.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst0.ex.tval,
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(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) -> io.fetchUnit.target
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)
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)
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io.memoryStage.inst1.pc := io.executeStage.inst1.pc
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io.memoryStage.inst1.info := io.executeStage.inst1.info
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io.memoryStage.inst1.info := io.executeStage.inst1.info
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io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
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io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
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io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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@ -172,6 +181,15 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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)
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)
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)
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io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
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io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
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io.memoryStage.inst1.ex.tval := MuxCase(
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io.executeStage.inst1.ex.tval,
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Seq(
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(io.executeStage.inst1.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst1.ex.tval,
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(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) -> io.fetchUnit.target
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)
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)
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io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
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io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
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