refactor(axi): 将常量移动到cache-axi中

chisel/playground/src/cache/CacheAXIInterface.scala

@@ -12,20 +12,20 @@ class CacheAXIInterface extends Module {
   })
 
   // pass-through aw {
-  io.axi.aw.bits.id    := io.dcache.aw.bits.id
+  io.axi.aw.bits.id    := 1.U
   io.axi.aw.bits.addr  := io.dcache.aw.bits.addr
   io.axi.aw.bits.len   := io.dcache.aw.bits.len
   io.axi.aw.bits.size  := io.dcache.aw.bits.size
-  io.axi.aw.bits.burst := io.dcache.aw.bits.burst
   io.axi.aw.valid      := io.dcache.aw.valid
-  io.axi.aw.bits.prot  := io.dcache.aw.bits.prot
-  io.axi.aw.bits.cache := io.dcache.aw.bits.cache
-  io.axi.aw.bits.lock  := io.dcache.aw.bits.lock
+  io.axi.aw.bits.burst := 1.U
+  io.axi.aw.bits.prot  := 0.U
+  io.axi.aw.bits.cache := 0.U
+  io.axi.aw.bits.lock  := 0.U
   io.dcache.aw.ready   := io.axi.aw.ready
   // pass-through aw }
 
   // pass-through w {
-  io.axi.w.bits.id   := io.dcache.w.bits.id
+  io.axi.w.bits.id   := 1.U
   io.axi.w.bits.data := io.dcache.w.bits.data
   io.axi.w.bits.strb := io.dcache.w.bits.strb
   io.axi.w.bits.last := io.dcache.w.bits.last
@@ -59,11 +59,11 @@ class CacheAXIInterface extends Module {
   io.axi.ar.bits.addr  := Mux(ar_sel, io.dcache.ar.bits.addr, io.icache.ar.bits.addr)
   io.axi.ar.bits.len   := Mux(ar_sel, io.dcache.ar.bits.len, io.icache.ar.bits.len)
   io.axi.ar.bits.size  := Mux(ar_sel, io.dcache.ar.bits.size, io.icache.ar.bits.size)
-  io.axi.ar.bits.burst := Mux(ar_sel, io.dcache.ar.bits.burst, io.icache.ar.bits.burst)
   io.axi.ar.valid      := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid)
-  io.axi.ar.bits.prot  := Mux(ar_sel, io.dcache.ar.bits.prot, io.icache.ar.bits.prot)
-  io.axi.ar.bits.cache := Mux(ar_sel, io.dcache.ar.bits.cache, io.icache.ar.bits.cache)
-  io.axi.ar.bits.lock  := Mux(ar_sel, io.dcache.ar.bits.lock, io.icache.ar.bits.lock)
+  io.axi.ar.bits.burst := 1.U
+  io.axi.ar.bits.prot  := 0.U
+  io.axi.ar.bits.cache := 0.U
+  io.axi.ar.bits.lock  := 0.U
   io.icache.ar.ready   := !ar_sel && io.axi.ar.ready
   io.dcache.ar.ready   := ar_sel && io.axi.ar.ready
   // mux ar }

chisel/playground/src/cache/DCache.scala

@@ -30,7 +30,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
 
   val tlb_fill = RegInit(false.B)
   // * fsm * //
-  val s_idle :: s_uncached :: s_writeback :: s_replace :: Nil = Enum(4)
+  val s_idle :: s_uncached :: s_writeback :: s_replace :: s_save :: Nil = Enum(5)
   val state                                                             = RegInit(s_idle)
 
   io.cpu.tlb.fill           := tlb_fill
@@ -99,7 +99,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val dcache_stall = Mux(
     state === s_idle && !tlb_fill,
     Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall || !io.cpu.tlb.translation_ok), io.cpu.fence),
-    true.B
+    state =/= s_save
   )
   io.cpu.dcache_ready := !dcache_stall
 
@@ -111,7 +111,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val last_wdata         = RegNext(data_wdata)
   val cache_data_forward = Wire(Vec(nway, UInt(XLEN.W)))
 
-  io.cpu.rdata := cache_data_forward(sel)
+  io.cpu.rdata := Mux(state === s_save, saved_rdata, cache_data_forward(sel))
 
   // bank tagv ram
   for { i <- 0 until nway } {
@@ -213,14 +213,14 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
       when(tlb_fill) {
         tlb_fill := false.B
         when(!io.cpu.tlb.hit) {
-          state := s_idle
+          state := s_save
         }
       }.elsewhen(io.cpu.en) {
         when(addr_err) {
           acc_err := true.B
         }.elsewhen(!io.cpu.tlb.translation_ok) {
           when(io.cpu.tlb.tlb1_ok) {
-            state := s_idle
+            state := s_save
           }.otherwise {
             tlb_fill := true.B
           }
@@ -270,7 +270,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
               }
               when(!io.cpu.cpu_ready) {
                 saved_rdata := cache_data_forward(sel)
-                state       := s_idle
+                state       := s_save
               }
             }
           }
@@ -291,7 +291,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
             valid(fset)(0) := false.B
             valid(fset)(1) := false.B
           }
-          state := s_idle
+          state := s_save
         }
       }
     }
@@ -302,7 +302,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
       when(io.axi.r.valid) {
         saved_rdata := io.axi.r.bits.data
         acc_err     := io.axi.r.bits.resp =/= RESP_OKEY.U
-        state       := s_idle
+        state       := s_save
       }
     }
     is(s_writeback) {
@@ -440,5 +440,10 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
         }
       }
     }
+    is(s_save) {
+      when(io.cpu.dcache_ready && io.cpu.cpu_ready) {
+        state := s_idle
+      }
+    }
   }
 }

chisel/playground/src/cache/ICache.scala

@@ -136,9 +136,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
 
   io.cpu.icache_stall := Mux(state === s_idle && !tlb_fill, (!cache_hit_available && io.cpu.req), state =/= s_save)
 
-  val ar_init = WireInit(0.U.asTypeOf(new AR()))
-  ar_init.burst := 1.U
-  val ar      = RegInit(ar_init)
+  val ar      = RegInit(0.U.asTypeOf(new AR()))
   val arvalid = RegInit(false.B)
   ar <> io.axi.ar.bits
   arvalid <> io.axi.ar.valid