From fa41d3014684da3bf005d052997a97d67f099a9b Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 28 Dec 2023 18:39:43 +0800 Subject: [PATCH] =?UTF-8?q?fix(dcache):=20=E4=BF=AE=E5=A4=8D=E8=AF=BB?= =?UTF-8?q?=E6=95=B0=E6=8D=AE=E6=97=B6data=E7=9A=84=E7=B4=A2=E5=BC=95?= =?UTF-8?q?=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/DCache.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index b3824f9..f70bc0f 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -82,7 +82,9 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul // | | | bank index | bank offset | // ========================================================== - val exe_index = io.cpu.exe_addr(indexWidth + offsetWidth - 1, offsetWidth) + // exe级的index，用于访问第i行的数据 + val exe_index = io.cpu.exe_addr(indexWidth + offsetWidth - 1, offsetWidth) + // mem级的bank的index，用于访问第i个bank的数据 val bank_index = io.cpu.addr(bankIndexWidth + bankOffsetWidth - 1, bankOffsetWidth) // // 一个bank行内存了一个数据，所以bank_offset恒为0 @@ -159,7 +161,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val saved_rdata = RegInit(0.U(XLEN.W)) - io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(replace_index)(select_way)) + io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(bank_index)(select_way)) // bank tagv ram for { i <- 0 until nway } {