From f4e0e1b5be983c3dc13d422577452f088aa27693 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 22 Dec 2023 18:12:56 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20nset=E6=94=B9=E4=B8=BAnindex?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/CpuConfig.scala | 16 +++++++--------- chisel/playground/src/cache/Cache.scala | 4 ++-- chisel/playground/src/cache/DCache.scala | 2 +- chisel/playground/src/cache/ICache.scala | 4 ++-- .../src/cache/memory/PortDefinitions.scala | 10 +++++----- 5 files changed, 17 insertions(+), 19 deletions(-) diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala index d7ba5a8..c430d51 100644 --- a/chisel/playground/src/CpuConfig.scala +++ b/chisel/playground/src/CpuConfig.scala @@ -29,21 +29,19 @@ case class BranchPredictorConfig( case class CacheConfig( nway: Int = 2, // 路数 - nbank: Int = 8, // bank数 - nset: Int, - bankWidth: Int // bytes per bank + nbank: Int = 8, // 每个项目中的bank数 + nindex: Int, // 每路的项目数 + bankWidth: Int // 每个bank中的字节数 ) { val config = CpuConfig() - val indexWidth = log2Ceil(nset) + val indexWidth = log2Ceil(nindex) // index的位宽 val bankIndexWidth = log2Ceil(nbank) val bankOffsetWidth = log2Ceil(bankWidth) - val offsetWidth = bankIndexWidth + bankOffsetWidth - val tagWidth = 32 - indexWidth - offsetWidth - val tagvWidth = tagWidth + 1 + val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽 + val tagWidth = 32 - indexWidth - offsetWidth // tag的位宽 val bankWidthBits = bankWidth * 8 val burstSize = 16 - val ninst = config.instFetchNum // TODO:改成可随意修改的参数 - require(isPow2(nset)) + require(isPow2(nindex)) require(isPow2(nway)) require(isPow2(nbank)) require(isPow2(bankWidth)) diff --git a/chisel/playground/src/cache/Cache.scala b/chisel/playground/src/cache/Cache.scala index cd87004..c50a199 100644 --- a/chisel/playground/src/cache/Cache.scala +++ b/chisel/playground/src/cache/Cache.scala @@ -15,9 +15,9 @@ class Cache(implicit config: CpuConfig) extends Module { }) implicit val iCacheConfig = - CacheConfig(nset = 64, nbank = 4, bankWidth = (32 / 8) * 4) // 每个 bank 存 4 条 32 bit 指令 + CacheConfig(nindex = 64, nbank = 4, bankWidth = (32 / 8) * 4) // 每个 bank 存 4 条 32 bit 指令 implicit val dCacheConfig = - CacheConfig(nset = 128, bankWidth = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据 + CacheConfig(nindex = 128, bankWidth = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据 val icache = Module(new ICache(iCacheConfig)) val dcache = Module(new DCache(dCacheConfig)) diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index eaf92c7..f683904 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -17,7 +17,7 @@ class WriteBufferUnit extends Bundle { class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module { val nway: Int = cacheConfig.nway - val nset: Int = cacheConfig.nset + val nset: Int = cacheConfig.nindex val nbank: Int = cacheConfig.nbank val bankWidthBits: Int = cacheConfig.bankWidthBits val tagWidth: Int = cacheConfig.tagWidth diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 38d1d38..5739d06 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -10,9 +10,9 @@ import cpu.defines.Const._ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module { val nway: Int = cacheConfig.nway - val nset: Int = cacheConfig.nset + val nset: Int = cacheConfig.nindex val nbank: Int = cacheConfig.nbank - val ninst: Int = cacheConfig.ninst // 取指令的数量 + val ninst: Int = config.instFetchNum val bankOffsetWidth: Int = cacheConfig.bankOffsetWidth val bankWidth: Int = cacheConfig.bankWidth val tagWidth: Int = cacheConfig.tagWidth diff --git a/chisel/playground/src/cache/memory/PortDefinitions.scala b/chisel/playground/src/cache/memory/PortDefinitions.scala index f7ed75e..b918f5e 100644 --- a/chisel/playground/src/cache/memory/PortDefinitions.scala +++ b/chisel/playground/src/cache/memory/PortDefinitions.scala @@ -5,32 +5,32 @@ import chisel3.util._ import cpu.CacheConfig class ReadOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle { - val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W)) + val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W)) val data = Output(gen) } class WriteOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle { - val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W)) + val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W)) val en = Input(Bool()) val data = Input(gen) } class WriteOnlyMaskPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle { - val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W)) + val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W)) val en = Input(UInt(cacheConfig.bankWidth.W)) val data = Input(gen) } class ReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle { - val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W)) + val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W)) val en = Input(Bool()) val wdata = Input(gen) val rdata = Output(gen) } class MaskedReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle { - val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W)) + val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W)) val writeMask = Input(UInt(cacheConfig.bankWidth.W)) val wdata = Input(gen) val rdata = Output(gen)