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refactor: 将所有的地址宽度调为XLEN

This commit is contained in:
Liphen 2024-01-03 10:54:44 +08:00
parent 69e8b45484
commit f3d5b5cd1e
13 changed files with 35 additions and 41 deletions
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2
chisel/playground/src/cache/DCache.scala vendored
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@ -45,7 +45,7 @@ import cpu.defines.Const._
class WriteBufferUnit extends Bundle {
val data = UInt(XLEN.W)
val addr = UInt(DATA_ADDR_WID.W)
val addr = UInt(XLEN.W)
val strb = UInt(AXI_STRB_WID.W)
val size = UInt(AXI_SIZE_WID.W)
}

2
chisel/playground/src/cache/ICache.scala vendored
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@ -204,7 +204,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
rready <> io.axi.r.ready
val acc_err = RegInit(false.B)
val addr_err = io.cpu.addr(use_next_addr)(XLEN - 1, PADDR_WID).orR
val addr_err = io.cpu.addr(use_next_addr)(XLEN - 1, VADDR_WID).orR
when(acc_err) { acc_err := false.B }
io.cpu.acc_err := acc_err //TODO：实现cached段中的访存错误

2
chisel/playground/src/cache/mmu/DTlbL1.scala vendored
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@ -9,7 +9,7 @@ import cpu.CacheConfig
class DTlbL1 extends Module {
val io = IO(new Bundle {
val cache = new Tlb_DCache()
val addr = Input(UInt(DATA_ADDR_WID.W))
val addr = Input(UInt(XLEN.W))
})
val cacheConfig = CacheConfig("dcache")

6
chisel/playground/src/defines/Bundles.scala
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@ -109,7 +109,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// read inst request from cpu
val req = Output(Bool())
val complete_single_request = Output(Bool()) // !cpu_stall
val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
val addr = Output(Vec(config.instFetchNum, UInt(XLEN.W))) // virtual address and next virtual address
val fence_i = Output(Bool())
val dcache_stall = Output(Bool()) // dcache_stall
@ -125,8 +125,8 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// cpu to dcache
class Cache_DCache extends Bundle {
val exe_addr = Output(UInt(DATA_ADDR_WID.W))
val addr = Output(UInt(DATA_ADDR_WID.W))
val exe_addr = Output(UInt(XLEN.W))
val addr = Output(UInt(XLEN.W))
val rlen = Output(UInt(AXI_LEN_WID.W))
val en = Output(Bool())
val wen = Output(Bool())

10
chisel/playground/src/defines/Const.scala
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@ -7,7 +7,7 @@ import cpu.CpuConfig
trait CoreParameter {
def config = new CpuConfig
val XLEN = if (config.isRV32) 32 else 64
val VADDR_WID = 32
val VADDR_WID = if (config.isRV32) 32 else 39
val PADDR_WID = 32
}
@ -20,17 +20,13 @@ trait Constants extends CoreParameter {
// inst rom
val INST_WID = 32
val INST_ADDR_WID = XLEN
// data ram
val DATA_ADDR_WID = XLEN
// GPR RegFile
val AREG_NUM = 32
val REG_ADDR_WID = 5
}
trait AXIConst {
trait AXIConst extends Constants {
// AXI
val BURST_FIXED = 0
val BURST_INCR = 1
@ -43,7 +39,7 @@ trait AXIConst {
val RESP_DECERR = 3
val AXI_ID_WID = 4
val AXI_ADDR_WID = 32
val AXI_ADDR_WID = PADDR_WID // 32
val AXI_DATA_WID = 64
val AXI_STRB_WID = 8
val AXI_RESP_WID = 2

16
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
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@ -32,8 +32,8 @@ class DecoderBranchPredictorUnit extends Bundle {
val pht_index = Output(UInt(bpuConfig.phtDepth.W))
val branch_inst = Input(Bool())
val pred_branch = Input(Bool())
val branch_target = Input(UInt(XLEN.W))
val branch = Input(Bool())
val target = Input(UInt(XLEN.W))
val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
}
@ -89,10 +89,10 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
jumpCtrl.in.pc := pc(0)
jumpCtrl.in.src_info := io.executeStage.inst0.src_info
val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch
val inst0_branch = jumpCtrl.out.jump || io.bpu.branch
io.fetchUnit.branch := inst0_branch && io.ctrl.allow_to_go
io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
io.fetchUnit.target := Mux(io.bpu.branch, io.bpu.target, jumpCtrl.out.jump_target)
io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
io.bpu.pc := pc(0)
@ -108,7 +108,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.pc := pc(0)
io.executeStage.inst0.info := info(0)
io.executeStage.inst0.src_info.src1_data := MuxCase(
SignedExtend(pc(0), INST_ADDR_WID),
SignedExtend(pc(0), XLEN),
Seq(
info(0).src1_ren -> forwardCtrl.out.inst(0).src1.rdata,
(info(0).inst(6, 0) === "b0110111".U) -> 0.U
@ -144,14 +144,14 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch
io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
io.executeStage.inst0.jb_info.pred_branch := io.bpu.branch
io.executeStage.inst0.jb_info.branch_target := io.bpu.target
io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
io.executeStage.inst1.pc := pc(1)
io.executeStage.inst1.info := info(1)
io.executeStage.inst1.src_info.src1_data := MuxCase(
SignedExtend(pc(1), INST_ADDR_WID),
SignedExtend(pc(1), XLEN),
Seq(
info(1).src1_ren -> forwardCtrl.out.inst(1).src1.rdata,
(info(1).inst(6, 0) === "b0110111".U) -> 0.U

2
chisel/playground/src/pipeline/decoder/JumpCtrl.scala
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@ -16,7 +16,6 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
val forward = Vec(config.commitNum, new DataForwardToDecoderUnit())
})
val out = Output(new Bundle {
val jump_inst = Bool()
val jump_register = Bool()
val jump = Bool()
val jump_target = UInt(XLEN.W)
@ -28,7 +27,6 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
val fusel = io.in.info.fusel
val jump_inst = VecInit(BRUOpType.jal).contains(op) && fusel === FuType.bru
val jump_register_inst = VecInit(BRUOpType.jalr).contains(op) && fusel === FuType.bru
io.out.jump_inst := jump_inst || jump_register_inst
io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid
if (config.decoderNum == 2) {
io.out.jump_register := jump_register_inst && io.in.info.src1_raddr.orR &&

2
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
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@ -32,7 +32,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
}
val memoryStage = Output(new ExecuteUnitMemoryUnit())
val dataMemory = new Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W))
val addr = Output(UInt(XLEN.W))
}
})

2
chisel/playground/src/pipeline/execute/Fu.scala
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@ -23,7 +23,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
)
val stall_req = Output(Bool())
val dataMemory = new Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W))
val addr = Output(UInt(XLEN.W))
}
val branch = new Bundle {
val pred_branch = Input(Bool())

8
chisel/playground/src/pipeline/execute/fu/Csr.scala
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@ -15,14 +15,14 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
val set_lr = Bool()
val set_lr_val = Bool()
val set_lr_addr = UInt(DATA_ADDR_WID.W)
val set_lr_addr = UInt(XLEN.W)
})
val out = Output(new Bundle {
val flush = Bool()
val target = UInt(XLEN.W)
val lr = Bool()
val lr_addr = UInt(DATA_ADDR_WID.W)
val lr_addr = UInt(XLEN.W)
})
}
@ -147,9 +147,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
// Atom LR/SC Control Bits
val set_lr = WireInit(Bool(), false.B)
val set_lr_val = WireInit(Bool(), false.B)
val set_lr_addr = WireInit(UInt(DATA_ADDR_WID.W), 0.U)
val set_lr_addr = WireInit(UInt(XLEN.W), 0.U)
val lr = RegInit(Bool(), false.B)
val lr_addr = RegInit(UInt(DATA_ADDR_WID.W), 0.U)
val lr_addr = RegInit(UInt(XLEN.W), 0.U)
set_lr := io.memoryUnit.in.set_lr
set_lr_val := io.memoryUnit.in.set_lr_val
set_lr_addr := io.memoryUnit.in.set_lr_addr

8
chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala
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@ -62,7 +62,7 @@ class GlobalBranchPredictor(
io.decoder.branch_inst := io.decoder.info.valid &&
FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op)
io.decoder.branch_target := io.decoder.pc + imm
io.decoder.target := io.decoder.pc + imm
// 局部预测模式
val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))
@ -70,7 +70,7 @@ class GlobalBranchPredictor(
val bht_index = io.decoder.pc(1 + BHT_DEPTH, 2)
val pht_index = bht(bht_index)
io.decoder.pred_branch :=
io.decoder.branch :=
io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)
val update_pht_index = bht(update_bht_index)
@ -111,7 +111,7 @@ class AdaptiveTwoLevelPredictor(
io.decoder.branch_inst := io.decoder.info.valid &&
FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op)
io.decoder.branch_target := io.decoder.pc + imm
io.decoder.target := io.decoder.pc + imm
val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))
val pht = RegInit(VecInit(Seq.fill(1 << PHT_DEPTH)(strongly_taken)))
@ -121,7 +121,7 @@ class AdaptiveTwoLevelPredictor(
io.instBuffer.pht_index(i) := bht(io.instBuffer.pc(i)(1 + BHT_DEPTH, 2))
}
io.decoder.pred_branch :=
io.decoder.branch :=
io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
io.decoder.update_pht_index := bht(io.decoder.pc(1 + BHT_DEPTH, 2))

10
chisel/playground/src/pipeline/memory/Lsu.scala
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@ -18,7 +18,7 @@ class Lsu_DataMemory extends Bundle {
val rlen = UInt(AXI_LEN_WID.W)
val wen = Bool()
val wstrb = UInt(AXI_STRB_WID.W)
val addr = UInt(DATA_ADDR_WID.W)
val addr = UInt(XLEN.W)
val wdata = UInt(XLEN.W)
})
}
@ -31,7 +31,7 @@ class Lsu_MemoryUnit extends Bundle {
val ex = new ExceptionInfo()
val lr = Bool()
val lr_addr = UInt(DATA_ADDR_WID.W)
val lr_addr = UInt(XLEN.W)
val allow_to_go = Bool()
})
@ -44,7 +44,7 @@ class Lsu_MemoryUnit extends Bundle {
val set_lr = Bool()
val set_lr_val = Bool()
val set_lr_addr = UInt(DATA_ADDR_WID.W)
val set_lr_addr = UInt(XLEN.W)
})
}
@ -81,9 +81,9 @@ class Lsu(implicit val config: CpuConfig) extends Module {
// Atom LR/SC Control Bits
val setLr = Wire(Bool())
val setLrVal = Wire(Bool())
val setLrAddr = Wire(UInt(DATA_ADDR_WID.W))
val setLrAddr = Wire(UInt(XLEN.W))
val lr = WireInit(Bool(), false.B)
val lrAddr = WireInit(UInt(DATA_ADDR_WID.W), DontCare)
val lrAddr = WireInit(UInt(XLEN.W), DontCare)
io.memoryUnit.out.set_lr := setLr
io.memoryUnit.out.set_lr_val := setLrVal
io.memoryUnit.out.set_lr_addr := setLrAddr

2
chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
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@ -11,7 +11,7 @@ class LsExecute extends Module {
val dataMemory = new Lsu_DataMemory()
val in = Input(new Bundle {
val mem_en = Bool()
val mem_addr = UInt(DATA_ADDR_WID.W)
val mem_addr = UInt(XLEN.W)
val wdata = UInt(XLEN.W)
val info = new InstInfo()
})