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fix(id): 修复breakpoint信号错误

This commit is contained in:
Liphen 2023-12-01 16:45:33 +08:00
parent 651f8319dd
commit f3a2d4e522
1 changed files with 2 additions and 2 deletions
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4
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
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@ -125,7 +125,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(1, 0).orR || io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(1, 0).orR ||
io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak && io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
info(0).op === CSROpType.jmp info(0).op === CSROpType.jmp && info(0).fusel === FuType.csr
io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall && io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
info(0).op === CSROpType.jmp && priv_mode === ModeM && info(0).fusel === FuType.csr info(0).op === CSROpType.jmp && priv_mode === ModeM && info(0).fusel === FuType.csr
io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall && io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall &&
@ -166,7 +166,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR || io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR ||
io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak && io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
info(1).op === CSROpType.jmp info(1).op === CSROpType.jmp && info(0).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall && io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
info(1).op === CSROpType.jmp && priv_mode === ModeM && info(1).fusel === FuType.csr info(1).op === CSROpType.jmp && priv_mode === ModeM && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall && io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&