From f229789a12d7d71f1c47363723dece4e3cee02ce Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 13 Nov 2023 17:56:41 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E4=BF=AE=E6=94=B9=E5=B9=B6=E6=88=90?= =?UTF-8?q?=E5=8A=9F=E7=94=9F=E6=88=90=E6=97=A0cache=E7=9A=84axi?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 278 +++++++++--------- chisel/playground/src/PuaMips.scala | 8 - chisel/playground/src/cache/Cache.scala | 16 +- .../src/cache/CacheAXIInterface.scala | 2 +- chisel/playground/src/cache/DCache.scala | 36 ++- chisel/playground/src/cache/ICache.scala | 21 +- chisel/playground/src/defines/Bundles.scala | 62 +--- chisel/playground/src/defines/Const.scala | 6 +- chisel/playground/test/src/TestMain.scala | 4 +- 9 files changed, 193 insertions(+), 240 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 686efb3..13d6408 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -1,161 +1,161 @@ -package cpu +// package cpu -import chisel3._ -import chisel3.util._ -import chisel3.internal.DontCareBinding +// import chisel3._ +// import chisel3.util._ +// import chisel3.internal.DontCareBinding -import defines._ -import defines.Const._ -import pipeline.fetch._ -import pipeline.decoder._ -import pipeline.execute._ -import pipeline.memory._ -import pipeline.writeback._ -import ctrl._ -import mmu._ -import chisel3.util.experimental.decode.decoder -import cpu.pipeline.fetch.InstFifo +// import defines._ +// import defines.Const._ +// import pipeline.fetch._ +// import pipeline.decoder._ +// import pipeline.execute._ +// import pipeline.memory._ +// import pipeline.writeback._ +// import ctrl._ +// import mmu._ +// import chisel3.util.experimental.decode.decoder +// import cpu.pipeline.fetch.InstFifo -class Core(implicit val config: CpuConfig) extends Module { - val io = IO(new Bundle { - val ext_int = Input(UInt(6.W)) - val inst = new Cache_ICache() - val data = new Cache_DCache() - val debug = new DEBUG() - val statistic = if (!config.build) Some(new CPUStatistic()) else None - }) +// class Core(implicit val config: CpuConfig) extends Module { +// val io = IO(new Bundle { +// val ext_int = Input(UInt(6.W)) +// val inst = new Cache_ICache() +// val data = new Cache_DCache() +// val debug = new DEBUG() +// val statistic = if (!config.build) Some(new CPUStatistic()) else None +// }) - val ctrl = Module(new Ctrl()).io - val fetchUnit = Module(new FetchUnit()).io - val bpu = Module(new BranchPredictorUnit()).io - val instFifo = Module(new InstFifo()).io - val decoderUnit = Module(new DecoderUnit()).io - val regfile = Module(new ARegFile()).io - val executeStage = Module(new ExecuteStage()).io - val executeUnit = Module(new ExecuteUnit()).io - val cp0 = Module(new Cp0()).io - val memoryStage = Module(new MemoryStage()).io - val memoryUnit = Module(new MemoryUnit()).io - val writeBackStage = Module(new WriteBackStage()).io - val writeBackUnit = Module(new WriteBackUnit()).io +// val ctrl = Module(new Ctrl()).io +// val fetchUnit = Module(new FetchUnit()).io +// val bpu = Module(new BranchPredictorUnit()).io +// val instFifo = Module(new InstFifo()).io +// val decoderUnit = Module(new DecoderUnit()).io +// val regfile = Module(new ARegFile()).io +// val executeStage = Module(new ExecuteStage()).io +// val executeUnit = Module(new ExecuteUnit()).io +// val cp0 = Module(new Cp0()).io +// val memoryStage = Module(new MemoryStage()).io +// val memoryUnit = Module(new MemoryUnit()).io +// val writeBackStage = Module(new WriteBackStage()).io +// val writeBackUnit = Module(new WriteBackUnit()).io - ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty) - ctrl.decoderUnit <> decoderUnit.ctrl - ctrl.executeUnit <> executeUnit.ctrl - ctrl.memoryUnit <> memoryUnit.ctrl - ctrl.writeBackUnit <> writeBackUnit.ctrl - ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall - ctrl.cacheCtrl.dCache_stall := io.data.dcache_stall +// ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty) +// ctrl.decoderUnit <> decoderUnit.ctrl +// ctrl.executeUnit <> executeUnit.ctrl +// ctrl.memoryUnit <> memoryUnit.ctrl +// ctrl.writeBackUnit <> writeBackUnit.ctrl +// ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall +// ctrl.cacheCtrl.dCache_stall := io.data.dcache_stall - fetchUnit.memory <> memoryUnit.fetchUnit - fetchUnit.execute <> executeUnit.fetchUnit - fetchUnit.decoder <> decoderUnit.fetchUnit - fetchUnit.instFifo.full := instFifo.full - fetchUnit.iCache.inst_valid := io.inst.inst_valid - io.inst.addr(0) := fetchUnit.iCache.pc - io.inst.addr(1) := fetchUnit.iCache.pc_next - for (i <- 2 until config.instFetchNum) { - io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U - } +// fetchUnit.memory <> memoryUnit.fetchUnit +// fetchUnit.execute <> executeUnit.fetchUnit +// fetchUnit.decoder <> decoderUnit.fetchUnit +// fetchUnit.instFifo.full := instFifo.full +// fetchUnit.iCache.inst_valid := io.inst.inst_valid +// io.inst.addr(0) := fetchUnit.iCache.pc +// io.inst.addr(1) := fetchUnit.iCache.pc_next +// for (i <- 2 until config.instFetchNum) { +// io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U +// } - bpu.decoder.ena := ctrl.decoderUnit.allow_to_go - bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op - bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst - bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr - bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr - bpu.decoder.pc := decoderUnit.bpu.pc - bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U - bpu.decoder.pht_index := decoderUnit.bpu.pht_index - decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index - bpu.execute <> executeUnit.bpu - if (config.branchPredictor == "pesudo") { - bpu.regfile.get <> regfile.bpu.get - } - decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst - decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch - decoderUnit.bpu.branch_target := bpu.decoder.branch_target +// bpu.decoder.ena := ctrl.decoderUnit.allow_to_go +// bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op +// bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst +// bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr +// bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr +// bpu.decoder.pc := decoderUnit.bpu.pc +// bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U +// bpu.decoder.pht_index := decoderUnit.bpu.pht_index +// decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index +// bpu.execute <> executeUnit.bpu +// if (config.branchPredictor == "pesudo") { +// bpu.regfile.get <> regfile.bpu.get +// } +// decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst +// decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch +// decoderUnit.bpu.branch_target := bpu.decoder.branch_target - instFifo.do_flush := ctrl.decoderUnit.do_flush - instFifo.icache_stall := io.inst.icache_stall - instFifo.jump_branch_inst := decoderUnit.instFifo.jump_branch_inst - instFifo.ren <> decoderUnit.instFifo.allow_to_go - decoderUnit.instFifo.inst <> instFifo.read +// instFifo.do_flush := ctrl.decoderUnit.do_flush +// instFifo.icache_stall := io.inst.icache_stall +// instFifo.jump_branch_inst := decoderUnit.instFifo.jump_branch_inst +// instFifo.ren <> decoderUnit.instFifo.allow_to_go +// decoderUnit.instFifo.inst <> instFifo.read - for (i <- 0 until config.instFetchNum) { - instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i) - bpu.instBuffer.pc(i) := instFifo.write(i).pc - instFifo.wen(i) := io.inst.inst_valid(i) - instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U - instFifo.write(i).inst := io.inst.inst(i) - } +// for (i <- 0 until config.instFetchNum) { +// instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i) +// bpu.instBuffer.pc(i) := instFifo.write(i).pc +// instFifo.wen(i) := io.inst.inst_valid(i) +// instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U +// instFifo.write(i).inst := io.inst.inst(i) +// } - decoderUnit.instFifo.info.empty := instFifo.empty - decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty - decoderUnit.regfile <> regfile.read - for (i <- 0 until (config.fuNum)) { - decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe - decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg - decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i) - } - decoderUnit.cp0 <> cp0.decoderUnit - decoderUnit.executeStage <> executeStage.decoderUnit +// decoderUnit.instFifo.info.empty := instFifo.empty +// decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty +// decoderUnit.regfile <> regfile.read +// for (i <- 0 until (config.fuNum)) { +// decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe +// decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg +// decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i) +// } +// decoderUnit.cp0 <> cp0.decoderUnit +// decoderUnit.executeStage <> executeStage.decoderUnit - executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req || - !decoderUnit.executeStage.inst0.ex.bd && ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || - !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go - executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req || - (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) || - (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go) - executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go +// executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req || +// !decoderUnit.executeStage.inst0.ex.bd && ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || +// !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go +// executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req || +// (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) || +// (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go) +// executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go - executeUnit.decoderUnit.inst0_bd := decoderUnit.executeStage.inst0.ex.bd - executeUnit.executeStage <> executeStage.executeUnit - executeUnit.cp0 <> cp0.executeUnit - executeUnit.memoryStage <> memoryStage.executeUnit +// executeUnit.decoderUnit.inst0_bd := decoderUnit.executeStage.inst0.ex.bd +// executeUnit.executeStage <> executeStage.executeUnit +// executeUnit.cp0 <> cp0.executeUnit +// executeUnit.memoryStage <> memoryStage.executeUnit - cp0.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go - cp0.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go - cp0.ext_int := io.ext_int +// cp0.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go +// cp0.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go +// cp0.ext_int := io.ext_int - memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go - memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush +// memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go +// memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush - memoryUnit.memoryStage <> memoryStage.memoryUnit - memoryUnit.cp0 <> cp0.memoryUnit - memoryUnit.writeBackStage <> writeBackStage.memoryUnit +// memoryUnit.memoryStage <> memoryStage.memoryUnit +// memoryUnit.cp0 <> cp0.memoryUnit +// memoryUnit.writeBackStage <> writeBackStage.memoryUnit - memoryUnit.dataMemory.in.rdata := io.data.rdata - io.data.en := memoryUnit.dataMemory.out.en - io.data.rlen := memoryUnit.dataMemory.out.rlen - io.data.wen := memoryUnit.dataMemory.out.wen - io.data.wdata := memoryUnit.dataMemory.out.wdata - io.data.addr := memoryUnit.dataMemory.out.addr +// memoryUnit.dataMemory.in.rdata := io.data.rdata +// io.data.en := memoryUnit.dataMemory.out.en +// io.data.rlen := memoryUnit.dataMemory.out.rlen +// io.data.wen := memoryUnit.dataMemory.out.wen +// io.data.wdata := memoryUnit.dataMemory.out.wdata +// io.data.addr := memoryUnit.dataMemory.out.addr - writeBackStage.memoryUnit <> memoryUnit.writeBackStage - writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go - writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush +// writeBackStage.memoryUnit <> memoryUnit.writeBackStage +// writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go +// writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush - writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit - writeBackUnit.ctrl <> ctrl.writeBackUnit - regfile.write <> writeBackUnit.regfile +// writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit +// writeBackUnit.ctrl <> ctrl.writeBackUnit +// regfile.write <> writeBackUnit.regfile - io.debug <> writeBackUnit.debug +// io.debug <> writeBackUnit.debug - io.inst.fence := executeUnit.executeStage.inst0.inst_info.ifence - io.inst.fence_addr := executeUnit.executeStage.inst0.inst_info.mem_addr - io.data.fence := memoryUnit.memoryStage.inst0.inst_info.dfence - io.data.fence_addr := memoryUnit.memoryStage.inst0.inst_info.mem_addr - io.data.execute_addr := executeUnit.memoryStage.inst0.mem.addr - io.inst.req := !instFifo.full - io.inst.cpu_stall := !ctrl.fetchUnit.allow_to_go - io.data.cpu_stall := !ctrl.memoryUnit.allow_to_go +// io.inst.fence := executeUnit.executeStage.inst0.inst_info.ifence +// io.inst.fence_addr := executeUnit.executeStage.inst0.inst_info.mem_addr +// io.data.fence := memoryUnit.memoryStage.inst0.inst_info.dfence +// io.data.fence_addr := memoryUnit.memoryStage.inst0.inst_info.mem_addr +// io.data.execute_addr := executeUnit.memoryStage.inst0.mem.addr +// io.inst.req := !instFifo.full +// io.inst.cpu_stall := !ctrl.fetchUnit.allow_to_go +// io.data.cpu_stall := !ctrl.memoryUnit.allow_to_go - // ===----------------------------------------------------------------=== - // statistic - // ===----------------------------------------------------------------=== - if (!config.build) { - io.statistic.get.soc <> writeBackUnit.statistic.get - io.statistic.get.bpu <> executeUnit.statistic.get - } -} +// // ===----------------------------------------------------------------=== +// // statistic +// // ===----------------------------------------------------------------=== +// if (!config.build) { +// io.statistic.get.soc <> writeBackUnit.statistic.get +// io.statistic.get.bpu <> executeUnit.statistic.get +// } +// } diff --git a/chisel/playground/src/PuaMips.scala b/chisel/playground/src/PuaMips.scala index 58f3ad5..78956a0 100644 --- a/chisel/playground/src/PuaMips.scala +++ b/chisel/playground/src/PuaMips.scala @@ -21,12 +21,4 @@ class PuaMips extends Module { io.ext_int <> core.io.ext_int io.debug <> core.io.debug io.axi <> cache.io.axi - - // ===----------------------------------------------------------------=== - // statistic - // ===----------------------------------------------------------------=== - if (!config.build) { - io.statistic.get.cpu <> core.io.statistic.get - io.statistic.get.cache <> cache.io.statistic.get - } } diff --git a/chisel/playground/src/cache/Cache.scala b/chisel/playground/src/cache/Cache.scala index 0955f1f..8d4f65f 100644 --- a/chisel/playground/src/cache/Cache.scala +++ b/chisel/playground/src/cache/Cache.scala @@ -3,7 +3,6 @@ package cache import chisel3._ import chisel3.util._ import cpu.defines._ -import cpu.CacheConfig import cpu.CpuConfig class Cache(implicit config: CpuConfig) extends Module { @@ -11,13 +10,10 @@ class Cache(implicit config: CpuConfig) extends Module { val inst = Flipped(new Cache_ICache()) val data = Flipped(new Cache_DCache()) val axi = new AXI() - val statistic = if (!config.build) Some(new CacheStatistic()) else None }) - implicit val iCacheConfig = CacheConfig(nset = 64, nbank = 4, bankWidth = 16) - implicit val dCacheConfig = CacheConfig(nset = 128, bankWidth = 4) - val icache = Module(new ICache(iCacheConfig)) - val dcache = Module(new DCache(dCacheConfig)) + val icache = Module(new ICache()) + val dcache = Module(new DCache()) val axi_interface = Module(new CacheAXIInterface()) icache.io.axi <> axi_interface.io.icache @@ -26,12 +22,4 @@ class Cache(implicit config: CpuConfig) extends Module { io.inst <> icache.io.cpu io.data <> dcache.io.cpu io.axi <> axi_interface.io.axi - - // ===----------------------------------------------------------------=== - // statistic - // ===----------------------------------------------------------------=== - if (!config.build) { - io.statistic.get.icache <> icache.io.statistic.get - io.statistic.get.dcache <> dcache.io.statistic.get - } } diff --git a/chisel/playground/src/cache/CacheAXIInterface.scala b/chisel/playground/src/cache/CacheAXIInterface.scala index d378eef..242b028 100644 --- a/chisel/playground/src/cache/CacheAXIInterface.scala +++ b/chisel/playground/src/cache/CacheAXIInterface.scala @@ -44,7 +44,7 @@ class CacheAXIInterface extends Module { // we need to lock ar to avoid signals change during handshake val ar_sel_lock = RegInit(false.B) val ar_sel_val = RegInit(false.B) - val ar_sel = Mux(ar_sel_lock, ar_sel_val, io.dcache.ar.valid) + val ar_sel = Mux(ar_sel_lock, ar_sel_val, !io.icache.ar.valid && io.dcache.ar.valid) when(io.axi.ar.valid) { when(io.axi.ar.ready) { diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index b5998e3..017514d 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -9,7 +9,7 @@ import cpu.defines._ import cpu.CpuConfig import cpu.defines.Const._ -class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module { +class DCache(implicit config: CpuConfig) extends Module { val io = IO(new Bundle { val cpu = Flipped(new Cache_DCache()) val axi = new DCache_AXIInterface() @@ -34,24 +34,36 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val addr_err = io.cpu.addr(63, 32).orR // default + io.axi.aw.id := 1.U io.axi.aw.addr := 0.U io.axi.aw.len := 0.U io.axi.aw.size := 0.U io.axi.aw.burst := BURST_FIXED.U io.axi.aw.valid := 0.U + io.axi.aw.prot := 0.U + io.axi.aw.lock := 0.U + io.axi.aw.cache := 0.U + io.axi.w.id := 1.U io.axi.w.data := 0.U io.axi.w.strb := 0.U io.axi.w.last := 1.U io.axi.w.valid := 0.U io.axi.b.ready := 1.U + io.axi.ar.id := 1.U io.axi.ar.addr := 0.U io.axi.ar.len := 0.U io.axi.ar.size := 0.U io.axi.ar.burst := BURST_FIXED.U - io.axi.ar.valid := 0.U - io.axi.r.ready := 1.U + val arvalid = RegInit(false.B) + io.axi.ar.valid := arvalid + io.axi.ar.prot := 0.U + io.axi.ar.cache := 0.U + io.axi.ar.lock := 0.U + io.axi.r.ready := true.B io.cpu.rdata := 0.U + io.cpu.acc_err := false.B + switch(status) { is(s_idle) { when(io.cpu.en) { @@ -68,17 +80,17 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul io.axi.w.valid := true.B status := s_write }.otherwise { - io.axi.ar.addr := io.cpu.addr(31, 0) - io.axi.ar.size := Cat(false.B, io.cpu.size) - io.axi.ar.valid := true.B - status := s_read + io.axi.ar.addr := io.cpu.addr(31, 0) + io.axi.ar.size := Cat(false.B, io.cpu.size) + arvalid := true.B + status := s_read } } } } is(s_read) { when(io.axi.ar.ready) { - io.axi.ar.valid := false.B + arvalid := false.B } when(io.axi.r.valid) { io.cpu.rdata := io.axi.r.data @@ -115,10 +127,10 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul io.axi.w.valid := true.B status := s_write }.otherwise { - io.axi.ar.addr := io.cpu.addr(31, 0) - io.axi.ar.size := Cat(false.B, io.cpu.size) - io.axi.ar.valid := true.B - status := s_read + io.axi.ar.addr := io.cpu.addr(31, 0) + io.axi.ar.size := Cat(false.B, io.cpu.size) + arvalid := true.B + status := s_read } } }.otherwise { diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 009cbdd..c247109 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -21,11 +21,16 @@ class ICache(implicit config: CpuConfig) extends Module { val addr_err = io.cpu.addr.orR // default + io.axi.ar.id := 0.U io.axi.ar.addr := 0.U io.axi.ar.len := 0.U io.axi.ar.size := 2.U + io.axi.ar.lock := 0.U io.axi.ar.burst := BURST_FIXED.U - io.axi.ar.valid := false.B + val arvalid = RegInit(false.B) + io.axi.ar.valid := arvalid + io.axi.ar.prot := 0.U + io.axi.ar.cache := 0.U io.axi.r.ready := true.B io.cpu.rdata := 0.U io.cpu.acc_err := false.B @@ -37,15 +42,15 @@ class ICache(implicit config: CpuConfig) extends Module { io.cpu.acc_err := true.B status := s_finishwait }.otherwise { - io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W)) - io.axi.ar.valid := true.B - status := s_read + io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W)) + arvalid := true.B + status := s_read } } } is(s_read) { when(io.axi.ar.ready) { - io.axi.ar.valid := false.B + arvalid := false.B } when(io.axi.r.valid) { io.cpu.rdata := Mux(io.axi.ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0)) @@ -61,9 +66,9 @@ class ICache(implicit config: CpuConfig) extends Module { io.cpu.acc_err := true.B status := s_finishwait }.otherwise { - io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W)) - io.axi.ar.valid := true.B - status := s_read + io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W)) + arvalid := true.B + status := s_read } } } diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 3aa7df8..f5fd56e 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -163,7 +163,7 @@ class R extends Bundle { val ready = Output(Bool()) val id = Input(UInt(4.W)) - val data = Input(UInt(32.W)) + val data = Input(UInt(DATA_WID.W)) val resp = Input(UInt(2.W)) val last = Input(Bool()) val valid = Input(Bool()) @@ -185,7 +185,7 @@ class AW extends Bundle { class W extends Bundle { val id = Output(UInt(4.W)) - val data = Output(UInt(32.W)) + val data = Output(UInt(DATA_WID.W)) val strb = Output(UInt(4.W)) val last = Output(Bool()) val valid = Output(Bool()) @@ -206,7 +206,7 @@ class ICache_AXIInterface extends Bundle { val r = new R() } -class DCache_AXIInterface extends ICache_AXIInterface { +class DCache_AXIInterface extends Bundle { val aw = new AW() val w = new W() val b = new B() @@ -220,59 +220,13 @@ class Cache_AXIInterface extends Bundle { val dcache = new DCache_AXIInterface() } -// AXI read address channel -class AXI_AR extends Bundle { - val id = UInt(4.W) // transaction ID - val addr = UInt(32.W) // address - val len = UInt(8.W) // burst length - val size = UInt(3.W) // transfer size - val burst = UInt(2.W) // burst type - val lock = UInt(2.W) // lock type - val cache = UInt(4.W) // cache type - val prot = UInt(3.W) // protection type -} - -// AXI read data channel -class AXI_R extends Bundle { - val id = UInt(4.W) // transaction ID - val data = UInt(32.W) // read data - val resp = UInt(2.W) // response type - val last = Bool() // last beat of burst -} - -// AXI write address channel -class AXI_AW extends Bundle { - val id = UInt(4.W) // transaction ID - val addr = UInt(32.W) // address - val len = UInt(8.W) // burst length - val size = UInt(3.W) // transfer size - val burst = UInt(2.W) // burst type - val lock = UInt(2.W) // lock type - val cache = UInt(4.W) // cache type - val prot = UInt(3.W) // protection type -} - -// AXI write data channel -class AXI_W extends Bundle { - val id = UInt(4.W) // transaction ID - val data = UInt(32.W) // write data - val strb = UInt(4.W) // byte enable - val last = Bool() // last beat of burst -} - -// AXI write response channel -class AXI_B extends Bundle { - val id = UInt(4.W) // transaction ID - val resp = UInt(2.W) // response type -} - // AXI interface class AXI extends Bundle { - val ar = Decoupled(new AXI_AR()) // read address channel - val r = Flipped(Decoupled(new AXI_R())) // read data channel - val aw = Decoupled(new AXI_AW()) // write address channel - val w = Decoupled(new AXI_W()) // write data channel - val b = Flipped(Decoupled(new AXI_B())) // write response channel + val ar = new AR() // read address channel + val r = new R() // read data channel + val aw = new AW() // write address channel + val w = new W() // write data channel + val b = new B() // write response channel } class DEBUG(implicit config: CpuConfig) extends Bundle { diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index 8bcff72..2809998 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -7,11 +7,13 @@ import cpu.CpuConfig trait Constants { val config = new CpuConfig + val XLEN = 64 // 全局 - val PC_WID = 64 + val PC_WID = XLEN val PC_INIT = "h60000000".U(PC_WID.W) val EXT_INT_WID = 6 + val HILO_WID = 64 val WRITE_ENABLE = true.B val WRITE_DISABLE = false.B @@ -151,7 +153,7 @@ trait Constants { // GPR RegFile val AREG_NUM = 32 val REG_ADDR_WID = 5 - val DATA_WID = 64 + val DATA_WID = XLEN // CP0寄存器 // CP0 Register (5.w), Select (3.w) diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala index f96906f..8817895 100644 --- a/chisel/playground/test/src/TestMain.scala +++ b/chisel/playground/test/src/TestMain.scala @@ -1,10 +1,10 @@ import cpu._ import circt.stage._ -import cache.CacheAXIInterface +import cache.Cache object TestMain extends App { implicit val config = new CpuConfig() - def top = new CacheAXIInterface() + def top = new Cache() val useMFC = false // use MLIR-based firrtl compiler val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) if (useMFC) {