From f182d9b1b1fb2122bac259d9785a1d0dfae71c73 Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 18 Jan 2024 13:30:40 +0800 Subject: [PATCH] =?UTF-8?q?fix:=20ptw=E7=9A=84windex=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/DCache.scala | 33 ++++++++++++++++------- chisel/playground/src/cache/ICache.scala | 2 +- chisel/playground/src/cache/mmu/Tlb.scala | 8 +++--- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index 866a352..72d4858 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -83,11 +83,13 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo val ptw_state = RegInit(ptw_handshake) // 临时寄存器 - val ptw_working = ptw_state =/= ptw_handshake + val ptw_working = ptw_state =/= ptw_handshake && ptw_state =/= ptw_set val ptw_scratch = RegInit(0.U.asTypeOf(new Bundle { - val paddr = cacheAddr - val replace = Bool() + val paddr = cacheAddr + val replace = Bool() + val dcache_wait = Bool() })) + io.cpu.tlb.ptw.vpn.ready := false.B // ========================================================== @@ -176,7 +178,8 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo val use_next_addr = (state === s_idle) || (state === s_wait) val do_replace = RegInit(false.B) // replace index 表示行的索引 - val replace_index = io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth) + val replace_index = Wire(UInt(indexWidth.W)) + replace_index := io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth) val replace_wstrb = Wire(Vec(nbank, Vec(nway, UInt(AXI_STRB_WID.W)))) val replace_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata) @@ -492,7 +495,12 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo // ptw复用的模式 state := s_tlb_refill }.otherwise { - state := s_idle + when(ptw_scratch.dcache_wait && !io.cpu.complete_single_request) { + state := s_wait + }.otherwise { + ptw_scratch.dcache_wait := false.B + state := s_idle + } } } }.otherwise { @@ -531,8 +539,11 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo } is(s_wait) { // 等待流水线的allow_to_go信号，防止多次发出读、写请求 + io.cpu.tlb.ptw.vpn.ready := !ptw_working + ptw_scratch.dcache_wait := true.B when(io.cpu.complete_single_request) { - state := s_idle + ptw_scratch.dcache_wait := false.B + state := s_idle } } is(s_tlb_refill) { @@ -597,15 +608,15 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo } switch(ptw_state) { - is(ptw_handshake) { + is(ptw_handshake) { // 0 // 页表访问虚地址握手 - when(io.cpu.tlb.ptw.vpn.valid) { + when(io.cpu.tlb.ptw.vpn.fire) { vpn_index := (level - 1).U ppn := satp.ppn ptw_state := ptw_send } } - is(ptw_send) { + is(ptw_send) { // 1 val vpnn = Mux1H( Seq( (vpn_index === 0.U) -> vpn.vpn0, @@ -625,14 +636,16 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo }.otherwise { bank_raddr := ptw_addr.index tagRam.map(_.io.raddr := ptw_addr.index) + replace_index := ptw_addr.index ptw_state := ptw_cached ptw_scratch.paddr := ptw_addr ptw_scratch.replace := false.B } } - is(ptw_cached) { + is(ptw_cached) { // 2 bank_raddr := ptw_scratch.paddr.index tagRam.map(_.io.raddr := ptw_scratch.paddr.index) + replace_index := ptw_scratch.paddr.index for { i <- 0 until nway } { tag_compare_valid(i) := tag(i) === ptw_scratch.paddr.tag && // tag相同 diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 39e8c71..c96fafe 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -190,7 +190,7 @@ class ICache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo io.cpu.tlb.addr := io.cpu.addr(0) io.cpu.tlb.complete_single_request := io.cpu.complete_single_request - io.cpu.tlb.en := io.cpu.req + io.cpu.tlb.en := io.cpu.req && (state === s_idle || state === s_tlb_refill) val ar = RegInit(0.U.asTypeOf(new AR())) val arvalid = RegInit(false.B) diff --git a/chisel/playground/src/cache/mmu/Tlb.scala b/chisel/playground/src/cache/mmu/Tlb.scala index aefbf71..c843db3 100644 --- a/chisel/playground/src/cache/mmu/Tlb.scala +++ b/chisel/playground/src/cache/mmu/Tlb.scala @@ -122,12 +122,12 @@ class Tlb extends Module with HasTlbConst with HasCSRConst { // 我们默认优先发送数据tlb的请求 val choose_icache = Mux(ar_sel_lock, ar_sel_val, req_ptw(0) && !req_ptw(1)) - when(io.dcache.ptw.vpn.ready) { - when(io.dcache.ptw.vpn.valid) { + when(io.dcache.ptw.vpn.valid) { + when(io.dcache.ptw.vpn.ready) { + ar_sel_lock := false.B + }.otherwise { ar_sel_lock := true.B ar_sel_val := choose_icache - }.otherwise { - ar_sel_lock := false.B } }