diff --git a/chisel/playground/src/pipeline/memory/Lsu.scala b/chisel/playground/src/pipeline/memory/Lsu.scala
index 5082b1a..4f15e9f 100644
--- a/chisel/playground/src/pipeline/memory/Lsu.scala
+++ b/chisel/playground/src/pipeline/memory/Lsu.scala
@@ -181,12 +181,9 @@ class Lsu(implicit val cpuConfig: CpuConfig) extends Module {
     }
   }
   when(
-    lsExe.out.loadAddrMisaligned ||
-      lsExe.out.storeAddrMisaligned ||
-      lsExe.out.loadAccessFault ||
-      lsExe.out.storeAccessFault ||
-      lsExe.out.loadPageFault ||
-      lsExe.out.storePageFault
+    lsExe.out.addr_misaligned ||
+      lsExe.out.access_fault ||
+      lsExe.out.page_fault
   ) {
     state                   := s_idle
     io.memoryUnit.out.ready := true.B
@@ -200,12 +197,12 @@ class Lsu(implicit val cpuConfig: CpuConfig) extends Module {
   io.dataMemory <> lsExe.dataMemory
 
   io.memoryUnit.out.ex                                := io.memoryUnit.in.ex
-  io.memoryUnit.out.ex.exception(loadAddrMisaligned)  := lsExe.out.loadAddrMisaligned
-  io.memoryUnit.out.ex.exception(storeAddrMisaligned) := lsExe.out.storeAddrMisaligned
-  io.memoryUnit.out.ex.exception(loadAccessFault)     := lsExe.out.loadAccessFault
-  io.memoryUnit.out.ex.exception(storeAccessFault)    := lsExe.out.storeAccessFault
-  io.memoryUnit.out.ex.exception(loadPageFault)       := lsExe.out.loadPageFault
-  io.memoryUnit.out.ex.exception(storePageFault)      := lsExe.out.storePageFault
+  io.memoryUnit.out.ex.exception(loadAddrMisaligned)  := (loadReq || lrReq) && lsExe.out.addr_misaligned
+  io.memoryUnit.out.ex.exception(loadAccessFault)     := (loadReq || lrReq) && lsExe.out.access_fault
+  io.memoryUnit.out.ex.exception(loadPageFault)       := (loadReq || lrReq) && lsExe.out.page_fault
+  io.memoryUnit.out.ex.exception(storeAddrMisaligned) := (storeReq || scReq || amoReq) && lsExe.out.addr_misaligned
+  io.memoryUnit.out.ex.exception(storeAccessFault)    := (storeReq || scReq || amoReq) && lsExe.out.addr_misaligned
+  io.memoryUnit.out.ex.exception(storePageFault)      := (storeReq || scReq || amoReq) && lsExe.out.page_fault
 
   io.memoryUnit.out.ex.tval := io.dataMemory.out.addr
   io.memoryUnit.out.rdata := MuxCase(
diff --git a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
index 582e42e..e3a47e5 100644
--- a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
+++ b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
@@ -16,14 +16,11 @@ class LsExecute extends Module {
       val info     = new InstInfo()
     })
     val out = Output(new Bundle {
-      val loadAddrMisaligned  = Bool()
-      val storeAddrMisaligned = Bool()
-      val loadAccessFault     = Bool()
-      val storeAccessFault    = Bool()
-      val loadPageFault       = Bool()
-      val storePageFault      = Bool()
-      val rdata               = UInt(XLEN.W)
-      val ready               = Bool()
+      val addr_misaligned = Bool()
+      val access_fault    = Bool()
+      val page_fault      = Bool()
+      val rdata           = UInt(XLEN.W)
+      val ready           = Bool()
     })
   })
 
@@ -131,20 +128,16 @@ class LsExecute extends Module {
     )
   )
 
-  io.dataMemory.out.en    := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned
+  io.dataMemory.out.en    := valid && !io.out.addr_misaligned
   io.dataMemory.out.rlen  := size
   io.dataMemory.out.wen   := isStore
   io.dataMemory.out.wstrb := reqWmask
   io.dataMemory.out.addr  := reqAddr
   io.dataMemory.out.wdata := reqWdata
 
-  val is_amo = valid && LSUOpType.isAMO(op)
-  io.out.ready               := io.dataMemory.in.ready && io.dataMemory.out.en
-  io.out.rdata               := Mux(partialLoad, rdataPartialLoad, rdataSel)
-  io.out.loadAddrMisaligned  := valid && !isStore && !is_amo && !addrAligned
-  io.out.loadAccessFault     := valid && !isStore && !is_amo && access_fault
-  io.out.loadPageFault       := valid && !isStore && !is_amo && page_fault
-  io.out.storeAddrMisaligned := valid && (isStore || is_amo) && !addrAligned
-  io.out.storeAccessFault    := valid && (isStore || is_amo) && access_fault
-  io.out.storePageFault      := valid && (isStore || is_amo) && page_fault
+  io.out.ready           := io.dataMemory.in.ready && io.dataMemory.out.en
+  io.out.rdata           := Mux(partialLoad, rdataPartialLoad, rdataSel)
+  io.out.addr_misaligned := valid && !addrAligned
+  io.out.access_fault    := valid && access_fault
+  io.out.page_fault      := valid && page_fault
 }