From eecedc66595aa788febfdd42d3d87b41b72d0e04 Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 21 Nov 2023 12:01:51 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E8=AE=BF=E5=AD=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../pipeline/memory/DataMemoryAccess.scala | 258 +++++++----------- chisel/playground/test/src/TestMain.scala | 3 +- 2 files changed, 95 insertions(+), 166 deletions(-) diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala index bd0a89f..8d70100 100644 --- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala +++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala @@ -1,168 +1,96 @@ -// package cpu.pipeline.memory +package cpu.pipeline.memory -// import chisel3._ -// import chisel3.util._ -// import cpu.defines._ -// import cpu.defines.Const._ -// import cpu.CpuConfig +import chisel3._ +import chisel3.util._ +import cpu.defines._ +import cpu.defines.Const._ +import cpu.CpuConfig -// class DataMemoryAccess(implicit val config: CpuConfig) extends Module { -// val io = IO(new Bundle { -// val memoryUnit = new Bundle { -// val in = Input(new Bundle { -// val mem_en = Bool() -// val inst_info = new InstInfo() -// val mem_wdata = UInt(DATA_WID.W) -// val mem_addr = UInt(DATA_ADDR_WID.W) -// val mem_sel = Vec(config.fuNum, Bool()) -// val ex = Vec(config.fuNum, new ExceptionInfo()) -// val llbit = Bool() -// }) -// val out = Output(new Bundle { -// val rdata = Output(UInt(DATA_WID.W)) -// }) -// } +class DataMemoryAccess(implicit val config: CpuConfig) extends Module { + val io = IO(new Bundle { + val memoryUnit = new Bundle { + val in = Input(new Bundle { + val mem_en = Bool() + val inst_info = new InstInfo() + val mem_wdata = UInt(DATA_WID.W) + val mem_addr = UInt(DATA_ADDR_WID.W) + val mem_sel = Vec(config.fuNum, Bool()) + val ex = Vec(config.fuNum, new ExceptionInfo()) + }) + val out = Output(new Bundle { + val rdata = Output(UInt(DATA_WID.W)) + }) + } -// val dataMemory = new Bundle { -// val in = Input(new Bundle { -// val rdata = UInt(DATA_WID.W) -// }) -// val out = Output(new Bundle { -// val en = Bool() -// val rlen = UInt(2.W) -// val wen = UInt(4.W) -// val addr = UInt(DATA_ADDR_WID.W) -// val wdata = UInt(DATA_WID.W) -// }) -// } -// }) -// val mem_addr = io.memoryUnit.in.mem_addr -// val mem_addr2 = mem_addr(1, 0) -// val mem_rdata = io.dataMemory.in.rdata -// val mem_wdata = io.memoryUnit.in.mem_wdata -// val op = io.memoryUnit.in.inst_info.op -// io.dataMemory.out.en := io.memoryUnit.in.mem_en && -// (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).flush_req || -// io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).flush_req && !io.memoryUnit.in.ex(1).flush_req) -// io.dataMemory.out.addr := mem_addr - -// io.memoryUnit.out.rdata := MuxLookup(op, 0.U)( -// Seq( -// EXE_LB -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> Util.signedExtend(mem_rdata(31, 24)), -// "b10".U -> Util.signedExtend(mem_rdata(23, 16)), -// "b01".U -> Util.signedExtend(mem_rdata(15, 8)), -// "b00".U -> Util.signedExtend(mem_rdata(7, 0)) -// ) -// ), -// EXE_LBU -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> Util.zeroExtend(mem_rdata(31, 24)), -// "b10".U -> Util.zeroExtend(mem_rdata(23, 16)), -// "b01".U -> Util.zeroExtend(mem_rdata(15, 8)), -// "b00".U -> Util.zeroExtend(mem_rdata(7, 0)) -// ) -// ), -// EXE_LH -> Mux( -// mem_addr2(1), -// Util.signedExtend(mem_rdata(31, 16)), -// Util.signedExtend(mem_rdata(15, 0)) -// ), -// EXE_LHU -> Mux( -// mem_addr2(1), -// Util.zeroExtend(mem_rdata(31, 16)), -// Util.zeroExtend(mem_rdata(15, 0)) -// ), -// EXE_LW -> mem_rdata, -// EXE_LL -> mem_rdata, -// EXE_LWL -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> mem_rdata, -// "b10".U -> Cat(mem_rdata(23, 0), mem_wdata(7, 0)), -// "b01".U -> Cat(mem_rdata(15, 0), mem_wdata(15, 0)), -// "b00".U -> Cat(mem_rdata(7, 0), mem_wdata(23, 0)) -// ) -// ), -// EXE_LWR -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> Cat(mem_wdata(31, 8), mem_rdata(31, 24)), -// "b10".U -> Cat(mem_wdata(31, 16), mem_rdata(31, 16)), -// "b01".U -> Cat(mem_wdata(31, 24), mem_rdata(31, 8)), -// "b00".U -> mem_rdata -// ) -// ) -// ) -// ) -// io.dataMemory.out.wdata := MuxLookup(op, mem_wdata)( // default SW, SC -// Seq( -// EXE_SB -> Fill(4, mem_wdata(7, 0)), -// EXE_SH -> Fill(2, mem_wdata(15, 0)), -// EXE_SWL -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> mem_wdata, -// "b10".U -> Cat(0.U(8.W), mem_wdata(31, 8)), -// "b01".U -> Cat(0.U(16.W), mem_wdata(31, 16)), -// "b00".U -> Cat(0.U(24.W), mem_wdata(31, 24)) -// ) -// ), -// EXE_SWR -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> Cat(mem_wdata(7, 0), 0.U(24.W)), -// "b10".U -> Cat(mem_wdata(15, 0), 0.U(16.W)), -// "b01".U -> Cat(mem_wdata(23, 0), 0.U(8.W)), -// "b00".U -> mem_wdata -// ) -// ) -// ) -// ) -// io.dataMemory.out.wen := MuxLookup(op, 0.U)( -// Seq( -// EXE_SB -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> "b1000".U, -// "b10".U -> "b0100".U, -// "b01".U -> "b0010".U, -// "b00".U -> "b0001".U -// ) -// ), -// EXE_SH -> Mux(mem_addr2(1), "b1100".U, "b0011".U), -// EXE_SW -> "b1111".U, -// EXE_SC -> Fill(4, io.memoryUnit.in.llbit), -// EXE_SWL -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> "b1111".U, -// "b10".U -> "b0111".U, -// "b01".U -> "b0011".U, -// "b00".U -> "b0001".U -// ) -// ), -// EXE_SWR -> MuxLookup(mem_addr2, 0.U)( -// Seq( -// "b11".U -> "b1000".U, -// "b10".U -> "b1100".U, -// "b01".U -> "b1110".U, -// "b00".U -> "b1111".U -// ) -// ) -// ) -// ) -// io.dataMemory.out.rlen := MuxLookup(op, 0.U)( -// Seq( -// EXE_LW -> 2.U, -// EXE_LL -> 2.U, -// EXE_LH -> 1.U, -// EXE_LHU -> 1.U, -// EXE_LB -> 0.U, -// EXE_LBU -> 0.U, -// EXE_LWL -> 2.U, -// EXE_LWR -> 2.U, -// EXE_SW -> 2.U, -// EXE_SWL -> 2.U, -// EXE_SWR -> 2.U, -// EXE_SC -> 2.U, -// EXE_SH -> 1.U, -// EXE_SB -> 0.U -// ) -// ) -// } + val dataMemory = new Bundle { + val in = Input(new Bundle { + val rdata = UInt(DATA_WID.W) + }) + val out = Output(new Bundle { + val en = Bool() + val rlen = UInt(2.W) + val wen = UInt(4.W) + val addr = UInt(DATA_ADDR_WID.W) + val wdata = UInt(DATA_WID.W) + }) + } + }) + val mem_addr = io.memoryUnit.in.mem_addr + val mem_addr2 = mem_addr(1, 0) + val mem_rdata = io.dataMemory.in.rdata + val mem_wdata = io.memoryUnit.in.mem_wdata + val op = io.memoryUnit.in.inst_info.op + io.dataMemory.out.en := io.memoryUnit.in.mem_en && + (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).flush_req || + io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).flush_req && !io.memoryUnit.in.ex(1).flush_req) + io.dataMemory.out.addr := mem_addr + val rdata = Util.LookupTree( + mem_addr(2, 0), + List( + "b000".U -> mem_rdata(63, 0), + "b001".U -> mem_rdata(63, 8), + "b010".U -> mem_rdata(63, 16), + "b011".U -> mem_rdata(63, 24), + "b100".U -> mem_rdata(63, 32), + "b101".U -> mem_rdata(63, 40), + "b110".U -> mem_rdata(63, 48), + "b111".U -> mem_rdata(63, 56) + ) + ) + io.memoryUnit.out.rdata := Util.LookupTree( + op, + List( + LSUOpType.lb -> Util.signedExtend(rdata(7, 0), XLEN), + LSUOpType.lh -> Util.signedExtend(rdata(15, 0), XLEN), + LSUOpType.lw -> Util.signedExtend(rdata(31, 0), XLEN), + LSUOpType.lbu -> Util.zeroExtend(rdata(7, 0), XLEN), + LSUOpType.lhu -> Util.zeroExtend(rdata(15, 0), XLEN), + LSUOpType.lwu -> Util.zeroExtend(rdata(31, 0), XLEN) + ) + ) + def genWdata(data: UInt, sizeEncode: UInt): UInt = { + Util.LookupTree( + sizeEncode, + List( + "b00".U -> Fill(8, data(7, 0)), + "b01".U -> Fill(4, data(15, 0)), + "b10".U -> Fill(2, data(31, 0)), + "b11".U -> data + ) + ) + } + io.dataMemory.out.wdata := genWdata(mem_wdata, op(1, 0)) + def genWmask(addr: UInt, sizeEncode: UInt): UInt = { + Util.LookupTree( + sizeEncode, + List( + "b00".U -> 0x1.U, //0001 << addr(2:0) + "b01".U -> 0x3.U, //0011 + "b10".U -> 0xf.U, //1111 + "b11".U -> 0xff.U //11111111 + ) + ) << addr(2, 0) + } + io.dataMemory.out.wen := genWmask(mem_addr, op(1, 0)) + io.dataMemory.out.rlen := op(1, 0) +} diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala index 788b1be..0618b01 100644 --- a/chisel/playground/test/src/TestMain.scala +++ b/chisel/playground/test/src/TestMain.scala @@ -9,10 +9,11 @@ import cpu.pipeline.execute.Alu import cpu.pipeline.execute.BranchCtrl import cpu.pipeline.execute.Fu import cpu.pipeline.execute.ExeAccessMemCtrl +import cpu.pipeline.memory.DataMemoryAccess object TestMain extends App { implicit val config = new CpuConfig() - def top = new ExeAccessMemCtrl() + def top = new DataMemoryAccess() val useMFC = false // use MLIR-based firrtl compiler val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) if (useMFC) {