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fix(ptw): 修复working逻辑

This commit is contained in:
Liphen 2024-01-20 14:41:42 +08:00
parent 3b330cf8d7
commit ee3b3bddcd
1 changed files with 4 additions and 1 deletions
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5
chisel/playground/src/cache/DCache.scala vendored
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@ -94,7 +94,10 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
val ptw_state = RegInit(ptw_handshake) val ptw_state = RegInit(ptw_handshake)
// 临时寄存器 // 临时寄存器
val ptw_working = ptw_state =/= ptw_handshake && ptw_state =/= ptw_set val ptw_working =
ptw_state =/= ptw_handshake &&
ptw_state =/= ptw_set &&
!(io.cpu.tlb.ptw.pte.bits.access_fault || io.cpu.tlb.ptw.pte.bits.page_fault)
val ptw_scratch = RegInit(0.U.asTypeOf(new Bundle { val ptw_scratch = RegInit(0.U.asTypeOf(new Bundle {
val paddr = pAddr val paddr = pAddr
val replace = Bool() val replace = Bool()