diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
index 13d0146..7a483e0 100644
--- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
@@ -12,7 +12,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
     val in = Input(new Bundle {
       val allow_to_go = Bool()
       val pc          = UInt(PC_WID.W)
-      val info   = new InstInfo()
+      val info        = new InstInfo()
       val src_info    = new SrcInfo()
       val forward     = Vec(config.fuNum, new DataForwardToDecoderUnit())
     })
@@ -44,6 +44,6 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
   io.out.jump_target := Mux(
     jump_inst,
     io.in.src_info.src1_data + io.in.src_info.src2_data,
-    io.in.src_info.src1_data
+    (io.in.src_info.src1_data + io.in.src_info.src2_data) & ~1.U(XLEN.W)
   )
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index b859078..2c3d31a 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -115,7 +115,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     Seq(
       (fu.branch.pred_fail && fu.branch.branch)    -> io.executeStage.inst0.jb_info.branch_target,
       (fu.branch.pred_fail && !fu.branch.branch)   -> (io.executeStage.inst0.pc + 4.U),
-      (io.executeStage.inst0.jb_info.jump_regiser) -> (io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data)
+      (io.executeStage.inst0.jb_info.jump_regiser) -> ((io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data) & ~1.U(XLEN.W)),
     )
   )