diff --git a/chisel/playground/src/pipeline/fetch/FetchUnit.scala b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
index 86f88c0..fcde053 100644
--- a/chisel/playground/src/pipeline/fetch/FetchUnit.scala
+++ b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
@@ -13,7 +13,20 @@ class FetchUnit extends Module {
     val instSram    = new InstSram()
   })
 
-  val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), io.decodeStage.data.valid)
+  val boot :: send :: recieve :: Nil = Enum(3)
+  val state                          = RegInit(boot)
+
+  switch(state) {
+    is(boot) {
+      state := send
+    }
+    is(send) {
+      state := recieve
+    }
+    is(recieve) {}
+  }
+
+  val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
 
   io.instSram.addr := MuxCase(
     pc + 4.U,
@@ -23,7 +36,7 @@ class FetchUnit extends Module {
     )
   )
 
-  io.decodeStage.data.valid           := RegNext(!reset.asBool, false.B) & !reset.asBool
+  io.decodeStage.data.valid           := state === recieve
   io.decodeStage.data.pc              := pc
   io.decodeStage.data.inst            := io.instSram.rdata
   io.decodeStage.data.addr_misaligned := pc(1, 0) =/= 0.U