From eab5da04cf63ab6aa5f1c42748c6028aa66e3e0d Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Tue, 28 Nov 2023 15:24:00 +0800
Subject: [PATCH] =?UTF-8?q?fix(mem):=20ld=E7=9B=B8=E5=85=B3=E8=AF=BB?=
 =?UTF-8?q?=E9=94=99=E8=AF=AF?=
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---
 chisel/playground/src/pipeline/memory/DataMemoryAccess.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
index 33bab2d..a97c122 100644
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@@ -59,8 +59,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       "b111".U -> mem_rdata(63, 56)
     )
   )
-  io.memoryUnit.out.rdata := LookupTree(
-    op,
+  io.memoryUnit.out.rdata := MuxLookup(op, rdata(XLEN - 1, 0))(
     List(
       LSUOpType.lb  -> SignedExtend(rdata(7, 0), XLEN),
       LSUOpType.lh  -> SignedExtend(rdata(15, 0), XLEN),