From e897b0f00f92aa80eaff615f406f2c0ce8903a47 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Wed, 17 Jan 2024 14:03:30 +0800
Subject: [PATCH] =?UTF-8?q?=E6=8F=90=E4=BA=A4=E7=BC=93=E5=AD=98=E5=A4=A7?=
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---
 chisel/playground/src/pipeline/writeback/CommitBuffer.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/chisel/playground/src/pipeline/writeback/CommitBuffer.scala b/chisel/playground/src/pipeline/writeback/CommitBuffer.scala
index 3b7708e..a848c93 100644
--- a/chisel/playground/src/pipeline/writeback/CommitBuffer.scala
+++ b/chisel/playground/src/pipeline/writeback/CommitBuffer.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import cpu.defines.DEBUG
 
 class CommitBuffer(
-  depth: Int = 32)
+  depth: Int = 128)
     extends Module {
   val io = IO(new Bundle {
     val flush = Input(Bool())