修改mdu
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Liphen
parent
1ab2644cba
commit
e6decd7c82
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@ -6,133 +6,15 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class SignedDiv extends BlackBox with HasBlackBoxResource {
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val io = IO(new Bundle {
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val aclk = Input(Clock())
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// 除数
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val s_axis_divisor_tvalid = Input(Bool())
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val s_axis_divisor_tready = Output(Bool())
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val s_axis_divisor_tdata = Input(UInt(XLEN.W))
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// 被除数
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val s_axis_dividend_tvalid = Input(Bool())
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val s_axis_dividend_tready = Output(Bool())
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val s_axis_dividend_tdata = Input(UInt(XLEN.W))
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// 结果
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val m_axis_dout_tvalid = Output(Bool())
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val m_axis_dout_tdata = Output(UInt((2 * XLEN).W))
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})
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}
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class UnsignedDiv extends BlackBox with HasBlackBoxResource {
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val io = IO(new Bundle {
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val aclk = Input(Clock())
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// 除数
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val s_axis_divisor_tvalid = Input(Bool())
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val s_axis_divisor_tready = Output(Bool())
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val s_axis_divisor_tdata = Input(UInt(XLEN.W))
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// 被除数
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val s_axis_dividend_tvalid = Input(Bool())
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val s_axis_dividend_tready = Output(Bool())
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val s_axis_dividend_tdata = Input(UInt(XLEN.W))
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// 结果
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val m_axis_dout_tvalid = Output(Bool())
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val m_axis_dout_tdata = Output(UInt((2 * XLEN).W))
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})
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}
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class Div(implicit cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val src1 = Input(UInt(XLEN.W))
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val src2 = Input(UInt(XLEN.W))
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val signed = Input(Bool())
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val en = Input(Bool())
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val allow_to_go = Input(Bool())
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val ready = Output(Bool())
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val result = Output(UInt((2 * XLEN).W))
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})
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if (cpuConfig.build) {
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// TODO：未经测试
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val signedDiv = Module(new SignedDiv()).io
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val unsignedDiv = Module(new UnsignedDiv()).io
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signedDiv.aclk := clock
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unsignedDiv.aclk := clock
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// 0为被除数，1为除数
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val unsignedDiv_sent = Seq.fill(2)(RegInit(false.B))
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val unsignedDiv_done = RegInit(false.B)
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val signedDiv_sent = Seq.fill(2)(RegInit(false.B))
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val signedDiv_done = RegInit(false.B)
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when(unsignedDiv.s_axis_dividend_tready && unsignedDiv.s_axis_dividend_tvalid) {
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unsignedDiv_sent(0) := true.B
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}.elsewhen(io.ready && io.allow_to_go) {
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unsignedDiv_sent(0) := false.B
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}
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when(unsignedDiv.s_axis_divisor_tready && unsignedDiv.s_axis_divisor_tvalid) {
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unsignedDiv_sent(1) := true.B
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}.elsewhen(io.ready && io.allow_to_go) {
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unsignedDiv_sent(1) := false.B
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}
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when(signedDiv.s_axis_dividend_tready && signedDiv.s_axis_dividend_tvalid) {
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signedDiv_sent(0) := true.B
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}.elsewhen(io.ready && io.allow_to_go) {
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signedDiv_sent(0) := false.B
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}
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when(signedDiv.s_axis_divisor_tready && signedDiv.s_axis_divisor_tvalid) {
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signedDiv_sent(1) := true.B
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}.elsewhen(io.ready && io.allow_to_go) {
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signedDiv_sent(1) := false.B
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}
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when(signedDiv.m_axis_dout_tvalid && !io.allow_to_go) {
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signedDiv_done := true.B
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}.elsewhen(io.allow_to_go) {
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signedDiv_done := false.B
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}
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when(unsignedDiv.m_axis_dout_tvalid && !io.allow_to_go) {
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unsignedDiv_done := true.B
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}.elsewhen(io.allow_to_go) {
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unsignedDiv_done := false.B
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}
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// 被除数和除数的valid信号
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signedDiv.s_axis_dividend_tvalid := io.en && !signedDiv_sent(0) && io.signed
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signedDiv.s_axis_divisor_tvalid := io.en && !signedDiv_sent(1) && io.signed
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unsignedDiv.s_axis_dividend_tvalid := io.en && !unsignedDiv_sent(0) && !io.signed
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unsignedDiv.s_axis_divisor_tvalid := io.en && !unsignedDiv_sent(1) && !io.signed
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// 被除数和除数的值
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signedDiv.s_axis_dividend_tdata := io.src1
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signedDiv.s_axis_divisor_tdata := io.src2
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unsignedDiv.s_axis_dividend_tdata := io.src1
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unsignedDiv.s_axis_divisor_tdata := io.src2
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io.ready := Mux(
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io.signed,
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signedDiv.m_axis_dout_tvalid || signedDiv_done,
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unsignedDiv.m_axis_dout_tvalid || unsignedDiv_done
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)
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val signedRes =
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Cat(signedDiv.m_axis_dout_tdata(XLEN - 1, 0), signedDiv.m_axis_dout_tdata((2 * XLEN) - 1, XLEN))
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val unsignedRes =
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Cat(unsignedDiv.m_axis_dout_tdata(XLEN - 1, 0), unsignedDiv.m_axis_dout_tdata((2 * XLEN) - 1, XLEN))
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io.result := Mux(io.signed, signedRes, unsignedRes)
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} else {
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val cnt = RegInit(0.U(log2Ceil(cpuConfig.divClockNum + 1).W))
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cnt := MuxCase(
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cnt,
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Seq(
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(io.en && !io.ready) -> (cnt + 1.U),
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io.allow_to_go -> 0.U
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)
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)
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val div_signed = io.signed
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val dividend_signed = io.src1(XLEN - 1) & div_signed
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@ -147,19 +29,15 @@ class Div(implicit cpuConfig: CpuConfig) extends Module {
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val quotient_abs = dividend_abs / divisor_abs
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val remainder_abs = dividend_abs - quotient_abs * divisor_abs
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val quotient = RegInit(0.S(XLEN.W))
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val remainder = RegInit(0.S(XLEN.W))
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val quotient = WireInit(0.S(XLEN.W))
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val remainder = WireInit(0.S(XLEN.W))
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when(io.en) {
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quotient := Mux(quotient_signed, (-quotient_abs).asSInt, quotient_abs.asSInt)
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remainder := Mux(remainder_signed, (-remainder_abs).asSInt, remainder_abs.asSInt)
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when(io.src2 === 0.U) {
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quotient := (~0.U).asSInt
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remainder := io.src1.asSInt
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}
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}
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io.ready := cnt >= cpuConfig.divClockNum.U
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io.result := Cat(remainder, quotient)
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}
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}
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@ -10,9 +10,7 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val info = Input(new Info())
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val src_info = Input(new SrcInfo())
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val allow_to_go = Input(Bool())
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val ready = Output(Bool())
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val result = Output(UInt(XLEN.W))
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})
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@ -38,21 +36,16 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module {
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mul.src1 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._1(src1))))
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mul.src2 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._2(src2))))
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mul.en := valid && !is_div
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mul.allow_to_go := io.allow_to_go
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val srcDivConvertFunc = (x: UInt) =>
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Mux(is_w, Mux(MDUOpType.isDivSign(op), SignedExtend(x(31, 0), XLEN), ZeroExtend(x(31, 0), XLEN)), x)
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div.src1 := srcDivConvertFunc(src1)
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div.src2 := srcDivConvertFunc(src2)
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div.signed := MDUOpType.isDivSign(op)
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div.en := valid && is_div
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div.allow_to_go := io.allow_to_go
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val mul_result = Mux(op(1, 0) === MDUOpType.mul, mul.result(XLEN - 1, 0), mul.result(2 * XLEN - 1, XLEN))
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val div_result = Mux(op(1), div.result(2 * XLEN - 1, XLEN), div.result(XLEN - 1, 0))
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val result = Mux(is_div, div_result, mul_result)
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io.ready := Mux(is_div, div.ready, mul.ready)
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io.result := Mux(is_w, SignedExtend(result(31, 0), XLEN), result)
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}
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@ -6,63 +6,15 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class SignedMul extends BlackBox with HasBlackBoxResource {
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val io = IO(new Bundle {
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val CLK = Input(Clock())
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val CE = Input(Bool())
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val A = Input(UInt((XLEN + 1).W))
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val B = Input(UInt((XLEN + 1).W))
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val P = Output(UInt(((2 * XLEN) + 2).W))
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})
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}
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class Mul(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val src1 = Input(UInt((XLEN + 1).W))
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val src2 = Input(UInt((XLEN + 1).W))
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val en = Input(Bool())
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val allow_to_go = Input(Bool())
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val ready = Output(Bool())
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val result = Output(UInt((2 * XLEN).W))
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})
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if (cpuConfig.build) {
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// TODO:未经测试
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val signedMul = Module(new SignedMul()).io
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val cnt = RegInit(0.U(log2Ceil(cpuConfig.mulClockNum + 1).W))
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cnt := MuxCase(
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cnt,
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Seq(
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(io.en && !io.ready) -> (cnt + 1.U),
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io.allow_to_go -> 0.U
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)
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)
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signedMul.CLK := clock
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signedMul.CE := io.en
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signedMul.A := io.src1
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signedMul.B := io.src2
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io.ready := cnt >= cpuConfig.mulClockNum.U
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io.result := signedMul.P((2 * XLEN) - 1, 0)
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} else {
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val cnt = RegInit(0.U(log2Ceil(cpuConfig.mulClockNum + 1).W))
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cnt := MuxCase(
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cnt,
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Seq(
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(io.en && !io.ready) -> (cnt + 1.U),
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io.allow_to_go -> 0.U
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)
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)
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val signed = RegInit(0.U((2 * XLEN).W))
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when(io.en) {
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val signed = WireInit(0.U((2 * XLEN).W))
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signed := (io.src1.asSInt * io.src2.asSInt).asUInt
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}
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io.result := signed
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io.ready := cnt >= cpuConfig.mulClockNum.U
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}
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}
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