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修改csr的status掩码

This commit is contained in:
Liphen 2024-01-15 16:58:37 +08:00
parent b16eff1ba7
commit e37a05f5db
2 changed files with 8 additions and 7 deletions
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7
chisel/playground/src/cache/mmu/Tlb.scala vendored
View File

@ -108,7 +108,6 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
// 使用随机的方法替换TLB条目
val replace_index = new Counter(cpuConfig.tlbEntries)
replace_index.inc()
val ipage_fault = RegInit(false.B)
val dpage_fault = RegInit(false.B)
@ -248,7 +247,8 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
replace_entry.pteaddr := io.dcache.ptw.pte.bits.addr
tlbl2(replace_index.value) := replace_entry
itlb := replace_entry
immu_state := search_l1
replace_index.inc()
immu_state := search_l1
}
}
}
@ -343,7 +343,8 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
replace_entry.pteaddr := io.dcache.ptw.pte.bits.addr
tlbl2(replace_index.value) := replace_entry
dtlb := replace_entry
dmmu_state := search_l1
replace_index.inc()
dmmu_state := search_l1
}
}
}

8
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -125,8 +125,8 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
// Supervisor Trap Setup
// sstatus 状态寄存器，源自mstatus
val sstatusWmask = "hc6122".U(XLEN.W)
val sstatusRmask = sstatusWmask | "h8000000300018000".U
val sstatusWmask = "h00000000000c0122".U(XLEN.W)
val sstatusRmask = "h80000000000de762".U(XLEN.W)
// sedeleg 异常代理寄存器，未实现
// sideleg 中断代理寄存器，未实现
// sie 中断使能寄存器，源自mie
@ -178,8 +178,8 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
val mstatus_wmask = Mux(
VecInit(ModeM, ModeS, ModeU).contains(wdata.asTypeOf(new Mstatus).mpp),
"h0000000000021888".U(64.W),
"h0000000000020088".U(64.W)
"h00000000007e19aa".U(64.W),
"h00000000007e01aa".U(64.W)
)
// CSR reg map