From e3366efc563120644d50f03a94c715df1b7519b3 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Mon, 27 Nov 2023 16:01:17 +0800
Subject: [PATCH] =?UTF-8?q?fix(icache):=20=E4=BF=AE=E5=A4=8Dstall=E9=80=BB?=
 =?UTF-8?q?=E8=BE=91?=
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---
 chisel/playground/src/cache/ICache.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index 8834a24..8f6c574 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -42,14 +42,15 @@ class ICache(implicit config: CpuConfig) extends Module {
   io.axi.r.ready := true.B
 
   val acc_err = RegInit(false.B)
-  io.cpu.acc_err      := acc_err
-  io.cpu.icache_stall := false.B
+  io.cpu.acc_err := acc_err
   (0 until config.instFetchNum).foreach(i => {
     io.cpu.inst(i)       := saved(i).inst
     io.cpu.inst_valid(i) := saved(i).valid
   })
   io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
 
+  io.cpu.icache_stall := Mux(status === s_idle, io.cpu.req, status =/= s_save)
+
   switch(status) {
     is(s_idle) {
       acc_err := false.B