From e191004c0f909f2156793c5dc640b5608c093c1f Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Sat, 11 May 2024 15:49:59 +0800
Subject: [PATCH] =?UTF-8?q?fix(lsu):=20mem=E7=BA=A7=E8=AF=BB=E6=95=B0?=
 =?UTF-8?q?=E6=8D=AE=E5=A4=84=E7=90=86=E9=94=99=E8=AF=AF?=
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---
 .../playground/src/pipeline/execute/fu/Lsu.scala  | 15 ++++++++++-----
 .../src/pipeline/memory/MemoryUnit.scala          |  8 +++++++-
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
index 73009df..a2ce83d 100644
--- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
@@ -61,7 +61,7 @@ class Lsu extends Module {
     )
   }
 
-  val valid        = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go// && 无异常
+  val valid        = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go // && 无异常
   val op           = io.info.op
   val is_load      = valid && LSUOpType.isLoad(op)
   val is_store     = valid && LSUOpType.isStore(op)
@@ -74,8 +74,11 @@ class Lsu extends Module {
   val req_wmask    = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
   val rdata        = io.dataSram.rdata
 
+  val mem_op   = Wire(FuOpType())
+  val mem_addr = Wire(UInt(XLEN.W))
+
   val rdata64 = LookupTree(
-    addr(2, 0),
+    mem_addr(2, 0),
     List(
       "b000".U -> rdata(63, 0),
       "b001".U -> rdata(63, 8),
@@ -88,7 +91,7 @@ class Lsu extends Module {
     )
   )
   val rdata32 = LookupTree(
-    addr(1, 0),
+    mem_addr(1, 0),
     List(
       "b00".U -> rdata(31, 0),
       "b01".U -> rdata(31, 8),
@@ -98,7 +101,7 @@ class Lsu extends Module {
   )
   val rdata_result = if (XLEN == 32) rdata32 else rdata64
   val rdata_partial_result = LookupTree(
-    op,
+    mem_op,
     List(
       LSUOpType.lb  -> SignedExtend(rdata_result(7, 0), XLEN),
       LSUOpType.lh  -> SignedExtend(rdata_result(15, 0), XLEN),
@@ -126,5 +129,7 @@ class Lsu extends Module {
 
   val result = Wire(UInt(XLEN.W))
   result := Mux(partial_load, rdata_partial_result, rdata_result)
-  BoringUtils.addSource(result, "lsu_rdata")
+  BoringUtils.addSource(result, "mem_lsu_rdata")
+  BoringUtils.addSink(mem_op, "mem_lsu_op")
+  BoringUtils.addSink(mem_addr, "mem_lsu_addr")
 }
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index e6ba8f2..8ee94d6 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -16,7 +16,13 @@ class MemoryUnit extends Module {
   })
 
   val rdata = Wire(UInt(XLEN.W))
-  BoringUtils.addSink(rdata, "lsu_rdata")
+  val op    = Wire(FuOpType())
+  val addr  = Wire(UInt(XLEN.W))
+  op   := io.memoryStage.data.info.op
+  addr := io.memoryStage.data.src_info.src1_data + io.memoryStage.data.info.imm
+  BoringUtils.addSink(rdata, "mem_lsu_rdata")
+  BoringUtils.addSource(op, "mem_lsu_op")
+  BoringUtils.addSource(addr, "mem_lsu_addr")
 
   io.decodeUnit.wen   := io.writeBackStage.data.info.reg_wen
   io.decodeUnit.waddr := io.writeBackStage.data.info.reg_waddr