From df724507476877177e1351cfce3d7d504b3a1ee1 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 17 Jan 2024 16:10:00 +0800 Subject: [PATCH] =?UTF-8?q?fix(idu):=20=E5=A2=9E=E5=8A=A0tval=E6=9D=A5?= =?UTF-8?q?=E6=BA=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/decode/DecodeUnit.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/decode/DecodeUnit.scala b/chisel/playground/src/pipeline/decode/DecodeUnit.scala index b79822b..7e55e40 100644 --- a/chisel/playground/src/pipeline/decode/DecodeUnit.scala +++ b/chisel/playground/src/pipeline/decode/DecodeUnit.scala @@ -134,11 +134,14 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall && info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr + // tval注意先后顺序 io.executeStage.inst0.ex.tval := MuxCase( 0.U, Seq( - pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(0), + io.executeStage.inst0.ex.exception(instrPageFault) -> pc(0), + io.executeStage.inst0.ex.exception(instrAccessFault) -> pc(0), !info(0).inst_legal -> info(0).inst, + pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(0), (io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target ) ) @@ -182,8 +185,10 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep io.executeStage.inst1.ex.tval := MuxCase( 0.U, Seq( - pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(1), + io.executeStage.inst1.ex.exception(instrPageFault) -> pc(1), + io.executeStage.inst1.ex.exception(instrAccessFault) -> pc(1), !info(1).inst_legal -> info(1).inst, + pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(1), (io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target ) )