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修改exu

This commit is contained in:
Liphen 2023-11-20 22:31:03 +08:00
parent 2d36926238
commit d9b66b2468
4 changed files with 126 additions and 137 deletions
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1
chisel/playground/src/defines/Bundles.scala
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@ -34,6 +34,7 @@ class InstInfo extends Bundle {
val imm = UInt(XLEN.W) val imm = UInt(XLEN.W)
val dual_issue = Bool() val dual_issue = Bool()
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
val mem_wreg = Bool()
} }
class MemRead extends Bundle { class MemRead extends Bundle {

1
chisel/playground/src/pipeline/decoder/Decoder.scala
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@ -67,4 +67,5 @@ class Decoder extends Module with HasInstrType {
) )
io.out.inst_info.dual_issue := false.B io.out.inst_info.dual_issue := false.B
io.out.inst_info.inst := inst io.out.inst_info.inst := inst
io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
} }

260
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
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@ -1,151 +1,139 @@
// package cpu.pipeline.execute package cpu.pipeline.execute
// import chisel3._ import chisel3._
// import chisel3.util._ import chisel3.util._
// import cpu.CpuConfig import cpu.CpuConfig
// import cpu.defines._ import cpu.defines._
// import cpu.defines.Const._ import cpu.defines.Const._
// import cpu.pipeline.decoder.RegWrite import cpu.pipeline.decoder.RegWrite
// import cpu.pipeline.memory.{ExecuteUnitMemoryUnit, CsrInfo} import cpu.pipeline.memory.{CsrInfo, ExecuteUnitMemoryUnit}
// import cpu.pipeline.fetch.ExecuteUnitBranchPredictor import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
// class ExecuteUnit(implicit val config: CpuConfig) extends Module { class ExecuteUnit(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle { val io = IO(new Bundle {
// val ctrl = new ExecuteCtrl() val ctrl = new ExecuteCtrl()
// val executeStage = Input(new DecoderUnitExecuteUnit()) val executeStage = Input(new DecoderUnitExecuteUnit())
// val csr = Flipped(new CsrExecuteUnit()) val csr = Flipped(new CsrExecuteUnit())
// val bpu = new ExecuteUnitBranchPredictor() val bpu = new ExecuteUnitBranchPredictor()
// val fetchUnit = Output(new Bundle { val fetchUnit = Output(new Bundle {
// val branch = Bool() val branch = Bool()
// val target = UInt(PC_WID.W) val target = UInt(PC_WID.W)
// }) })
// val decoderUnit = new Bundle { val decoderUnit = new Bundle {
// val forward = Output( val forward = Output(
// Vec( Vec(
// config.fuNum, config.fuNum,
// new Bundle { new Bundle {
// val exe = new RegWrite() val exe = new RegWrite()
// val exe_mem_wreg = Bool() val exe_mem_wreg = Bool()
// }, }
// ), )
// ) )
// val inst0_bd = Input(Bool()) val inst0_bd = Input(Bool())
// } }
// val memoryStage = Output(new ExecuteUnitMemoryUnit()) val memoryStage = Output(new ExecuteUnitMemoryUnit())
})
// val statistic = if (!config.build) Some(new BranchPredictorUnitStatistic()) else None val fu = Module(new Fu()).io
// }) val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
// val fu = Module(new Fu()).io io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
// val accessMemCtrl = Module(new ExeAccessMemCtrl()).io io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
io.ctrl.branch := io.ctrl.allow_to_go &&
(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
// io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data
// io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr io.csr.in.inst_info(0) := Mux(
// io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg !io.executeStage.inst0.ex.flush_req,
// io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr io.executeStage.inst0.inst_info,
// io.ctrl.branch := io.ctrl.allow_to_go && 0.U.asTypeOf(new InstInfo())
// (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) )
io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info
// io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data // input accessMemCtrl
// io.csr.in.inst_info(0) := Mux( accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
// !io.executeStage.inst0.ex.flush_req, accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
// io.executeStage.inst0.inst_info, accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
// 0.U.asTypeOf(new InstInfo()), accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
// ) accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
// io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
// // input accessMemCtrl // input fu
// accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info fu.ctrl <> io.ctrl.fu
// accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info fu.inst(0).pc := io.executeStage.inst0.pc
// accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex fu.inst(0).mul_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
// accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info !MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
// accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info fu.inst(0).div_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
// accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
fu.inst(0).inst_info := io.executeStage.inst0.inst_info
fu.inst(0).src_info := io.executeStage.inst0.src_info
fu.inst(0).ex.in :=
Mux(io.executeStage.inst0.inst_info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
fu.inst(1).pc := io.executeStage.inst1.pc
fu.inst(1).mul_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
!MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
fu.inst(1).div_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
fu.inst(1).inst_info := io.executeStage.inst1.inst_info
fu.inst(1).src_info := io.executeStage.inst1.src_info
fu.inst(1).ex.in := io.executeStage.inst1.ex
fu.csr_rdata := io.csr.out.csr_rdata
fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
// // input fu io.bpu.pc := io.executeStage.inst0.pc
// fu.ctrl <> io.ctrl.fu io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
// fu.inst(0).pc := io.executeStage.inst0.pc io.bpu.branch := fu.branch.branch
// fu.inst(0).hilo_wen := io.executeStage.inst0.inst_info.whilo io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
// fu.inst(0).mul_en := io.executeStage.inst0.inst_info.mul
// fu.inst(0).div_en := io.executeStage.inst0.inst_info.div
// fu.inst(0).inst_info := io.executeStage.inst0.inst_info
// fu.inst(0).src_info := io.executeStage.inst0.src_info
// fu.inst(0).ex.in :=
// Mux(io.executeStage.inst0.inst_info.fusel === FU_MEM, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
// fu.inst(1).pc := io.executeStage.inst1.pc
// fu.inst(1).hilo_wen := io.executeStage.inst1.inst_info.whilo
// fu.inst(1).mul_en := io.executeStage.inst1.inst_info.mul
// fu.inst(1).div_en := io.executeStage.inst1.inst_info.div
// fu.inst(1).inst_info := io.executeStage.inst1.inst_info
// fu.inst(1).src_info := io.executeStage.inst1.src_info
// fu.inst(1).ex.in := io.executeStage.inst1.ex
// fu.csr_rdata := io.csr.out.csr_rdata
// fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
// io.bpu.pc := io.executeStage.inst0.pc io.fetchUnit.branch := io.ctrl.allow_to_go &&
// io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
// io.bpu.branch := fu.branch.branch io.fetchUnit.target := MuxCase(
// io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
Seq(
(fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
(fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U),
(io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data
)
)
// io.fetchUnit.branch := io.ctrl.allow_to_go && io.ctrl.fu_stall := fu.stall_req
// (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
// io.fetchUnit.target := MuxCase(
// io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
// Seq(
// (fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
// (fu.branch.pred_fail && !fu.branch.branch) -> Mux(
// io.decoderUnit.inst0_bd || io.executeStage.inst1.ex.bd,
// io.executeStage.inst0.pc + 8.U,
// io.executeStage.inst0.pc + 4.U,
// ),
// (io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data,
// ),
// )
// io.ctrl.fu_stall := fu.stall_req io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
// io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en io.memoryStage.inst0.pc := io.executeStage.inst0.pc
// io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
// io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen io.memoryStage.inst0.rd_info.wdata := fu.inst(0).result
// io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr io.memoryStage.inst0.ex := Mux(
// io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata io.executeStage.inst0.inst_info.fusel === FuType.lsu,
// io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel) accessMemCtrl.inst(0).ex.out,
// io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info fu.inst(0).ex.out
// io.memoryStage.inst0.mem.llbit := fu.llbit )
io.memoryStage.inst0.csr := io.csr.out.debug
// io.memoryStage.inst0.pc := io.executeStage.inst0.pc io.memoryStage.inst1.pc := io.executeStage.inst1.pc
// io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
// io.memoryStage.inst0.rd_info.wdata := fu.inst(0).result io.memoryStage.inst1.rd_info.wdata := fu.inst(1).result
// io.memoryStage.inst0.ex := Mux( io.memoryStage.inst1.ex := Mux(
// io.executeStage.inst0.inst_info.fusel === FU_MEM, io.executeStage.inst1.inst_info.fusel === FuType.lsu,
// accessMemCtrl.inst(0).ex.out, accessMemCtrl.inst(1).ex.out,
// fu.inst(0).ex.out, fu.inst(1).ex.out
// ) )
// io.memoryStage.inst0.csr := io.csr.out.debug
// io.memoryStage.inst1.pc := io.executeStage.inst1.pc io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
// io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
// io.memoryStage.inst1.rd_info.wdata := fu.inst(1).result io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata
// io.memoryStage.inst1.ex := Mux( io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
// io.executeStage.inst1.inst_info.fusel === FU_MEM,
// accessMemCtrl.inst(1).ex.out,
// fu.inst(1).ex.out,
// )
// io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
// io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
// io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata
// io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
}
// io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
// io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
// io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata
// io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
// // ===----------------------------------------------------------------===
// // statistic
// // ===----------------------------------------------------------------===
// if (!config.build) {
// io.statistic.get <> fu.statistic.get
// }
// }

1
chisel/playground/src/pipeline/memory/MemoryStage.scala
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@ -29,7 +29,6 @@ class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
val addr = UInt(DATA_ADDR_WID.W) val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(DATA_WID.W) val wdata = UInt(DATA_WID.W)
val sel = Vec(config.fuNum, Bool()) val sel = Vec(config.fuNum, Bool())
val llbit = Bool()
} }
} }