修改exu
This commit is contained in:
Liphen
parent
2d36926238
commit
d9b66b2468
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@ -34,6 +34,7 @@ class InstInfo extends Bundle {
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val imm = UInt(XLEN.W)
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val dual_issue = Bool()
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val inst = UInt(INST_WID.W)
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val mem_wreg = Bool()
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}
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class MemRead extends Bundle {
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@ -67,4 +67,5 @@ class Decoder extends Module with HasInstrType {
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)
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io.out.inst_info.dual_issue := false.B
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io.out.inst_info.inst := inst
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io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
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}
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@ -1,151 +1,139 @@
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// package cpu.pipeline.execute
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package cpu.pipeline.execute
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// import chisel3._
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// import chisel3.util._
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// import cpu.CpuConfig
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// import cpu.defines._
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// import cpu.defines.Const._
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// import cpu.pipeline.decoder.RegWrite
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// import cpu.pipeline.memory.{ExecuteUnitMemoryUnit, CsrInfo}
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// import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.pipeline.decoder.RegWrite
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import cpu.pipeline.memory.{CsrInfo, ExecuteUnitMemoryUnit}
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import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
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// class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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// val io = IO(new Bundle {
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// val ctrl = new ExecuteCtrl()
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// val executeStage = Input(new DecoderUnitExecuteUnit())
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// val csr = Flipped(new CsrExecuteUnit())
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// val bpu = new ExecuteUnitBranchPredictor()
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// val fetchUnit = Output(new Bundle {
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// val branch = Bool()
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// val target = UInt(PC_WID.W)
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// })
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// val decoderUnit = new Bundle {
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// val forward = Output(
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// Vec(
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// config.fuNum,
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// new Bundle {
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// val exe = new RegWrite()
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// val exe_mem_wreg = Bool()
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// },
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// ),
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// )
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// val inst0_bd = Input(Bool())
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// }
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// val memoryStage = Output(new ExecuteUnitMemoryUnit())
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class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ctrl = new ExecuteCtrl()
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val executeStage = Input(new DecoderUnitExecuteUnit())
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val csr = Flipped(new CsrExecuteUnit())
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val bpu = new ExecuteUnitBranchPredictor()
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val fetchUnit = Output(new Bundle {
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val branch = Bool()
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val target = UInt(PC_WID.W)
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})
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val decoderUnit = new Bundle {
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val forward = Output(
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Vec(
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config.fuNum,
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new Bundle {
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val exe = new RegWrite()
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val exe_mem_wreg = Bool()
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}
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)
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)
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val inst0_bd = Input(Bool())
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}
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val memoryStage = Output(new ExecuteUnitMemoryUnit())
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})
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// val statistic = if (!config.build) Some(new BranchPredictorUnitStatistic()) else None
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// })
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val fu = Module(new Fu()).io
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val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
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// val fu = Module(new Fu()).io
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// val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
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io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
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io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
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io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
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io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
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io.ctrl.branch := io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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// io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
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// io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
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// io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
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// io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
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// io.ctrl.branch := io.ctrl.allow_to_go &&
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// (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data
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io.csr.in.inst_info(0) := Mux(
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!io.executeStage.inst0.ex.flush_req,
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io.executeStage.inst0.inst_info,
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0.U.asTypeOf(new InstInfo())
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)
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io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info
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// io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data
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// io.csr.in.inst_info(0) := Mux(
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// !io.executeStage.inst0.ex.flush_req,
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// io.executeStage.inst0.inst_info,
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// 0.U.asTypeOf(new InstInfo()),
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// )
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// io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info
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// input accessMemCtrl
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accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
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accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
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accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
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accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
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accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
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accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
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// // input accessMemCtrl
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// accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
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// accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
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// accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
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// accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
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// accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
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// accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
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// input fu
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fu.ctrl <> io.ctrl.fu
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fu.inst(0).pc := io.executeStage.inst0.pc
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fu.inst(0).mul_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
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!MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
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fu.inst(0).div_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
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fu.inst(0).inst_info := io.executeStage.inst0.inst_info
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fu.inst(0).src_info := io.executeStage.inst0.src_info
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fu.inst(0).ex.in :=
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Mux(io.executeStage.inst0.inst_info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
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fu.inst(1).pc := io.executeStage.inst1.pc
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fu.inst(1).mul_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
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!MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
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fu.inst(1).div_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
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fu.inst(1).inst_info := io.executeStage.inst1.inst_info
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fu.inst(1).src_info := io.executeStage.inst1.src_info
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fu.inst(1).ex.in := io.executeStage.inst1.ex
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fu.csr_rdata := io.csr.out.csr_rdata
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fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
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// // input fu
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// fu.ctrl <> io.ctrl.fu
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// fu.inst(0).pc := io.executeStage.inst0.pc
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// fu.inst(0).hilo_wen := io.executeStage.inst0.inst_info.whilo
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// fu.inst(0).mul_en := io.executeStage.inst0.inst_info.mul
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// fu.inst(0).div_en := io.executeStage.inst0.inst_info.div
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// fu.inst(0).inst_info := io.executeStage.inst0.inst_info
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// fu.inst(0).src_info := io.executeStage.inst0.src_info
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// fu.inst(0).ex.in :=
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// Mux(io.executeStage.inst0.inst_info.fusel === FU_MEM, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
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// fu.inst(1).pc := io.executeStage.inst1.pc
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// fu.inst(1).hilo_wen := io.executeStage.inst1.inst_info.whilo
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// fu.inst(1).mul_en := io.executeStage.inst1.inst_info.mul
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// fu.inst(1).div_en := io.executeStage.inst1.inst_info.div
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// fu.inst(1).inst_info := io.executeStage.inst1.inst_info
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// fu.inst(1).src_info := io.executeStage.inst1.src_info
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// fu.inst(1).ex.in := io.executeStage.inst1.ex
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// fu.csr_rdata := io.csr.out.csr_rdata
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// fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
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io.bpu.pc := io.executeStage.inst0.pc
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io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
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io.bpu.branch := fu.branch.branch
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io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
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// io.bpu.pc := io.executeStage.inst0.pc
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// io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
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// io.bpu.branch := fu.branch.branch
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// io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
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io.fetchUnit.branch := io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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io.fetchUnit.target := MuxCase(
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io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
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Seq(
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(fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
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(fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U),
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(io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data
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)
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)
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// io.fetchUnit.branch := io.ctrl.allow_to_go &&
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// (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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// io.fetchUnit.target := MuxCase(
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// io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
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// Seq(
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// (fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
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// (fu.branch.pred_fail && !fu.branch.branch) -> Mux(
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// io.decoderUnit.inst0_bd || io.executeStage.inst1.ex.bd,
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// io.executeStage.inst0.pc + 8.U,
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// io.executeStage.inst0.pc + 4.U,
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// ),
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// (io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data,
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// ),
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// )
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io.ctrl.fu_stall := fu.stall_req
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// io.ctrl.fu_stall := fu.stall_req
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io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
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// io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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// io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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// io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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// io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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// io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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// io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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// io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
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// io.memoryStage.inst0.mem.llbit := fu.llbit
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io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
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io.memoryStage.inst0.rd_info.wdata := fu.inst(0).result
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io.memoryStage.inst0.ex := Mux(
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io.executeStage.inst0.inst_info.fusel === FuType.lsu,
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accessMemCtrl.inst(0).ex.out,
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fu.inst(0).ex.out
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)
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io.memoryStage.inst0.csr := io.csr.out.debug
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// io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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// io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
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// io.memoryStage.inst0.rd_info.wdata := fu.inst(0).result
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// io.memoryStage.inst0.ex := Mux(
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// io.executeStage.inst0.inst_info.fusel === FU_MEM,
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// accessMemCtrl.inst(0).ex.out,
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// fu.inst(0).ex.out,
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// )
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// io.memoryStage.inst0.csr := io.csr.out.debug
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io.memoryStage.inst1.pc := io.executeStage.inst1.pc
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io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
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io.memoryStage.inst1.rd_info.wdata := fu.inst(1).result
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io.memoryStage.inst1.ex := Mux(
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io.executeStage.inst1.inst_info.fusel === FuType.lsu,
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accessMemCtrl.inst(1).ex.out,
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fu.inst(1).ex.out
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)
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// io.memoryStage.inst1.pc := io.executeStage.inst1.pc
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// io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
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// io.memoryStage.inst1.rd_info.wdata := fu.inst(1).result
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// io.memoryStage.inst1.ex := Mux(
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// io.executeStage.inst1.inst_info.fusel === FU_MEM,
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// accessMemCtrl.inst(1).ex.out,
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// fu.inst(1).ex.out,
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// )
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io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
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io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
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io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata
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io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
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// io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
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// io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
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// io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata
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// io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
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// io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
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// io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
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// io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata
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// io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
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// // ===----------------------------------------------------------------===
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// // statistic
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// // ===----------------------------------------------------------------===
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// if (!config.build) {
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// io.statistic.get <> fu.statistic.get
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// }
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// }
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io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
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io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
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io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata
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io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
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}
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@ -29,7 +29,6 @@ class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
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val addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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val sel = Vec(config.fuNum, Bool())
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val llbit = Bool()
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}
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}
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