构建目录大致框架
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Liphen
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prj/simulation/icarus/
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user/src/test.v
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user/sim/wave.vcd
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user/sim/testbench.v
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img
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{
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"toolChain": "xilinx",
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题目：面向教学的计算机底层硬件系统设计与实现
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毕业设计地点：校内
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要求：针对教学需要，使用硬件描述语言设计基于RISC-V指令集的多级流水线处理器，使其适合数字电路与计算机组成原理的教学实验。
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重点难点：硬件描述语言的应用；教学化设计；数字电路与计算机组成原理实验的连续性与贯通性。
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# 指导手册框架
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一、实验介绍
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二、实验目的
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三、实验要求
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四、实验步骤
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# 实验设计
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#### 数字电路
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- 认识Verilog
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- ##### 组合逻辑电路基础实验
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- 全加器
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- 超前进位电路
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- 加减法器
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- 数据选择器
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- 译码器
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- 思考题：编码器
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- ##### 时序逻辑电路基础实验
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- 触发器
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- 边沿型/电平型D触发器，门电路实现
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- 思考题：其他触发器
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- 寄存器实验
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- 计数器
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- ##### 综合设计实验
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- 定时与分频实验
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- 数码管实验
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- 桶型移位器
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- 多功能ALU设计实验
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- 寄存器堆与运算器设计实验
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- 取指令与指令译码实验
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#### 计算机组成原理
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- 认识Chisel
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- 对比下Chisel和Verilog
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- 设计一个简单的单周期CPU
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- 只支持一些简单的、基础的、有代表性的指令，如支持跑通冒泡排序
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- ##### 计算机体系结构实验
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- 不考虑相关冲突的流水线CPU
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- 指令相关与流水线冲突
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- 介绍为什么会发生冲突
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- 阻塞技术
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- 前递技术
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- 在流水线中添加运算类指令
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- 让学生参照已经实现的指令添加一条新指令
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- 在流水线中添加转移指令
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- 在流水线中添加访存指令
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- 例外与中断的支持
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## 一、实验介绍
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## 二、实验目的
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## 三、实验要求
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## 四、实验步骤
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||||
Loading…
Reference in New Issue