完成lab1大致实验框架

实现R型运算类指令的理想流水线设计

chisel/playground/src/defines/Bundles.scala

@@ -23,16 +23,11 @@ class RdInfo extends Bundle {
 
 class Info extends Bundle {
   val valid      = Bool()
-  val src1_ren   = Bool()
   val src1_raddr = UInt(REG_ADDR_WID.W)
-  val src2_ren   = Bool()
   val src2_raddr = UInt(REG_ADDR_WID.W)
-  val fusel      = FuType()
   val op         = FuOpType()
   val reg_wen    = Bool()
   val reg_waddr  = UInt(REG_ADDR_WID.W)
-  val imm        = UInt(XLEN.W)
-  val inst       = UInt(XLEN.W)
 }
 
 class SrcReadSignal extends Bundle {

chisel/playground/src/defines/isa/Instructions.scala

@@ -15,13 +15,6 @@ trait HasInstrType {
   def isRegWen(instrType: UInt): Bool = instrType(2)
 }
 
-object SrcType {
-  def reg     = "b0".U
-  def pc      = "b1".U
-  def imm     = "b1".U
-  def apply() = UInt(1.W)
-}
-
 object FuType {
   def num     = 1
   def alu     = 0.U // arithmetic logic unit

chisel/playground/src/pipeline/decode/DecodeUnit.scala

@@ -26,18 +26,9 @@ class DecodeUnit extends Module {
   io.regfile.src1.raddr := info.src1_raddr
   io.regfile.src2.raddr := info.src2_raddr
 
-  io.executeStage.data.pc   := pc
+  io.executeStage.data.pc                 := pc
-  io.executeStage.data.info := info
+  io.executeStage.data.info               := info
-  io.executeStage.data.src_info.src1_data := MuxCase(
+  io.executeStage.data.src_info.src1_data := io.regfile.src1.rdata
-    SignedExtend(pc, XLEN),
+  io.executeStage.data.src_info.src2_data := io.regfile.src2.rdata
-    Seq(
+
-      info.src1_ren                      -> io.regfile.src1.rdata,
-      (info.inst(6, 0) === "b0110111".U) -> 0.U
-    )
-  )
-  io.executeStage.data.src_info.src2_data := Mux(
-    info.src2_ren,
-    io.regfile.src2.rdata,
-    info.imm
-  )
 }

chisel/playground/src/pipeline/decode/Decoder.scala

@@ -21,38 +21,12 @@ class Decoder extends Module with HasInstrType {
   val instrType :: fuType :: fuOpType :: Nil =
     ListLookup(inst, Instructions.DecodeDefault, Instructions.DecodeTable)
 
-  val srcTypeTable = Seq(
-    InstrI  -> (SrcType.reg, SrcType.imm),
-    InstrR  -> (SrcType.reg, SrcType.reg),
-    InstrS  -> (SrcType.reg, SrcType.reg),
-    InstrB  -> (SrcType.reg, SrcType.reg),
-    InstrU  -> (SrcType.pc, SrcType.imm),
-    InstrJ  -> (SrcType.pc, SrcType.imm),
-    InstrN  -> (SrcType.pc, SrcType.imm)
-  )
-  val src1Type = LookupTree(instrType, srcTypeTable.map(p => (p._1, p._2._1)))
-  val src2Type = LookupTree(instrType, srcTypeTable.map(p => (p._1, p._2._2)))
-
   val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
 
   io.out.info.valid      := false.B
-  io.out.info.inst       := inst
+  io.out.info.src1_raddr := rs
-  io.out.info.src1_ren   := src1Type === SrcType.reg
+  io.out.info.src2_raddr := rt
-  io.out.info.src1_raddr := Mux(io.out.info.src1_ren, rs, 0.U)
-  io.out.info.src2_ren   := src2Type === SrcType.reg
-  io.out.info.src2_raddr := Mux(io.out.info.src2_ren, rt, 0.U)
-  io.out.info.fusel      := fuType
   io.out.info.op         := fuOpType
   io.out.info.reg_wen    := isRegWen(instrType)
   io.out.info.reg_waddr  := Mux(isRegWen(instrType), rd, 0.U)
-  io.out.info.imm := LookupTree(
-    instrType,
-    Seq(
-      InstrI  -> SignedExtend(inst(31, 20), XLEN),
-      InstrS  -> SignedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN),
-      InstrB  -> SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN),
-      InstrU  -> SignedExtend(Cat(inst(31, 12), 0.U(12.W)), XLEN),
-      InstrJ  -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
-    )
-  )
 }

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -14,10 +14,6 @@ class ExecuteUnit extends Module {
     val dataSram     = new DataSram()
   })
 
-
-  val valid = io.executeStage.data.info.valid
-  val fusel = io.executeStage.data.info.fusel
-
   val fu = Module(new Fu()).io
   fu.data.pc       := io.executeStage.data.pc
   fu.data.info     := io.executeStage.data.info