增加sfence.vma

chisel/playground/src/Core.scala

@@ -40,6 +40,7 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
   tlb.icache <> io.inst.tlb
   tlb.dcache <> io.data.tlb
   tlb.csr <> csr.tlb
+  tlb.sfence_vma <> memoryUnit.ctrl.sfence_vma
 
   ctrl.decodeUnit <> decodeUnit.ctrl
   ctrl.executeUnit <> executeUnit.ctrl

chisel/playground/src/cache/mmu/Tlb.scala

@@ -49,13 +49,10 @@ class Tlb_DCache extends Tlb_ICache {
 
 class Tlb extends Module with HasTlbConst with HasCSRConst {
   val io = IO(new Bundle {
-    val icache = new Tlb_ICache()
+    val icache     = new Tlb_ICache()
-    val dcache = new Tlb_DCache()
+    val dcache     = new Tlb_DCache()
-    val csr    = Flipped(new CsrTlb())
+    val csr        = Flipped(new CsrTlb())
-    // val fence_vma = Input(new Bundle {
+    val sfence_vma = Input(new MouTlb())
-    //   val src1 = UInt(XLEN.W)
-    //   val src2 = UInt(XLEN.W)
-    // })
   })
 
   val satp    = io.csr.satp.asTypeOf(satpBundle)
@@ -302,6 +299,58 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
     }
   }
 
+  val src1 = io.sfence_vma.src_info.src1_data
+  val src2 = io.sfence_vma.src_info.src2_data
+  when(io.sfence_vma.valid) {
+    when(!src1.orR && !src2.orR) {
+      // 将所有tlb的有效位置为0
+      itlb.flag.v := false.B
+      dtlb.flag.v := false.B
+      for (i <- 0 until cpuConfig.tlbEntries) {
+        tlbl2(i).flag.v := false.B
+      }
+    }.elsewhen(!src1.orR && src2.orR) {
+      // 将asid一致的且g不为1的tlb的有效位置为0
+      when(itlb.asid === src2 && !itlb.flag.g) {
+        itlb.flag.v := false.B
+      }
+      when(dtlb.asid === src2 && !dtlb.flag.g) {
+        dtlb.flag.v := false.B
+      }
+      for (i <- 0 until cpuConfig.tlbEntries) {
+        when(tlbl2(i).asid === src2 && !tlbl2(i).flag.g) {
+          tlbl2(i).flag.v := false.B
+        }
+      }
+    }.elsewhen(src1.orR && !src2.orR) {
+      // 将vpn一致的tlb的有效位置为0
+      when(itlb.vpn === src1) {
+        itlb.flag.v := false.B
+      }
+      when(dtlb.vpn === src1) {
+        dtlb.flag.v := false.B
+      }
+      for (i <- 0 until cpuConfig.tlbEntries) {
+        when(tlbl2(i).vpn === src1) {
+          tlbl2(i).flag.v := false.B
+        }
+      }
+    }.elsewhen(src1.orR && src2.orR) {
+      // 将asid一致的且vpn一致的tlb的有效位置为0，g为1的除外
+      when(itlb.asid === src2 && itlb.vpn === src1 && !itlb.flag.g) {
+        itlb.flag.v := false.B
+      }
+      when(dtlb.asid === src2 && dtlb.vpn === src1 && !dtlb.flag.g) {
+        dtlb.flag.v := false.B
+      }
+      for (i <- 0 until cpuConfig.tlbEntries) {
+        when(tlbl2(i).asid === src2 && tlbl2(i).vpn === src1 && !tlbl2(i).flag.g) {
+          tlbl2(i).flag.v := false.B
+        }
+      }
+    }
+  }
+
   io.icache.uncached := AddressSpace.isMMIO(io.icache.addr)
   io.icache.ptag     := Mux(vm_enabled, itlb.ppn, io.icache.addr(PADDR_WID - 1, pageOffsetLen))
   io.icache.paddr    := Cat(io.icache.ptag, io.icache.addr(pageOffsetLen - 1, 0))

chisel/playground/src/defines/Bundles.scala

@@ -6,6 +6,7 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 import icache.mmu.{Tlb_DCache, Tlb_ICache}
+import cpu.pipeline.memory.Mou
 
 class ExceptionInfo extends Bundle {
   val exception = Vec(EXC_WID, Bool())
@@ -88,6 +89,11 @@ class ExecuteCtrl(implicit val cpuConfig: CpuConfig) extends Bundle {
   val fu = new ExecuteFuCtrl()
 }
 
+class MouTlb extends Bundle {
+  val valid    = Bool()
+  val src_info = new SrcInfo()
+}
+
 class MemoryCtrl extends Bundle {
   val flush     = Output(Bool())
   val mem_stall = Output(Bool())
@@ -98,6 +104,8 @@ class MemoryCtrl extends Bundle {
   // to cache
   val fence_i                 = Output(Bool())
   val complete_single_request = Output(Bool()) // to dcache
+  // to tlb
+  val sfence_vma = Output(new MouTlb())
 }
 
 class WriteBackCtrl extends Bundle {

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -17,7 +17,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
       val flush  = Bool()
       val target = UInt(XLEN.W)
     })
-    val decodeUnit    = Output(Vec(cpuConfig.commitNum, new RegWrite()))
+    val decodeUnit     = Output(Vec(cpuConfig.commitNum, new RegWrite()))
     val csr            = Flipped(new CsrMemoryUnit())
     val writeBackStage = Output(new MemoryUnitWriteBackUnit())
     val dataMemory     = new Lsu_DataMemory()
@@ -128,6 +128,9 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
   io.ctrl.fence_i                 := mou.out.fence_i
   io.ctrl.complete_single_request := lsu.memoryUnit.out.complete_single_request
 
+  io.ctrl.sfence_vma.valid    := mou.out.sfence_vma
+  io.ctrl.sfence_vma.src_info := io.memoryStage.inst0.src_info
+
   io.fetchUnit.flush  := io.ctrl.allow_to_go && (io.csr.out.flush || mou.out.flush)
   io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.target, mou.out.target)
 }

chisel/playground/src/pipeline/memory/Mou.scala

@@ -12,17 +12,20 @@ class Mou extends Module {
       val pc   = UInt(XLEN.W)
     })
     val out = Output(new Bundle {
-      val flush   = Bool()
+      val flush      = Bool()
-      val fence_i = Bool()
+      val fence_i    = Bool()
-      val target  = UInt(XLEN.W)
+      val sfence_vma = Bool()
+      val target     = UInt(XLEN.W)
     })
   })
 
-  val valid   = io.in.info.valid && io.in.info.fusel === FuType.mou
+  val valid      = io.in.info.valid && io.in.info.fusel === FuType.mou
-  val fence_i = valid && io.in.info.op === MOUOpType.fencei
+  val fence_i    = valid && io.in.info.op === MOUOpType.fencei
+  val sfence_vma = valid && io.in.info.op === MOUOpType.sfence_vma
 
-  io.out.flush   := valid
+  io.out.flush      := valid
-  io.out.fence_i := fence_i
+  io.out.fence_i    := fence_i
-  io.out.target  := io.in.pc + 4.U
+  io.out.sfence_vma := sfence_vma
+  io.out.target     := io.in.pc + 4.U
 
 }