From cc842aff6eef85c867c8256bd17f647c0cb4f999 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Wed, 22 Nov 2023 14:48:00 +0800
Subject: [PATCH] =?UTF-8?q?id=E7=BA=A7=E5=A2=9E=E5=8A=A0=E6=9B=B4=E5=A4=9A?=
 =?UTF-8?q?=E4=BE=8B=E5=A4=96?=
MIME-Version: 1.0
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---
 chisel/playground/src/defines/Bundles.scala   |  3 +-
 .../src/pipeline/decoder/DecoderUnit.scala    | 43 ++++++++++++++++---
 .../src/pipeline/memory/MemoryUnit.scala      |  6 +--
 3 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index d17b574..e37979b 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -9,7 +9,8 @@ import cpu.CpuConfig
 class ExceptionInfo extends Bundle {
   val flush_req = Bool()
   val excode    = Vec(EXCODE_WID, Bool())
-  val int       = Vec(INT_WID, Bool())
+  val interrupt = Vec(INT_WID, Bool())
+  val tval      = UInt(XLEN.W)
 }
 
 class SrcInfo extends Bundle {
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 30a4b45..581d00f 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -25,7 +25,7 @@ class DataForwardToDecoderUnit extends Bundle {
   val mem      = new RegWrite()
 }
 
-class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO {
+class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
   val io = IO(new Bundle {
     // 输入
     val instFifo = new InstFifoDecoderUnit()
@@ -104,6 +104,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   val pc        = io.instFifo.inst.map(_.pc)
   val inst      = io.instFifo.inst.map(_.inst)
   val inst_info = decoder.map(_.io.out.inst_info)
+  val priv_mode = io.csr.priv_mode
 
   for (i <- 0 until (config.decoderNum)) {
     decoder(i).io.in.inst := inst(i)
@@ -111,8 +112,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
 
   val int = WireInit(0.U(INT_WID.W))
   BoringUtils.addSink(int, "intDecoderUnit")
-  io.executeStage.inst0.ex.int.zip(int.asBools).map { case (x, y) => x := y }
-  val hasInt = int.orR
+  io.executeStage.inst0.ex.interrupt.zip(int.asBools).map { case (x, y) => x := y }
 
   io.executeStage.inst0.valid     := !io.instFifo.info.empty
   io.executeStage.inst0.pc        := pc(0)
@@ -129,10 +129,24 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   )
   io.executeStage.inst0.ex.flush_req    := io.executeStage.inst0.ex.excode.asUInt.orR
   io.executeStage.inst0.ex.excode.map(_ := false.B)
-  io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
-    !hasInt && !io.instFifo.info.empty
+
+  io.executeStage.inst0.ex.excode(illegalInstr)        := !inst_info(0).inst_valid
   io.executeStage.inst0.ex.excode(instrAccessFault)    := io.instFifo.inst(0).acc_err
   io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
+  io.executeStage.inst0.ex.excode(breakPoint) := inst_info(0).inst(31, 20) === privEbreak &&
+    inst_info(0).op === CSROpType.jmp
+  io.executeStage.inst0.ex.excode(ecallM) := inst_info(0).inst(31, 20) === privEcall &&
+    inst_info(0).op === CSROpType.jmp && priv_mode === ModeM
+  io.executeStage.inst0.ex.excode(ecallS) := inst_info(0).inst(31, 20) === privEcall &&
+    inst_info(0).op === CSROpType.jmp && priv_mode === ModeS
+  io.executeStage.inst0.ex.excode(ecallU) := inst_info(0).inst(31, 20) === privEcall &&
+    inst_info(0).op === CSROpType.jmp && priv_mode === ModeU
+
+  io.executeStage.inst0.ex.tval := Mux(
+    io.executeStage.inst0.ex.excode(instrAccessFault) || io.executeStage.inst0.ex.excode(instrAddrMisaligned),
+    io.instFifo.inst(0).pc,
+    0.U
+  )
 
   io.executeStage.inst0.jb_info.jump_regiser     := jumpCtrl.out.jump_register
   io.executeStage.inst0.jb_info.branch_inst      := io.bpu.branch_inst
@@ -153,11 +167,26 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
       forwardCtrl.out.inst(1).src2.rdata,
       decoder(1).io.out.inst_info.imm
     )
+    io.executeStage.inst1.ex.flush_req    := io.executeStage.inst1.ex.excode.asUInt.orR
     io.executeStage.inst1.ex.excode.map(_ := false.B)
-    io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
-    !hasInt && !io.instFifo.info.almost_empty
+
+    io.executeStage.inst1.ex.excode(illegalInstr)        := !inst_info(1).inst_valid
     io.executeStage.inst1.ex.excode(instrAccessFault)    := io.instFifo.inst(1).acc_err
     io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
+    io.executeStage.inst1.ex.excode(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
+    inst_info(1).op === CSROpType.jmp
+    io.executeStage.inst1.ex.excode(ecallM) := inst_info(1).inst(31, 20) === privEcall &&
+    inst_info(1).op === CSROpType.jmp && priv_mode === ModeM
+    io.executeStage.inst1.ex.excode(ecallS) := inst_info(1).inst(31, 20) === privEcall &&
+    inst_info(1).op === CSROpType.jmp && priv_mode === ModeS
+    io.executeStage.inst1.ex.excode(ecallU) := inst_info(1).inst(31, 20) === privEcall &&
+    inst_info(1).op === CSROpType.jmp && priv_mode === ModeU
+
+    io.executeStage.inst1.ex.tval := Mux(
+      io.executeStage.inst1.ex.excode(instrAccessFault) || io.executeStage.inst1.ex.excode(instrAddrMisaligned),
+      io.instFifo.inst(1).pc,
+      0.U
+    )
   } else {
     io.executeStage.inst1 := DontCare
   }
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index 0f0f343..26bc31a 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -82,11 +82,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc
   io.csr.in.inst(1).ex := io.writeBackStage.inst1.ex
 
-  io.fetchUnit.flush := Mux(
-    io.csr.out.flush,
-    io.csr.out.flush,
-    io.writeBackStage.inst0.inst_info.op === EXE_MTC0 && io.ctrl.allow_to_go
-  )
+  io.fetchUnit.flush    := io.csr.out.flush
   io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
 
   io.ctrl.flush_req := io.fetchUnit.flush