From ca1a6abe7b5f66945f72d4309d0f14d97e270d9e Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Sat, 11 May 2024 14:49:38 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8Dmem=E8=A2=AB=E9=98=BB?=
 =?UTF-8?q?=E5=A1=9E=E6=97=B6=E8=AF=BB=E6=95=B0=E6=8D=AE=E9=94=99=E8=AF=AF?=
 =?UTF-8?q?=E9=97=AE=E9=A2=98?=
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---
 .gitignore                                               | 3 ++-
 chisel/.gitignore                                        | 1 +
 chisel/playground/src/pipeline/execute/ExecuteUnit.scala | 4 ++++
 chisel/playground/src/pipeline/execute/fu/Lsu.scala      | 7 ++++++-
 difftest                                                 | 2 +-
 5 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/.gitignore b/.gitignore
index 82463a8..530703f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,4 +6,5 @@
 *.~vsd
 
 .vscode/
-.metals/
\ No newline at end of file
+.metals/
+.VSCodeCounter/
diff --git a/chisel/.gitignore b/chisel/.gitignore
index 905ee06..795145d 100644
--- a/chisel/.gitignore
+++ b/chisel/.gitignore
@@ -26,3 +26,4 @@ test_run_dir/
 # vscode
 .metals/
 .vscode/
+.VSCodeCounter/
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index f364864..b1621e4 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -5,6 +5,7 @@ import chisel3.util._
 import cpu.CpuConfig
 import cpu.defines._
 import cpu.defines.Const._
+import chisel3.util.experimental.BoringUtils
 
 class ExecuteUnit extends Module {
   val io = IO(new Bundle {
@@ -22,6 +23,9 @@ class ExecuteUnit extends Module {
     val dataSram    = new DataSram()
   })
 
+  val allow_to_go = io.ctrl.ctrlSignal.allow_to_go
+  BoringUtils.addSource(allow_to_go, "exe_allow_to_go")
+
   val valid = io.executeStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
   val fusel = io.executeStage.data.info.fusel
 
diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
index 1b11bf2..4e0ee48 100644
--- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
@@ -115,9 +115,14 @@ class Lsu extends Module {
     )
   )
 
+  val allow_to_go = Wire(Bool())
+  BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
+
+  val addr_last = RegEnable(addr, allow_to_go)
+
   io.dataSram.en    := valid && addr_aligned
   io.dataSram.wen   := req_wmask & Fill(8, is_store)
-  io.dataSram.addr  := req_addr
+  io.dataSram.addr  := Mux(!allow_to_go, addr_last, req_addr) // 在mem被阻塞时，保持原先的读地址不变
   io.dataSram.wdata := req_wdata
 
   val result = Wire(UInt(XLEN.W))
diff --git a/difftest b/difftest
index be00525..2d18d26 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit be00525e85796bf0e8361c8d2de46ba57c460231
+Subproject commit 2d18d26d5c5f4f920184318462589b96ab4e1504