diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 4c9b79b..f5b69c1 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -137,16 +137,17 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val ar_handshake = RegInit(false.B)
   val aw_handshake = RegInit(false.B)
 
-  val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
-  //
-  val data_raddr    = Mux(victim.valid, victim_addr, Mux(should_next_addr, exe_addr, bank_addr))
+  // 是否使用exe的地址进行提前访存
+  val use_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
+
+  val data_raddr    = Mux(victim.valid, victim_addr, Mux(use_next_addr, exe_addr, bank_addr))
   val replace_wstrb = Wire(Vec(nway, UInt(AXI_STRB_WID.W)))
   val replace_waddr = Mux(victim.valid, victim.waddr, bank_addr)
   val replace_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata)
 
   val replace_way = lru(index)
 
-  val tag_raddr = Mux(victim.valid, victim.index, Mux(should_next_addr, exe_addr, index))
+  val tag_raddr = Mux(victim.valid, victim.index, Mux(use_next_addr, exe_addr, index))
   val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
   val tag_wdata = RegInit(0.U(tagWidth.W))
 
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index 8877f2d..3fcf230 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -84,14 +84,14 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val valid = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(nindex)(false.B)))))
 
   // * should choose next addr * //
-  val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
+  val use_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
 
   // 读取一个cache条目中的所有bank行
   val data        = Wire(Vec(nway, Vec(nbank, Vec(instBlocksPerBank, UInt(AXI_DATA_WID.W)))))
-  val data_rindex = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
+  val data_rindex = io.cpu.addr(use_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
 
   val tag       = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
-  val tag_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
+  val tag_raddr = io.cpu.addr(use_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
   val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
   val tag_wdata = RegInit(0.U(tagWidth.W))
 
@@ -213,7 +213,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   rready <> io.axi.r.ready
 
   val acc_err  = RegInit(false.B)
-  val addr_err = io.cpu.addr(should_next_addr)(XLEN - 1, PADDR_WID).orR
+  val addr_err = io.cpu.addr(use_next_addr)(XLEN - 1, PADDR_WID).orR
 
   when(acc_err) { acc_err := false.B }
   io.cpu.acc_err := acc_err //TODO：实现cached段中的访存错误